SEMI 半导体产业网 Semiconductor and System Technology: A Future of Consolidation, Integration, and Discontinuities. Dr.

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1 Semiconductor and System Technology: A Future of Consolidation, Integration, and Discontinuities Dr. Gary Patton Vice President IBM Semiconductor Research & Development Center East Fishkill, New York

2 Accelerating Advances in Technology Moore s Law: doubling of chip integration every months 2

3 Exponential Technology Change If automobiles were like chips: miles per gallon of gasoline * mpg ,500 mpg ,000 mpg Million mpg * 15 MPG = 6 Km per Liter 3

4 Driving Force: Economics Smaller features Better performance & cost/function More applications Larger market 1962 $1B 1978 $10B 1994 $100B Goble Semiconductor Sales ($B) 4

5 Voltage, V / α The End of Traditional CMOS Scaling tox/α GATE WIRING W/α Why must we follow the recipe at left? We put 1,000,000 times as many devices on a modern chip versus 40 years ago This recipe describes how to reduce each device s power by a factor of 1,000,000 and keep total chip power CONSTANT. n+ source n+ drain L/α p substrate, doping α*na xd/α SCALING: Voltage: V/α Oxide: t ox /α Wire width: W/α Gate width: L/α Diffusion: x d /α Substrate: α N A R. H. Dennard et al., IEEE J. Solid State Circuits, (1974). RESULTS: Higher Density: ~α 2 Higher Speed: ~α Power/ckt: ~1/α 2 Power Density: ~Constant ATOMS DON T SCALE! 11Å Approaching atomistic and quantummechanical boundaries 5

6 The Power Problem; an Industry Dilemma Module Heat Flux (watts/cm 2 ) Junction Transistor Integrated Circuit Vacuum tube IBM 360 Water Cooling Bipolar Year of Announcement CPU 1 CPU 2 CMOS L2 Cache Multi-Core SoC / edram Low-Power Multicore Opportunity for 3D Si 3D Integration 6

7 Spending (US$B) $300 $250 $200 $150 Where Else Is Power An Issue? Power Usage in IT; Another Paradigm Shift Worldwide IT Spending Trend Power and cooling costs Server mgmt and admin costs New server spending Installed Base (M Units) Datacenter power demands are growing at unsustainable rates 1.2% of global electrical output is used by servers & cooling $100 $50 $ Source: IDC, Virtualization 2.0: The Next Phase in Customer Adoption, Doc #204904, Dec Post bubble, spending on datacenter power is growing % faster than spending on servers. In excess of 80% of Datacenter power is wasted 7

8 POWER-Net-Net Affordable/achievable datacenter Power and Cooling solutions are already the top challenges facing IT executives. Energy costs will spiral beyond Server Capex as the core issue facing CFO s at IT intensive Fortune 500 companies. Geo-political issues around energy supplies will only make this problem worse, and sooner than expected. 8

9 Where are we going? 9

10 The Discontinuity Then Scaling drove down cost Scaling drove performance Performance constrained Active power dominates Independent R&D Now Scaling drives down cost Materials Innovation drives performance Power constrained Standby power dominates Collaborative R&D 10

11 Breaking from the Past, Innovation Drives Performance Gain by Traditional Scaling Gain by Innovation Relative % Improvement 100% 80% 60% 40% 20% 0% 180nm 130nm 90nm 65nm 45nm 32nm 11

12 Materials Innovations Elements Employed in Silicon Technology Since the 90 s Beyond 2006 Before 90 s 12

13 One must Drive Performance Through Innovation Novel Materials, Structures, Processes, and Architecture Copper Nobel Prize, STM SOI Atomic Manipulation Strained Silicon Dual Core Highest Carbon Resolution Nanotube STEM Transistors Immersion Self Assembly Frozen SiGe Chip Slowing Speed of Light High-k Nanotube IC 3D Chip Stacking edram Molecular Processing Atomic Storage Airgap Nanophotonic Switch 13

14 The Lithography Challenge λ = 436nm Opportunities wavelength / NA (nm) λ = 365nm λ = 248nm λ = 193nm λ = 193nm immersion λ gap EUV: source? High NA materials? Imprint masks, overlay, breadth? ebeam throughput? Year Low K 1 imaging Computational Scaling! Density scaling has historically been driven by a 10%/year scaling of λ / NA. The next λ 13.5nm (EUV) will not be ready for the 22nm logic node. 14

15 Center for Semiconductor Research, Albany EUV Alpha Scanner 15

16 193 nm Optical Lithography Evolution: Lower k 1 Factors Design = Mask Mask + Correction + Assist 2 Masks + Correction + Assists Optimized Mask(s) + Optimized Source 90 nm 65 & 45 nm 32 & 28 nm 22 nm & Beyond Design (M1 SRAM) Mask Wafer / Contour Mask 23 Co-optimization Designs Get More Regular, Resolution Enhancement Techniques Get More Complex 16

17 Modeling at Unprecedented Levels of Sophistication is Required Illumination Source 45 nm cell: sub μm 2 Mask Optical Imaging Patterned Photoresist mask light just over photoresist light just under mask 1 st Wafer Prediction Design Results 32 nm cell: sub μm 2 22 nm cell: sub μm 2 Etching developed photoresist 17

18 The Value of Computational Scaling Time to Market Avoids need for next generation lithography by extending 193nm. Avoids churn in design rules via design-technology co-optimization. Early optimization of standard libraries. Cost Containment Minimizes the use of multiple exposure imaging processes. Fewer design re-spins due to less complex set of design rules. Access to Computational Scaling Technology Ecosystem of suppliers to support Computational Scaling. Commercially available tools from IBM and Computational Scaling supplierpartners. 18

19 Innovation at Back-End-Of-Line On-chip wiring is a critical limiter to chip advancement Reducing dielectric k to: Increase on-chip signal speed Reduce power consumption Airgap allows ~35% capacitance reduction, to keff ~ /22 nm 32 nm 45 nm 65+ nm Air gap k < 2.0 Porous ultra-low k k = Porous low k k = Low k k = x Wire RC Delay (ps/mm 2 ) X wire RC delay (a.u.) nm 45nm 32nm 22nm Industry RC IBM RC IBM RC w/gaps 19

20 First Successful Demonstration of an Active Chip with Airgap Wiring Mazes (composite) 35% wiring capacitance reduction to k eff ~2.0 Performance improvement and power reduction First implementation of self-assembly nanotechnology for sub-lithographic patterning in semiconductor fab 8x 8x 4x This airgap CPU prototype module currently runs in an IBM server Self assembly material, treated like a typical photoresist 4x 2x 2x 1x 1x 1x 1x Airgap of all Cu wiring levels 20

21 Multilevel Airgap Wiring Self Assembly from Lab to Fab 21

22 High-k k / Metal Gate - A Key Enabler for Scaling Gate scaling extendable to 22nm Achieve higher device performance / lower power 4 nm Device TEM Metal Gate High-K Silicon >100x gate leakage reduction with HKMG High-k / Metal Gate: AC Performance Gate Leakage Curent (A/cm 2 ) 10 7 Measured at 1.2 V 10 5 HKMG 32nm Poly/SiON HKMG 22nm nm 32nm Inversion Thickness (Å) 22

23 22 nm & Beyond: Leadership Innovation FINFET ETSOI HfO 2 Si NW deposited Si Si Nano-Wire C Electronics 15 nm 11 nm 8 nm 5 nm 3 nm 23

24 IBM alliance extends Moore s law to 22nm The world smallest SRAM cell with area of <0.1um 2 2 nd Generation High-k/Metal Gate enables less than 25nm gate length 22nm node ground rule with 90nm gate pitch Conventional high-na immersion lithography for patterning 25nm Gate 90nm Gate Pitch Gate to contact <20nm Thin NiSi 45nm SOI Contact ~26 nm 24

25 The Evolution of CNT-FETs 1998 Source Nanotube SiO 2 Drain The first CNTFET 2001 Fully-integrated complementary circuit 2002 The first self-aligned and doped CNTFET 2002 The first logic gate Schottky barriers The first top-gated CNTFET P. Avouris et al., (IBM). 25

26 Electrical BW Bottlenecks Optics Opportunities Electrical Buses become increasingly difficult at high data rates (physics): Increasing losses & cross-talk ; Frequency resonant affects Optical data transmission: Power Efficiency, much less lossy, not plagued by resonant effects BW (GB/s) Off-card Bandwidth, GB/s Optical Backplane: 10 GB/s, 62.5μm pitch Estimated Limit of MCM Electrical Escape BW Limit of Electrical Backplane BW Core 2 Core 2 Core 2 Core 2 Core 4 Core 8 Core 16 Core System or Time 32 Core Rack Backplane Module Card μp OPTICS μp MULTI CHIP MODULE CIRCUIT BOARD 26

27 Exploiting 3D Integration, Memory and Optics 3D Integration (w/ PCM, optics, heterogeneity) allows restructuring the compute node, to leverage memory (50-70% system costs) to dramatically increase bandwidth and capacity, resulting in significant performance improvement, with necessary software coevolution/adaptation Optics: Multi-cores require huge bandwidth, but the cost of optics is dropping rapidly, allowing Optics to move inside the system: rack to card to chip CMOS integrated silicon photonics can provide large power savings for on-chip interconnects Off-chip optical signals Optical I/O On-chip optical traffic Photonic Plane Memory Plane Logic Plane Logic plane Memory plane Photonic plane ~300 of cores ~30GB edram On-Chip Optical Network >1Tbps optical on-chip >1Tbps optical off-chip 27

28 3D- Integration Technologies IBM Research 28

29 Holistic Design: A New Paradigm in Value Creation Innovation from Atoms to Software The simultaneous optimization of: Materials, Devices, Circuits, Cores, Chips, System Architecture, System Assets and System Software Provides the most effective means to optimize the value of IT offerings to the end user Note: Execution relies upon the seamless integration of skills from across the spectrum 29

30 BlueGene/L Holistic Design in Practice Cabinet (32 Node boards, 8x8x16) System (64 cabinets, 64x32x32) Node Board (32 chips, 4x4x2) 16 Compute Cards >131,000 Processors Chip (2 processors) 2.8/5.6 GFLOPS 4 MB Compute Card (2 chips, 2x1x1) 11.2 GFLOPS 0.5 GB DDR 180 GFLOPS 8 GB DDR 5.7 TFLOPS 256 GB DDR 360 TFLOPS 16 TB DDR Using the industry-standard LINPACK benchmark, the IBM Blue Gene/L system attained a sustained performance of Teraflops, eclipsing the three year old top mark of Teraflops for the Japanese Earth Simulator and the recent mark of 42.7 Teraflops at the NASA's Ames research center. The BlueGene/L system is 1/100th the physical size (320 vs 32,500 square feet) and consumes 1/28th the power (216KW vs 6,000KW) as compared to the Earth Simulator. 30

31 Innovation: The Business Aspect

32 Is There a Sustainable Business Model? The industry trend as of today: R&D Expenses far outpace revenues ~$2.3B Projected CAGR Revenues ~ 6.5% 1,800 Estimated cost to develop the 22-nm CMOS logic process R&D ~ 12.2% 1,600 R&D Expenses 12.2% CAGR This is NOT sustainable, and will/must NOT happen. Revenue Growth 6.5% Costs ($M) 1,400 1,200 1, Process development $1.1B Process ramp-up extrapolated Fiscal reality is driving industry towards consolidation around Innovation Networks nm 130nm 90nm 65nm 45nm 32nm 22nm Source: IBS Global System IC Service Management Report, April

33 Globalization of Semiconductor R&D is Already a Pervasive Strategy Intel AMD Freescale IMEC Infineon Sony Phillips IBM Albany STM Toppan Toshiba SELETE, ASET NEC SEMATECH TSMC Chartered IBM & alliances Major Consortia-IMEC&SEMATECH There is a global recognition of challenges facing semiconductor industry, having already driven a its dramatic consolidation => Pre-competitive cooperation 33

34 Strategic Development Alliances: CAPEX Landscape $35 $30 $25 $20 $15 $10 $5 $ Semiconductor CAPEX (non-dram), $B $33.22 $19.08 $12.65 $8.06 $1.63 $4.83 $4.70 IBM Technology Alliances IBM Chartered Samsung Infineon AMD Sony Toshiba Freescale ST Micro Intel ASPLA TSMC Crolles Alliance Notes: Fujitsu NEC Matsushita Electric Renesas NXP UMC Freescale and STMicro have announced they are partnering with IBM; NXP has announced they will leave Crolles alliance at the end of 2007 essentially dissolving the Crolles alliance TI has announced they will cease investing in digital process technology development and will rely on their Foundry partners for process technology. Source: IBM MI, IC Insights August 2007 TI 34

35 Technology Collaboration Innovation Flow Bringing Research to the Market Fundamental Research Advanced Semiconductor R&D Technology Development Worldwide Manufacturing Screen new materials & processes Innovation in integrated device & process technology Multi-company co-located joint development Process synchronized fabricators (GDSII compatible) Patterning solutions High-k / metal gate Device structures Stress techniques Interconnects Ultra low-k Packaging IBM Almaden & Yorktown Equipment Applied Mat ls, ASML, Tokyo Electron Research IBM, AMD, ST, Toshiba, NEC Albany Nanotech Center Foundry bulk IBM, Chartered, Infineon, Samsung, AMD, ST, Toshiba, NEC High perf SOI IBM, AMD, Freescale IBM East Fishkill 35 Foundry bulk IBM, Chartered & Samsung High perf SOI IBM & Chartered USA, Singapore, Korea

36 Albany NanoTech Panoramic and aerial views of the College of Nanoscale Science and Engineering (CNSE) facilities, which houses the Center for Semiconductor Research (CSR) Line where IBM is performing 22nm advanced semiconductor research and development NanoFab South Annex (NFX) NanoFab North (NFN) NanoFab East (NFE) NanoFab South (NFS) 36

37 Common Platform Technology Ecosystem Packaging Design Compatibility GDSII Compatibility Design Center Collaborators Reference Design Flows Libraries and IP Technology Design Kits Process and Manufacturing Compatibility Design Manual SPICE Models 90 nm, 65 nm, 45 nm, 32nm Process Platforms 37

38 Summary Innovation & collaboration key to solve technology challenges of future nodes New device structures, advance dielectrics, and computational scaling Long-term investment in fundamental research Access to state of the art 300mm facilities for both research & development Collaboration brings together skills in technology R&D, design, and manufacturing needed to solve these challenges. Technology-Design co-optimization needed to achieve product objectives at 32nm and beyond Early engagement with product design teams on IP development 38