Industry Trends in 3D and Advanced Packaging

Transcription

1 Industry Trends in 3D and Advanced Packaging

2 Outline Industry System and Component Challenges & Trends 3D and Advanced Packaging Value-proposition and Client Examples 3D Technology Details 3DIC / 3DTSV Markets 2

3 The Future of Data Rates 1 Terabit Ethernet 100 Gigabit Ethernet 10 Gigabit Ethernet 1 Gigabit Ethernet Source: IEEE BWA Report 12 3

4 Module Heat Flux (watts/cm 2 ) As GHz (classical scaling) went up in power, new innovation drives performance Bipolar CMOS CP U 1 CPU 2 L2 Cache Multi-Core SoC / edram Lower-Power Multi-re Junction Transistor Integrated Circuit Vacuum tube IBM 360 Water Cooling Year of Announcement? Innovation Required 3D, FinFET s, Optics

5 Traditional Migration: Drive To Better Performance Seminductor Migration Wafer Fabs expensive $7 $10 Billion New process nodes every 2 years Short life for leading edge PCB limiting system performance Source: Semi Research, Dec. 11 5

6 Clock Speed (Arb.) Performance (Arb.) 3D Motivation Four Drivers Multi-re Solution to Achieve Performance As clock frequency flat lines, multi-re extends performance Single thread performance growth >4 Core slows significantly 4 Core 1 Core 2 Core 10 Historical Growth Historical Trend Growth Trend=45% per year Single But multi-res beme starved for data at some point in time (I/O limited) 6

7 A New Way to Achieve Performance 200mm 300mm Mixed technology 3D Packaging 3D packaging up to 10X system performance Will extend process node and wafer size life Be a catalyst for new applications Allow for smaller form factor Need to improve price points Source: Semi Research, Dec. 11 7

8 ++Perf --Pwr Traffic Mgmt IBM ASIC (w/ edram, HSS) System and Component Challenges and Trends Switch-Router/Transport/MI QDR DRAM TCAM DRAM NPU/Packet Engine IBM ASICs (w/ edram, etcam, HSS) Switch I/F Traffic Mgmt NPU MAC Port PHY CP Control Processor/SoC IBM ASICs (ARM or PPC SoCs) w/ partner IP Inflection points Exponential growth Exponential increase in data rate Throughput scaling, Port density, Computing/Watt Exponential increase in power density Demand for QoS - B/W guarantee & lowlatency Real-estate premium - rack & floor space Telem CO, Enterprise data center Solution trends - Integration Functional Integration Monolithic Multi-use, DE amortization Digital CMOS Mixed-signal SoCs Non-monolithic -- More than Moore SIP, 3D stack, MCM Memory & PHY integration (40Gbps & 100Gbps) Architectural Integration SoCs w/ edram -- Multi-re, multi-thread Control & Data plane nvergence; virtualization Clock gating, Voltage island 8

9 Outline Industry System and Component Challenges & Trends 3D and Advanced Packaging Value-proposition and Client Examples 3D Technology Details 3DIC / 3DTSV Markets 9

10 STG Advanced Packaging Market Trends The slowing of Moore s Law forces the market to higher integration which leads to larger die. Networking and mobile architects are moving to 3D stacking, 2.5D and multi-chip module (MCM). Heterogeneous integration of multiple technologies. Organic MCM Silin Interposer 3D TSV Apr IBM Corporation

11 What does 3D integration buy for you? Performance Reduced internnect length z direction latencies are smaller Improved transmission speed (reduced parasitic) Power Drive smaller internnect loads Reduced power nsumption Form Factor Reduced footprint, volume and weight Improved integration density TSV internnect overmes the space limitations of POP & SiP packages. Heterogeneous Integration Enable More than Moore Integration of different technologies Integrate different functional layers (RF, memory, logic, MEMS, imagers, etc.) based on different optimized process nodes 11

12 STG Range of Advanced Packaging Solutions Several approaches to meet More Than Moore performance requirements. Key attributes: 1. High bandwidth 2. Low power I/O 3. Low latency Organic MCM Silin Interposer Relative Aggregate Bandwidth on Module 3D Module ~5Tbps ~10Tbps ~100Tbps Logic Laminate Package Lid Logic TSV die Logic Sensor Sensor Sensor Sensor Thin re laminate Apr IBM Corporation

13 Advanced Packaging Product Announcements 3D early manufacturing is happening now In 4Q10 IBM announced a custom silin interposer development project with Semtech. In 4Q11 IBM announced manufacturing of a custom 32nm 3DIC logic die for Micron s Hybrid Memory Cube (HMC). Xilinx shipping high end FPGA silin interposer product today. 13

14 Customer Example: ADC/DSP Platform High-performance ADC/DSP platform The platform will use IBM s 3-D interposer technology to internnect ADC functions in IBM custom logic SOI-based Cu-45HP technology with interleaver ICs in IBM s 8HP BiCMOS SiGe technology. These two different technologies are nnected through a single wiring layer on an interposer, which supports a bandwidth of greater than 1.3Tbps in this design. IBM s 3-D technology mbines 90-nm BEOL (back-end-ofline) wiring levels for high speed signaling between die as well as providing ultra high capacitance density by integrating deep-trench (DT) capacitors at the top surface of the interposer. 100Gb Optical transport mponent Challenge of PCB parasitic at high data rate Issue of signal integrity & noise Form-factor nstraints Applications Fiber optic telemmunications High performance RF sampling and filtering Test equipment instrumentation Sub-array processing for phased array radar systems. 14

15 Request Write Data Customer Example: Micron HMC Gen2 Vault Control Memory Control DRAM Sequenc er Refresh Controll er Tx Link Interface Controller Writ ECC e Buffe r ECC Read Buffe r Read Data Crossbar Switch Rx Link Interface Controller MPU TSV Repair DRAM Repair I/F PHY Host Links PHY Rx Tx HMC is a new class of memory -- Serial Memory 10x better throughput than DDRx memories 30% pin reduction mpared to DDRx memories Higher capacity, smaller footprint 15

16 Example: Organic MCM with a edram and Logic Die Logic mm x 17.55mm edram 11.02mm x 16.96mm Package 2892pin FCPBGA 57.5 mm body size, 1.0mm 55mm x55mm FCPBGA Off Module IO 64 lanes 25G Serdes 144 lanes 15G pi Serdes 64 lanes 30G Serdes W HS30GBF0 HS30GBF0 4 4 HS30GBF0 8 HS30GBF0 HS30GBF0 4 4 HS30GBF0 HS30GBF0 HS30GBF0 HS30GBF0 HS30GBF Aggregate Bandwidth Die to Die >4Tbps Off Module >1Tbps _3 _4 _1 _ G S e r d e s X G S e r d e s

17 Possibilities for Advanced Organic MCMs Mix and match die to create integrated product. Requires a multiple partner esystem around an industry standard I/O and package. Values: 1. Greater performance due to serial I/O running at high frequency, >10Gbps 2. Lower power mmunication with use of ultra short reach I/O 3. Flexibility to create products with heterogeneous die Logic HMC FPGA Sensor 17 System on an organic package

18 Outline Industry System and Component Challenges & Trends 3D and Advanced Packaging Value-proposition and Client Examples 3D Technology Details 3DIC / 3DTSV Markets 18

19 3D Technology Options at IBM Shorted TSVs 200mm wafers SiGe and RF technologies on wafer TSVs short together through the silin wafer Insulated TSVs 300mm wafers Silin interposer without active devices 32nm, 22nm or 14nm CMOS on wafer TSVs insulated from bulk silin and each other 19

20 Shorted Tungsten TSV Array* * Polysilin can be substituted for W X-Section View Optical Image Top View Angled X-Section View 20

21 Insulated Cu TSV Structures MODULE LID TOP CHIP ORGANIC LAMINATE TOP CHIP THINNED BOTTOM CHIP C4 IEDM 2011, Farooq et al. 21

22 TSV Allows Top and Bottom Electrical Connection BEOL Devices TSV Top down view X-section view 22

23 Detailed TSV Integration Cu 13 level Cu 12 level Cu 11 level E1 Via Capture level 23 TSV Bottom TSV Active chips with 13 levels of metal TSVs nnect to last few levels of metal IEDM 2011, Farooq et al.

24 Outline Industry System and Component Challenges & Trends 3D and Advanced Packaging Value-proposition and Client Examples 3D Technology Details 3DIC / 3DTSV Markets 24

25 Interposer & 3D TSV IC Application Roadmap Server Memory Computing Infrastructure GPU Routers Base stations Central Office Switch High-end SmartPhones Tablet PC Notebooks Source: Semi Research, Dec. 11

26 Hype Cycle for Seminductors 26 Source: Gartner (July 2011)

27 TSV Market Forecast 27

28 Mobile Computing Handsets, Smart phones, Tablets, etc. Power Cntrl. SPXT Switch 3G iphone PA PA PA PA TV Tuner Transceiver/ABB GPS BT2.0 WLAN/ WiMax Power Management Digital Baseband Processor (s) Applications Processor (s) Memory Source: Openmoko, Aug

29 Wide IO DRAM (JEDEC JC42.6) WideIO DRAM die is stacked on top of the mobile processor in the same package to reduce internnect capacitance Face-to-Back stacking with Through Silin Vias (TSVs) in the mobile SoC flip-chip die Source: ST-Ericsson 29

30 3D and Advanced Packaging Availability from IBM J. Golz, et al., 2011 Symposia on VLSI Technology and Circuits TSV 32nm High-K CMOS 11 level metal Deep trench capacitor Cu Through Silin Via (TSV) Silin Interposer IBM plans to use this technology internally as well making it externally availability. In production with organic multi-chip modules Successfully built stacked 32nm edram module (2011 VLSI Technology Paper, Golz) TSV technology passed extensive reliability testing (IEDM 2011, Farooq) Integrated 3D design rules into 32nm design system Client 3D and silin interposer designs in progress and prototypes for products in build 30

31 References Gartner Market Definitions and Methodology Seminductor Devices & Applications 18-Jan-11.pdf Gartner Hype Cycle for Seminductors and Electronics Technologies, July-11.pdf Gartner Forecast Memory, Worldwide, , 3Q11 Update 19-Sep-11.xls Gartner Market Share Seminductor Memory, Worldwide, Apr-11.xls Gartner Forecast Seminductor Consumption by Electronic Equipment Type, Worldwide, 4Q11 Update.xls Gartner Forecast Analysis Seminductor Outsourcing Services, Worldwide, , 3Q11 Update 26-Sep-11.pdf Linley Communications Seminductor Market Forecast Aug 2010.xls Linley Communications Seminductor Market Share, 2010 June '11.xls isuppli Wireless Communications Q Topical Report - AFT-CD Database.xls isuppli Smart Phones & Converged Devices Q Market Tracker Database.xls 3D Copper TSV Integration, Testing and Reliability, M. G. Farooq et al., International Electron Devices Meeting, Dec D Stackable 32nm High-K/Metal Gate SOI Embedded DRAM Prototype J. Golz, et al., 2011 Symposia on VLSI Technology and Circuits. 31