Physical Design Issues in Biofluidic Microchips

Transcription

1 Physical Design Issues in Biofluidic Microchips Tamal Mukherjee MEMS Laboratory ECE Department Carnegie Mellon University Pittsburgh, PA, USA cmu edu/~mems Carnegie Mellon ISPD, April 16, 2008

2 Tubes to Chips: ICs Driven by Information Processing needs IBM 701 calculator (1952) Intel 4004 Calculator IC (1971) 2

3 Tubes to Chips: BioChips Driven by Biomolecular Analysis needs Image from Barnard College Archives Test tubes & Beakers Agilent DNA analysis (1950) Lab on a Chip (1997) 3

4 Portable Analysis New knowledge of molecular basis of biology e.g. Human Genome Project Massively parallel analysis infrastructure Integration and miniaturization will drive biomolecular analysis instrumentation Biomolecular Spock with Tricorder mainframes Sensor + computer Burns Science

5 Typical Biological Lab Functions Synthesis Analysis A B C A+B A+B A B Mixing Reaction Separation 5

6 Microdevice Technology Summary BioMEMS BioChips Lab-on-a Chip Droplet Channel Pressure Electrokinetics 6

7 Channel-based LoC: EK drive What is Electrokinetics? Voltage driven flow Flow direction Why Electrokinetic flow? Plug velocity profile Portable kv sources EK flow can be used for electrophoresis EK flow already used in complex designs EK flow Pressure flow Serial Mixer ORNL 7

8 Microdevice Technologies: LoC Miniaturized Bio-chemical Lab-on-a-Chip Individual functional units demonstrated Analyzer, Reactor, Research driven by integration Design aids needed to handle complexity! Amino-Acid Analysis DNA Analysis Chemical Synthesis Immunoassay ORNL U. C. Berkeley U. Hull U. Alberta 8

9 Outline Introduction Motivation for Design Automation Design Hierarchy Multi-function System Simulation Multi-plex Physical Synthesis Summary 9

10 Multiplex Lab-on-a-Chip Same subsystem, integrated for redundancy, combinatorial i experiments integration year 10

11 Multifunction LoCs Example: Immunoassay 1. Load sample {Ag*, Ag} 2. Mix with reagents {Ab} 3. Rxn: Ag* + Ab Ag*-Ab Ab mixing 4. Inject sample plug 5. Separate analytes 6. Detection {[Ag*,Ag], Ab, Ag*-Ab} reaction injection loading reagent buffer separation sample waste detection buffer waste 11

12 Complexity Hierarchy Element Functional Subsystem System Component Increasing Integration 12

13 Outline Introduction Motivation for Design Automation Design Hierarchy Multi-function System Simulation Multi-plex Physical Synthesis Summary 13

14 Simulation Techniques Computational fluid dynamics One single turn Complimentary turns buffer Buffer Sampl e sample Flow direction Flow direction ~ 10 Hours 2~3 days ~ 10 hours Reduced order models Hierarchical decomposition and parameterization Capture geometric effects Amenable for use in design Serial Mixer (ORNL) 14

15 Hierarchy Example: Immunoassay Sample Buffer V+ Ag*, Ag V+ Flow Direction V- Mixing and Reaction Ag* + Ab Ag*-Ab Sample Waste Pinching Ab Ag*, Ag, Ab, V+ Ag*-Ab Ab V+ Buffer Waste 15

16 Synthesis Phase: Steady State Buffer V+ V+ Flow Direction V- V+ Mixing and Reaction Ag* + Ab Ag*-Ab Pinching Sample Waste Ag*, Ag, Ab, Ag*-Ab Ab V+ Buffer Waste 16

17 Analysis Phase: Transient V- Buffer V+ Flow Direction Sample Plug Mixture of Ag*, Ag, Ab, Ag*-Ab lv- V- Sample Waste Separatio on Channe V- Buffer Waste 17

18 Analysis Phase: Transient V- Buffer V+ Flow Direction V- Sample Waste Ag*-Ab Ab Ag*,Ag lv- Separatio on Channe Resolution = distance apart band broadness V- Buffer Waste 18

19 Component Library Library of LoC Unit Operations Compose Topology Function Type well mixer reactor injector separator splitter 19

20 Composition Examples Buffer Sample Sample waste A B Serpentine separation chip (ORNL) Multi-stream t mixer (M. Koch, et al.) System waste Spiral chip (ORNL) System waste Sample wa aste Buffer Sample Buffer A 1 A 2 A 3 A 4 A 5 Sample Waste-2 Was ste-1 Serial Mixing network (S.C. Jacobson, et 20al.)

21 Outline Introduction Motivation for Design Automation Design Hierarchy Component Models Multi-function System Simulation Multi-plex Physical Synthesis Summary 21

22 Simulating a Multifunction Design (Cheim, Clin. Chem., 44:3, , 1998) Real Immunoassay Chip from U. Alberta Operation Mixing/Dilution Reaction Injection Separation Detection Wang et. al. Transducers 05 22

23 Simulation Results 10 mm after injection Calibration curve Re elative concen ntration c Ab-Ag* Th * -Ab complex Area ratio Before turn 0.6 Th * Ag* After turn 1.0 Schematic Experimental E i l Ag* Th * Ab-Ag* Ab-Th * Antigen Theophylline (Ag) Th (mg/l) Time (s) Electropherogram Ag unreacted Ag* Ab-Ag* Simulation matches experiment Simulation time is a few CPU seconds 23 Wang et. al. Transducers 05

24 Optimizing the design: NLP x 0 obj : min f s. t. g( y i ( y ) < 0 h ( y ) = 0 y i i ) x i y i y i = SIM ( x, PARAMS i ) 7.6 cm x * 10x less space Same perf injector reactor 1.22 cm mixer separation channel detector 0.75 cm 2 cm 1.73 cm 1.14 cm 7.6 cm 2.23 cm 2.33 cm Wang et. al. Transducers cm 24

25 Outline Introduction Motivation for Design Automation Design Hierarchy Multi-function System Simulation Multi-plex Physical Synthesis Summary 25

26 Multiplex Physical Synthesis Input: Design Specs Overall Chip Dimensions Species/Buffer properties Operational constraints Chip fabrication Subsystem performance Family of subsystems Final Routed Layout Simultaneously determine: placement dimensions # of sections voltage Intermediate Placement Pfeiffer et. al., TCAD 06 Route subsystems to wells: single layer, planar min. length, bends 26

27 Placement Features Subsystem optimization: NLP System-on-Chip extensions * : * Murata, H. et al., IEEE Trans. on CAD s e c f a d b t e c f a b d Orientation: and Well placement: e a d c Overlap constraints: Pfeiffer et. al., TCAD 06 f b E T e c a d a EL ER c f b E B Never a Penalty a d c b e f e f d b 27 b

28 Routing Features Routing grid graph * : e a d Expand e a d * Lengauer, T., Combinatorial Algs. for IC Layout, 1990 c f b c f b Node constraints: flows in = flows out 1 flow in/out of node (single layer, planar) penalize bends Bend reduction: 5 favor straight paths Pfeiffer et. al., TCAD

29 Multiplex Synthesis Example Placed and Routed Design P&R By Hand Automated Improvement Place: 20 min Time 5+ hrs. Route: 3 min > 10X faster Total: 23 min Dimensionsi cm x cm cm x cm ~ 25X 2.5X smaller Pfeiffer et. al., TCAD 06 29

30 Summary Lab on a Chips integrate bioanalysis functions Hierarchically decomposition used for development of fast, accurate, reusable, parameterized models Relatively few types of band profile on a chip Profile representation to simplify PDE into ODEs Models are reuseable Separation models integrated with P&R algorithms for simultaneous model based placement followed by routing Focus still at circuit -level, need to consider architecture, protocol optimization 30

31 Acknowledgements Collaborators Prof. James F. Hoburg (ECE) Prof. Steinar Hauan (ChE) Prof. Qiao Lin (ME, now at Columbia Univ) Students Anton Pfeiffer, Yi Wang, Ryan Magargle, Xiang He, Bikram Baidya Funding DARPA DSO SIMBIOSYS Program NSF ITR Program 31