applies to general (nontree) RC circuits can be eciently, globally optimized clock meshes busses with crosstalk Contribution dominant time constant as

Transcription

1 Optimal Wire and Transistor Sizing for Circuits With Non-Tree Topology Lieven Vandenberghe (UCLA) Stephen Boyd (Stanford University) Abbas El Gamal (Stanford University)

2 applies to general (nontree) RC circuits can be eciently, globally optimized clock meshes busses with crosstalk Contribution dominant time constant as measure for RC circuit delay example applications: sizing of 1

3 Elmore delay minimization in RC trees dominant time constant minimization in general RC circuits example applications conclusions Outline 2

4 v in v in (t) thres k T v k (t) C > 0, G > 0 (capacitance and conductance matrices) simple model for transistors & wires RC models for digital circuits k 1 0:5 t =,G(v(t), V ); v(0) = 0 dv C dt 3

5 threshold delay (e.g., 50%) power: 1 2 V T C(x)V per transition (i.e., ane in x) area (approximated by ane function of x) Sizing problem design variables: transistor and wire widths C(x), G(x) are ane in design variables x tradeo between... intractable 4

6 v k thres k T delay T elm k Elmore good approximation of 50% delay (for monotonic step resp.) eciently & globally minimized for RC trees geometric programming; c.f. TILOS) (via no useful convexity properties for non-tree circuits The Elmore delay 1 0:5 5

7 0 > 1 2 n : roots of det(c(x) + G(x)) = 0 slowest, i.e., dominant time constant is T dom =,1= 1,1=T dom Dominant time constant node voltages have form v k (t) = 1, P n i=1 ike it good approximation of max threshold delay (usually better than Elmore delay) 6

8 Sizing with dominant time constant constraint T dom T () TG(x), C(x) 0 convex constraint in x (linear matrix inequality) no restrictions on topology (i.e., G, C) example: minimize linear function (e.g., area, power) s.t. upper bound on T dom upper and lower bounds on x i a convex optimization problem (semidenite program) 7

9 convex (but not necessarily dierentiable) constraint Semidenite programming (SDP) minimize c T x subject to F 0 + x 1 F x m F m 0 linear objective function, linear matrix inequality constraint i = F T i 2 R nn ) (F global optimum eciently computed using recent methods interior-point 8

10 Elmore delay minimization in RC trees dominant time constant minimization in general RC circuits conclusions Outline example applications { clock meshes { busses with crosstalk 9

11 quantities of interest: skew, maximum delay, power Clock distribution mesh used in high-performance designs to reduce clock skew DEC alpha) (e.g., non-tree topology: Elmore delay methods nd local [Desai et al., DAC96] optimum 10

12 multiple synchronized drivers variables x i : interconnect widths i x x i minimize power subject to T dom T, 0 x i w max x i Clock mesh example 11

13 T dom small T dom large Power versus dominant time constant 150 T dom globally optimal tradeo curve 100 via semidenite programming power optimal topology varies along tradeo curve 12

14 Q Qs T thres T fastest response A A Q Qs T thres T elm + T dom is a good approximation of max. 50% delay minimizing T dom reduces A AK Two solutions on tradeo curve T dom + T elm 1:0 AK fastest response slowest response slowest response 0:5 0: : :0 13

15 capacitive coupling in deep submicron non-tree topology (non-grounded capacitors) Busses with crosstalk Elmore delay is not a good delay measure (non-monotonic response) step 14

16 s 1 s 2 w13 w14 w15 w12 w11 s12 s13 s14 s15 s11 w21 w22 w23 w24 w25 s21 s22 s23 s24 s25 w31 w32 w33 w34 w35 Example C1 =10 C2 =20 C3 =30 variables: widths w ij, spacing s 1, s 2 coupling capacitances 1=s ij minimize total width s 1 + s 2 subject to bound T dom T, and lower bounds on s ij, w ij upper 15

17 T dom large T dom small Total width versus dominant time constant 140 T dom total width 0 2 globally optimal tradeo curve via semidenite programming 16

18 T dom large T dom v 2 (output line 2) 1 3 v T dom small T dom v v Eect on crosstalk level apply unit step to bus line 2, zero input to lines 1 and , minimizing T dom indirectly reduces crosstalk level 17

19 worst-case: #iterations p problem size in practice: #iterations between 5 and 50 can exploit structure to reduce computation per iteration G(x), C(x) sparse; each entry depends on very few variables can evaluate T dom very eciently using Lanczos algorithm Computational complexity of SDP interior-point methods structure in SDPs arising in circuit sizing 18

20 applies to general (nontree) RC circuits Conclusions dominant time constant as measure for RC circuit delay { multiple sources { loops of resistors { capacitive coupling eciently, globally optimized via semidenite programming no specialized implementation for large-scale problems 19