A 19.4 nj/decision 364K Decisions/s In-Memory Random Forest Classifier in 6T SRAM Array. Mingu Kang, Sujan Gonugondla, Naresh Shanbhag

Transcription

1 A 19.4 nj/decision 364K Decisions/s In-Memory Random Forest Classifier in 6T SRAM Array Mingu Kang, Sujan Gonugondla, Naresh Shanbhag University of Illinois at Urbana Champaign

2 Machine Learning under Resource Constraints Embedded statistical inference: IoT, sensor-rich platforms Decision making under resource constraints Limited form factor, battery-powered, real-time 2

3 The Random Forest (RF) Algorithm Random Forest [1] Ensemble of many (a few hundreds) decision trees High accuracy Simple computation (only comparisons) Suitable for multi-class classifications Inherent error-resiliency (from ensemble nature) RF algorithm [1] L. Breiman, Machine Learning2001 3

4 Implementation Challenges Implementation challenges Non-uniform tree structure - Variations in depth, # of nodes, symmetricity Frequent memory access (,,, - Memory dominates the system efficiency Irregular data access pattern:, RF algorithm Prior Art: Software and FPGA implementations. No ASIC. Fails to take advantage of inherent error-resiliency 4

5 Proposed Solution: Deep In-memory Architecture (DIMA) with DSS DIMA [2-4]: Embedded analog processing Storage density, normal read & write function preserved FR: functional read BLP: bitline processor (subtraction, comparison) CBLP: cross BLP (aggregation) RDL: ADC & residual digital logic Deterministic sub-sampling (DSS) Regularizes memory access pattern [2] M.Kang, et al., ICASSP14 [3] M.Kang, et al., Arxiv16 [4] M.Kang, et al., US Patent no. 9,697,877 5

6 RF Chip Architecture Proposed architecture SRAM bitcell array Stores up to 42 groups Each group has 4 sub-group (1 sub group = 1 tree) Input buffer Stores 4:1 sub-sampled pixels in 4 sections for DSS Cross bar (CB) 31 CB units per sub-group enabled in parallel Comparator (COMP) 128 analog comparators (. ) -IREG: pixel index register, RSREG: RSS register 6

7 Functional READ (FR) Δ Δ Δ 0.5 Δ Conventional read Functional read (FR) -B: bit precision, L: column mux ratio Fetches and computes the linear combination of stored data into analog (LB) times more data access per read & precharge Savings in energy & delay at the cost of reduced SNR 7

8 In-memory Bitline Processing Subtraction 2 Store and in the same column, Comparison: > < : variation due to possible cominations of (T MSB, X MSB ) at the T MSB X MSB value V BL (V) A column of SRAM array X MSB 15 0 T MSB = T MSB X MSB T MSB 0 15 X MSB = Measured subtraction in a 65nm CMOS 8 0

9 Deterministic Sub-sampling (DSS) Random sub-sampling (RSS) Requires complex cross bar (e.g., 256:1 for 256-pixel ) Proposed RF algorithm Deterministic sub-sampling (DSS) before RSS Sub-samples to generate four sub-images,,, Reduces cross bar complexity (e.g., 256:1 64:1) More than 3 and 4 energy and layout area savings 4:1 chosen due to accuracy vs. sub-sampling ratio trade-off 9

10 Application & Measured Results KUL Belgium traffic sign dataset Training (off-chip) 200 images per class employed for training Bit precision: 8, tree depth: 6, 64 trees Testing Randomly chosen 200 testing images from test data set Platform (65nm CMOS) # of trees Max tree Depth Classification rate (decisions/ms) Energy per decision (nj) Energy delay product (fj s) Accuracy (%) Conv. Arch /bank Proposed Arch /bank EDP reduction by

11 Measured Energy vs. Accuracy Trade-off Accuracy vs. # of trees vs. Δ Accuracy vs. energy w.r.t BL swing (Δ )* Accuracy BL swing Energy # of trees error resiliency allows lower BL swing higher energy efficiency *Δ for conv. is 10 Δ per LSB 11

12 Chip Summary & Comparison Chip micrograph Technology Die size SRAM capacity Chip summary 65 nm CMOS mm 16 KB ( bit-cells) Bit-cell size um 2 CTRL CLK freq. Supply voltage (V) 1 GHz CORE 1.0 CTRL 0.75 Prior art [5] [6] Ours (M=64) Process Algorithm 130nm CMOS 14nm tri-gate 65nm CMOS Support vector machine K-nearest neighbor Random forest Comparison with state-of-the-art Dataset Traffic sign video Not reported KUL traffic signs Input size (8b) Throughput (decision/s) 33 [40K]* 21.5M [498.8K]* 364.4K Energy (nj/decision) 1.5M [1250]* 3.4 [145.3]* 19.4 (w/ CTRL) EDP (fjs/decision) 45G [31250]* 0.2 [292.3]* Accuracy 90% Not reported % [5]: J.Park JSSC12, [6]: H.Kaul ISSCC16, *scaled to 65 nm CMOS 12

13 Conclusions First ASIC implementation of RF algorithm low-snr processing via DIMA and DSS Energy & speed benefits 2.2 and 3.1 smaller delay and energy 6.8 smaller EDP compared to digital ASIC Higher potential in large-scale applications # of trees up to a few hundreds in real-life applications Higher error-resiliency More room to scale for energy efficiency Future work On-chip training to compensate process variations Different algorithms (e.g., boosted ensemble classifier) 13

14 Acknowledgment This work was supported by Systems on Nanoscale Information fabrics (SONIC), one of the six SRC STARnet Centers, sponsored by SRC and DARPA. 14