1 ( = 80 points) 50 min. LOAD INI I <= 0; J <= 1; LSA <= 1; DONE. COMP Compare M[I] with PREV

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1 Spring 203 EE457 Intructor: Gndhi Puvvd Quiz (~ 0%) Dte: 2/22/203, Fridy in THH20 Clcultor nd Epern Verilog Guide re llowed; Time: 09:5AM-:45AM (2 Hour 30 Min) Cloed-book/Cloed-note Exm Totl point: 246 Nme: Student ID: Do NOT write ny ID (tudent ID, SSN,..) Perfect core: 230 / 246 ( = 80 point) 50 min. Stte Digrm nd RTL deign: Here we hve n rry of 4 (note: not 6) 8-bit unigned number nd we need to find the longet equence of cing number (LSA) cnning from M[0] to M[3]. If ll fourteen re in cing order, then LSA hould come out to be 4. If there re not even two number in cing order, then LSA hould come out to be (nd not zero). The mllet equence i -number equence. If ll the number re equl to ech other, then LSA = becue "equl" doe not qulify to be cing. Reet Strt INI I <= 0; J <= ; LSA <= ; Strt for previou M[I] LOAD PREV <= M[I]; I <= I + ; Exmple: I: Sequence: ingle-item equence LSA = 5 Thi i till inpected even though there ren t mny item left in the rry 40 DONE No RTL needed here COMP Compre M[I] with PREV Februry 22, 203 5:23 pm EE457 Quiz - Spring 203 / 7 C Copyright 203 Gndhi Puvvd

2 . Beide I, the itertion counter to cce member of the rry M ( M[I]), there i nother 4-bit counter nmed J to count the number of item in the current cing equence. LSA nd J re initilized to in the INI tte hown bove. 2. You cn ue two comprion unit: n 8-bit comprtor to compre M[I] with PREV (PREV for previou M[I]) nd 4-bit comprtor to compre J (or J+, only one t time) with LSA. We do not tret "compring I with 3 or 4" comprtor, it i comprion with contnt nd it doe not require fullfledged comprion unit. Complete the tte digrm on the previou pge. You cn write generic RTL or Verilog in the COMP tte. In either ce, plee ue either {} or.. to mke it cler the cope of "if" or "ele". Note tht you try to updte LSA when the current longet equence h jut ed or the longet equence i continuing but you cme to the of the rry. Thee two itution my differ in term of whether J w updted lredy or being updted. Do you wnt to check J > LSA or J >= LSA or J+ > LSA? Do you wnt to depoit J or J+ in LSA? You do not need to nwer thee two quetion. Thee quetion re to help you to think. 40. Now we redo the bove deign with the retriction of uing only one 8-bit comprtor to compre M[I] with PREV nd lter (in eprte clock or tte) if needed to compre J (or J+, only one t time we hve only comprtor) with LSA. We pp (conctente) 4 zero on the left of the bove 4-bit item to compre them uing the 8-bit comprion unit. Complete the tte digrm below. Reet Strt INI LOAD I <= 0; Strt J <= ; PREV <= M[I]; LSA <= ; I <= I + ; COMP Stte ASJE tnd for Acing Sequence Jut Ended. Note: It could be equence of jut item! Stte ASCE tnd for Acing Sequence Continuing but reched the End of the 4 element rry. ASJE ASCE DONE DONE No RTL needed here Februry 22, 203 5:23 pm EE457 Quiz - Spring / 7 C Copyright 203 Gndhi Puvvd

3 2 ( = 2 point) 5 min. Adder/Subtrctor deign A -A = A + A + = In 4-bit ytem the bove i true (elect (circle) ll correct nwer nd if you elect, then fill-in the blnk too) () if A i treted n unigned number. The rw C4 = (0//dep on A). (b) if A i treted igned number, The V = (0//dep on A). 2.2 The (negtive / poitive / cn fill the blnk with either) number with lrget mgnitude in 6-bit 2 complement ytem i double in mgnitude compred to the one in 5-bit 2 complement ytem Strnge dder: A i 4-bit igned number (A 3 A 2 A A 0 ) repreented in 2 complement ytem. B i 4-bit unigned number (B 3 B 2 B B 0 ). Deign n dder to produce 5-bit igned um S (S = A + B) (i.e. the 5-bit reult i treted 5-bit number repreented in two complement ytem (S 4 S 3 S 2 S S 0 )). Complete the following three deign. The firt two deign ue n hlf dder nd 4-bit dder. The third deign ue two hlf dder nd 3-bit dder. Do not leve ny pin unlbeled. Connect it to either GND or VDD or lbel it NC (for no connection). Either rgue tht we will not hve ny overflow ince the reult h n extrit or explin briefly why there cn be overflow in pite of the 5th bit nd generte the V bit in ech of the three deign. A lwy fter logic get more point. 3 ( = 38 point) 20 min. Verilog Coding A3 A2 A A0 B3 B2 B B0 C4 b C3 C4 C4 C2 C b C0 S3 S2 S S0 A3 A2 A B3 B2 B C3 C2 b C S3 S2 S A3 A2 A B3 B2 B C3 C2 b C S3 S2 S? 6 3. If two concurrent "ign" ttement hve the me left-hnd-ide item hown on the ide, the lter ignment override the erlier. T / F If two procedurl ignment ttement hve the me left-hnd-ide item hown on the ide, the lter ignment override the erlier. T / F The X nd Y in both the egment of code cn be either reg dt type or wire dt type. T / F ign RESULT_wire = X + Y; ign RESULT_wire = X - Y; Y) RESULT_reg = X + Y; RESULT_reg = X - Y; Februry 22, 203 5:23 pm EE457 Quiz - Spring / 7 C Copyright 203 Gndhi Puvvd

4 Prt of ce ttement, coding tte mchine, i hown in ech of the two code below. Complete the correponding ection of the tte digrm implied by the code.. Digrm #A S S0 S2 S0: if (X) tte <= S0; if (Y) tte <= S; ele tte <= S2; Code #A Digrm #B S S0 S2 S0: if (Y) tte <= S; ele tte <= S2; if (X) tte <= S0; Code #B Three tudent re trying to decribe imple ALU which cn only dd or ubtrct nd produce zero inference beide the reult for n old CISC proceor with 2-bu tructure connecting the reg-file to the ALU. The reult R nd the zero inference Z re to be tored in temporry regiter temp_r nd temp_z o tht they both cn be tken bck nd tored in the detintion regiter nd CCR (Condition Code Regiter lo known Flg Regiter) in ubequent clock. Comment on ech of the three code (right.. wrong.. but.. becue..). Regiter #0 Regiter # Regiter #3 A B ALU temp_r temp_z Student # Student #2 Student #3 clk) if (ub) temp_r <= A - B; ele temp_r <= A + B; if (temp_r == 0) temp_z <= ; ele temp_z <= 0; clk) if (ub) int_r <= A - B; ele int_r <= A + B; if (int_r == 0) temp_z <= ; ele temp_z <= 0; clk) if (ub) int_r = A - B; ele int_r = A + B; if (int_r == 0) temp_z <= ; ele temp_z <= 0; Suppoe the bove deign i modified to ingle-bu tructure hown on the ide. Here temp_r i firt trnferred to the detintion regiter followed by temp_z to the CCR. Do you need to modify your previou comment on ny of the three tudent? A (temp) A B ALU temp_r temp_z Februry 22, 203 5:23 pm EE457 Quiz - Spring / 7 C Copyright 203 Gndhi Puvvd

5 4 ( = 2 point) 0 min. All re byte-ddreble proceor with logicl ddre = 32 bit. Fill-in ll miing info.l 9 up Dt Addre pin D3-D0 A3 - A, BE - BE i860 D63-D0 A3 - A, BE - BE USC_28 D27-D0 A3 - A, BE - BE Min. number of byte-wide bnk Shift in ddre connection to memory ddr pin 2 4. Shown on the ide i the memory interfce to 64KB chip in ytem bed on one of the bove three proceor. How do you figure out which proceor-bed ytem it i. Alo find the ytem ddree correponding to the lowet-ddreed two byte of thi memory chip. The ytem i bed on (80486 / i860 / USC_28) becue. The lowet-ddreed two byte of thi chip mp to the ytem ddree. 5 ( = 24 point) 5 min. A[8:3] A3 A30 A29 A28 A27 A26 A25 A24 A23 A22 A2 A20 A9 64KB A[5:0] D[7:0] WE RD CS BE2 D[23:6] Performnce 2 5. Very much like fewer cientific document cn tke much more time to type compred to mny imple "Thnk you" note, few complex intruction my tke longer time (becue of their higher CPI) compred to other impler intruction even if they re more in number (becue of their lower CPI). A proceor h only three ctegorie of intruction. Given the frequencie of their uge in the dynmic trce of ench mrk nd lo the time pent on them, find CPI_B nd CPI_C below. Hint: Apply rtio! CPI Frequency (%) Time (%) Ctegory A CPI_A = 4 50% 20% Ctegory B CPI_B = 30% 30% Ctegory C CPI_C = 20% 50% If one of the three intruction cn hve it CPI reduced by 2 provided you gree to incree the clock period by 5%, do you hve dequte dt to mke deciion, nd if o would you go for it, nd if you go for it, would you get A or B or C improved, nd wht i the fctor of improvement you chieve in the CPU performnce? Februry 22, 203 5:23 pm EE457 Quiz - Spring / 7 C Copyright 203 Gndhi Puvvd

6 6 ( = 50 point) 25 min. Single-cycle CPU: Reproduced on the next pge i the block digrm from your HW#5 olution with upport for both j (jump) nd jl (jump nd link). However the control ignl tble below i to be completed by you to upport thee two intruction, ddi, nd one more intruction. Intruction RegDt ALUSrc Memtoreg RegWrite MemRed MemWrite Brnch ALUOp ALUop0 Jump Jl Jl_ddi 24 R-formt lw w X X beq X 0 X ddi jump jl jl_ddi Now you need to provide upport for new intruction clled jl_ddi. Thi new jl_ddi produce the jump ddre by dding the 6-bit immedite field to ($r) very much like in ddi intructon except tht we hve word_offet here. The intruction formt i very much identicl to the ddi with the $rt field wted. The link behvior of thi new intruction i me tht of the jl. So it provide link to the ubroutine by depoiting the return ddre t $3". jl_ddi $r, word_offet A row nd column re dded to the bove tble to upport thi new intruction. Crry-out the needed modifiction to the block-digrm on the next pge nd complete the ignl tble bove. 7 ( = 2 point) 0 min. Multi-cycle CPU 6 6 Temporry regiter re needed if informtion i produced in one clock nd conumed in lter clock. However, we could void temporry regiter (for exmple, MDR Memory Dt Regiter) by Temporry regiter h Temp_RegWrite control input o tht the CU cn tell regiter when to write. The exception to thi rule i Februry 22, 203 5:23 pm EE457 Quiz - Spring / 7 C Copyright 203 Gndhi Puvvd

7 26 Q#6 (Single-cycle CPU) PCSource Februry 22, 203 5:23 pm EE457 Quiz - Spring / 7 C Copyright 203 Gndhi Puvvd