COMP303 Computer Architecture Lecture 9. Single Cycle Control
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1 COMP33 Computer Architecture Lecture 9 Single Cycle Control
2 A Single Cycle Datapath We have everything except control signals (underlined) RegDst busw Today s lecture will look at how to generate the control signals RegWr Rd imm6 5 5 Rs 5 Rw Ra Rb -bit Registers 6 busb Sign Extender npc_sel busa Src Instruction Fetch Unit ctr Data In Equal Instruction<3:> <2:25> WrEn Rs <6:2> MemWr Adr Data Rd MemRd <:5> <:5> Imm6 MemtoReg
3 RTL: R-Type Instructions op rs rt rd shamt funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits Example: add rd, rs, rt Mem[PC] Fetch the instruction from memory R[rd] R[rs] + R[rt] The actual operation PC PC + 4 Calculate the next instruction s address
4 Instruction Fetch Unit at the Beginning of Add Fetch the instruction from Instruction memory: Instruction mem[pc] Done for all instructions => Don t need special control bits npc_sel Inst Instruction<3:> Adr 4 imm6 PC Ext Adder Adder PC
5 The Single Cycle Datapath during Add R[rd] R[rs] op R[rt] RegDst = RegWr = busw 3 Rd imm Rs 5 Rw Ra Rb -bit Registers 6 busb Sign Extender 2 op rs rt rd shamt funct npc_sel= +4 busa ctr = Add 6 Data In Src = Instruction Fetch Unit Equal Instruction<3:> <2:25> 6 WrEn <6:2> Rs Rd Imm6 MemtoReg = MemWr = Adr Data <:5> MemRd = <:5>
6 Instruction Fetch Unit at the End of Add PC PC + 4 This is the same for all instructions except Branch and Jump npc_sel = +4 Inst Instruction<3:> 4 Adr imm6 PC Ext Adder Adder PC
7 The Single Cycle Datapath during Load R[rt] Data {R[rs] + SignExt[imm6]} RegDst = RegWr = busw 3 Rd imm6 5 5 Rs 5 Rw Ra Rb -bit Registers 6 26 busb Sign Extender 2 op rs rt immediate npc_sel= +4 busa 6 ctr = Add Src = Instruction Fetch Unit Data In Equal Instruction<3:> <2:25> WrEn <6:2> Rs Rd Imm6 MemtoReg = MemWr = Adr Data <:5> MemRd = <:5>
8 The Single Cycle Datapath during Store op rs rt immediate Data {R[rs] + SignExt[imm6]} R[rt] RegDst = x RegWr = busw Rd imm6 5 5 Rs 5 Rw Ra Rb -bit Registers 6 busb Sign Extender npc_sel= +4 busa ctr =Add Data In Src = Instruction Fetch Unit Equal Instruction<3:> <2:25> WrEn <6:2> Rs Rd Imm6 MemtoReg = x MemWr = Adr Data <:5> MemRd = <:5>
9 The Single Cycle Datapath during Branch if (R[rs] - R[rt] == ) then Equal ; else Equal RegDst = x RegWr = busw 3 Rd imm6 5 5 Rs 5 Rw Ra Rb -bit Registers 6 26 busb Extender 2 op rs rt immediate npc_sel= Br busa 6 ctr = Subtract Src = Instruction Fetch Unit Data In Equal Instruction<3:> <2:25> WrEn Rs <6:2> MemWr = Adr Data Rd <:5> MemRd = <:5> Imm6 MemtoReg = x
10 Instruction Fetch Unit at the End of Branch op rs rt immediate if (Equal & Branch) then PC = PC SignExt[imm6]*4 ; else PC = PC + 4 npc_sel Inst Instruction<3:> 4 Adr Adder PC See book for what the datapath and control looks like for jump instructions. imm6 PC Ext Adder
11 Control Lines Determined by the opcode Reg Memto Reg Mem Mem Instr. Des Src Reg Wr Rd Wr Branch op op R-type lw sw X X beq X X op op : -> Add, -> Subtract, -> Function field determines op.
12 Step 4: Given Datapath: RTL -> Control Instruction<3:> Inst Adr <:5> <26:3> Op Fun <2:25> <:5> <:5> <6:2> Rs Rd Imm6 Control npc_sel RegWr RegDst Src ctr MemWr MemRd MemtoReg Equal DATA PATH
13 Control Bits Instruction opcode op Instruction operation Function field Desired action control LW load word XXXXXX add SW store word XXXXXX add beq branch equal XXXXXX subtract R-type add add R-type subtract subtract R-type AND and R-type OR or R-type set on less than set on less than opcode 6 Main Control func 6 op 2 Control (Local) ctr 3
14 The Truth Table for the 3 Control Bits op Function filed Operation op op F5 F4 F3 F2 F F X X X X X X X X X X X X X X X X X X X X X X X X X X X X funct<5:> Instruction Operation add subtract and or set-on-less-than
15 The Logic Equation for ctr<2> op Function filed Operation op op F5 F4 F3 F2 F F X X X X X X X X X X X X X X X X X X X X X X X X X X X X ctr<2> = op + (op & func<>)
16 The Logic Equation for ctr<> op Function filed Operation op op F5 F4 F3 F2 F F X X X X X X X X X X X X X X X X X X X X X X X X X X X X ctr<> =!op +!func<2>
17 The Logic Equation for ctr<> op Function filed Operation op op F5 F4 F3 F2 F F X X X X X X X X X X X X X X X X X X X X X X X X X X X X ctr<> = op & (func<3> + func<>)
18 The Control Block func 6 op 2 Control (Local) ctr 3 ctr<2> = op + (op & func<>) ctr<> =!op +!func<2> ctr<> = op & (func<3> + func<>)
19 The Truth Table for the Main Control op 6 Main Control RegDst Src : op 2 func 6 Control (Local) ctr 3 opcode R-type lw sw beq RegDst Src MemtoReg RegWrite MemRead MemWrite Branch op (Symbolic) R-type Add x x Add x x Subtract op op
20 The Truth Table for RegWrite opcode R-type lw sw beq RegWrite RegWrite = R-type + lw =!op<5> &!op<4> &!op<3> &!op<2> &!op<> &!op<> (R-type) + op<5> &!op<4> &!op<3> &!op<2> & op<> & op<> (lw) op<5>.. op<5>.. op<5>.. op<5>.. <> <> <> <> R-type lw sw beq RegWrite
21 PLA Implementation of the Main Control op<5>.. op<5>.. op<5>.. op<5>.. <> <> <> <> R-type lw sw beq RegWrite Src RegDst MemtoReg MemRead MemWrite Branch op<> op<>
22 op 6 Instr<3:26> RegDst Putting it All Together: A Single Cycle Processor busw Main Control RegWr Rd imm6 Instr<5:> 5 5 Rs 5 Rw Ra Rb -bit Registers 6 op RegDst Src : busb Sign Extender busa 2 npc_sel Src Instruction Fetch Unit ctr func Instr<5:> 6 Data In Equal Instruction<3:> Control <2:25> WrEn Rs <6:2> MemWr Adr Data Rd MemRd ctr <:5> 3 <:5> Imm6 MemtoReg
23 An abstract view of the critical path - load instruction Next Address Ideal Instruction Instruction Address PC Rd 5 Instruction Rs 5 5 Rw Ra Rb -bit Registers Imm 6 A B Critical Path (Load Operation) = PC s -to-q + Instruction s Access Time + Register File s Access Time + to Perform a -bit Add + Data Access Time + Setup Time for Register File Write + Clock Skew Data Address Data In Ideal Data Worst case delay for load is much longer than needed for all other instructions, yet this sets the cycle time.
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