Introduction to Digital Logic

Transcription

1 Introduction to Digital Logic Lecture 26 Simple CPU HW Design

2 Our 8-bit Computer 8-bit data and addresses but 16-bit instructions I/O 8-bit input data from keyboard 8 LED s for output display Memory Store program instructions For our design we ll use a separate 256x16 instruction memory (256 rows / instructions each being 16-bits) Stores program data For our design we ll use a separate 128x8 data memory (each data element is a byte-size value Registers Temporary storage locations inside processor for fast access For our design we ll use (16) 8-bit registers: R0-RF

3 Data Address Space With 8-bit values we can make 256 unique addresses Mark Redekopp, All rights reserved Address range: 00-FF hex We said our data memory will only have 128 locations Address range: 00 7F hex What about the other 128? We will map our I/O devices to some of those unused addresses Read of address 80 hex will return keyboard data Write of address 80 hex will output to LED s 0 7F 80 FF Memory Keyboard (Read) / LEDs (Write) 81 Unoccupied / Unused 128 x 8 RAM I/O and Unused Space

4 Instruction Set Processor supports 11 instructions Instruction Type Comment ADD Rd,Rs,Rt Rd = Rs + Rt SUB Rd,Rs,Rt Rd = Rs Rt MOVE Rd,Rs Rd = Rs XOR Rd,Rs,Rt Rd = Rs XOR Rt AND Rd,Rs,Rt Rd = Rs AND Rt OR Rd,Rs,Rt Rd = Rs OR Rt JEQZ Rt,WX If(Rt = 0) jump to instruc. At address WX JLTZ Rt,WX If(Rt < 0) jump to instruc. At address WX ST Rs,[Rt] Store to Memory (MEM[Rt] = Rs) LDC Rd,XY Load Constant (Rd = XY) LD Rd,[Rt] Load from Memory (Rd = MEM[Rt] )

5 Machine Code Form of Instructions Mark Redekopp, All rights reserved IW[15:12] IW[11:8] IW[7:4] IW[3:0] ADD 0 d s t SUB 1 d s t MOVE 2 d s 0 XOR 4 d s t AND 5 d s t OR 6 d s t JEQZ 8 W X t JLTZ 9 W X t ST B 0 s t LDC E d X Y LD F d 0 t Examples: ADD R4,R5,R6 => 0456 hex; MOVE RC,R3 => 2c30; JEQZ R3,1C => 81C3 hex; LDC R1,FE => E1FE; LD R7,[R1] => F701;

6 Conditional (If) Example if(x==y) Z = X+Y Else Z = X; IMEM Addr Instruction Type Comment 0 LDC R0,0 Load constant 0 for later use 1 LDC R1,80 Address of Keyboard Input 2 LD R2,[R1] Read in X value from keyboard 3 LD R3,[R1] Read in Y value from keyboard 4 SUB R4,R2,R3 Do X-Y to check if X==Y 5 JEQZ R4,8 Goto THEN portion 6 MOVE R5,R2 Z = X 7 JEQZ R0,9 Skip the THEN portion 8 ADD R5,R2,R3 Z = X + Y 9 ST R5,[R1] Write value to LED s A next instruction

7 Loop Example char data[10] = { }; int i, j=0; for(i=9; i >= 0; i--) j = j + data[i]; IMEM Addr Instruction Type Comment 0 LDC R0,0 Constant 0 for later use 1 LDC R1,1 Constant for Decrement Op. 2 LDC R2,20 Based address of data array 3 LDC R3,0 J = 0 4 LDC R4,9 I = 9 5 JLTZ R4,0B I >= 0? 6 ADD R5,R2,R4 Setup address to data[i] 7 LD R6,[R5] Get value of data[i] 8 ADD R3,R3,R6 J = j + data[i] 9 SUB R4,R4,R1 I-- A JEQZ R0,05 Repeat B next instruction

8 Fetch Logic Counter generates address of each instruction (usually sequentially addr. 0, instruc. at addr. 1, addr. 2, etc.) Address used by Instruction Memory to lookup the instruction word

9 Registers 16 registers for use by the instructions [R0-RF] Inputs logic will be described later

10 Operand Select Logic Select the desired operands (registers) specified by the instruction = Rs = s field of instruc. word = Rt = t field of instruc. word

11 ALU ALU performs indicated operations on operands FS[2:0]: 000 => Z = X+Y 100 => Z = X xor Y 001 => Z = X-Y 101 => Z = X and Y 010 => Z = X 110 => Z = X or Y

12 JEQZ or JLTZ Logic ZCOMP compares operand B to 0 and provides EQ and LT results for the Jump instructions Condition Mux selects the condition for when to load the PC with a non-sequential value

13 Memory Access Below is the logic for reading and writing the data memory as well as the input (keyboard) and output (LED s) 8-bit address space is split into halves with lower half for data memory and upper half for I/O (only use 1 address)

14 Memory Access Below is the logic for reading (LD) and writing (ST) the data memory OPB (coming from Rt) is the address OPA (coming from Rs) is the data to write (for STM) 8-bit address space is split into halves with lower half (ADDR[7] = OPB[7] = 0) for data memory

15 I/O Access Access I/O devices by performing loads and stores to corresponding address Any access to the upper half (MSB of address = 1) of data memory address range should access the keyboard or LED s Address = 00-7f corresponds to where MSB of address (OPB[7]) is 0 Address = 80-ff corresponds to where MSB of address (OPB[7]) is 1

16 Register Inputs and Load Signals Load the appropriate register for the appropriate instructions Result of an instruction comes from either the ALU (ADD, SUB, etc.), MEM (LD), Instruction Word (LDC) We run the result to all registers and use a decoder to select which register is actually enabled to load the new value.

17 Control Signals IW15 IW14 IW13 IW12 IS1 IS0 RS1 RS0 LD RD WR FS2 FS1 FS d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d d Mark Redekopp, All rights reserved

18 Control Signal Equation Using the truth table on previous slide, each output can be derived using a K-Map, yielding the following values: IS1 = IW15 IW13 IW12 IS0 = IW15 IW13 IW12 RS1 = IW13 IW12 RS0 = IW15 IW12 LD = IW15 + IW14 RD = IW14 IW13 IW12 WR = IW15 IW14 IW13 FS[2:0] = IW[14:12]