EE380 Spring 2014 Exam 1 Answer Key

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1 Your name is: Your address is: The two questions you skipped are: There are 15 questions. Each of the first 14 questions is wor th 8points; you must answer any 12 and indicate above which 2 you skipped (no extra credit). You also must answer question 15, which is wor th just 4 points. For the multiple choice questions, indicate your single answer for each question by checking the appropriate box,,unless the question explicitly asks you to mar k all that apply. The short answer questions should get shor t answers; excessively long answers may beconsidered incorrect. You may tear-out the reference page at the end of this exam if you wish, and you do not need to turn that page in. The test is closed book, closed notes, closed minds, nocalculators. Page 1 of 7

2 1. One of the function units we discussed perfor med sign extension, converting a 16-bit 2 s complement number into the 32-bit 2 s complement representation with the same value. Suppose that you have the 4-bit 2 s complement value What 8-bit pattern would result from sign extending that value to an 8-bit 2 s complement representation? Sign extension replicates the top bit into the larger representation: 1010 becomes For this question, mar k all that apply. Which of the following does not descr ibe an instr uction in the MIPS ISA as discussed in this course? Store a 32-bit word from a register into memory Load a 32-bit immediate constant into a register Push a 32-bit value from a register onto a stack inmemor y Add two values in registers and put the result in a third register Add a value from memory toavalue in a register and put the result in that register 3. Using only MIPS instructions listed on the last page of this exam, write assembly code to implement the following C code. Var iables should be placed in the registers with the same name, i.e., t0 is kept in the register named $t0; other t registers may beused as temporar ies. Comment any non-obvious things you do. if (t0 < 0) { t0 = 42; } fi: slt $t1,$t0,$0 beq $t1,$0,fi ori $t0,$0,42 Page 2 of 7

3 4. Using only MIPS instructions listed on the last page of this exam, write assembly code to implement the following C code. Var iables should be placed in the registers with the same name, i.e., t0 is kept in the register named $t0; other t registers may beused as temporar ies. Comment any non-obvious things you do. while (t0) { t0 = t0 - t1; } while: beq $t0,$0,elihw sub $t0,$t0,$t1 j while elihw: 5. The IEEE 754 floating point standard specifies that a 32-bit float encodes 1 sign bit, 8 bits of exponent, and 24 bits of mantissa. That adds up to 33 bits. How is this possible? Normalized floating point numbers has a 1 in the mantissa MSB; thus, there is no need to store the MSB... and 24 bits fits a 23-bit field. 6. Which one of the following four ways to build a 32-bit 2 s-complement binary adder is not a strictly combinatorial circuit (i.e., might require two clock cycles to compute the correct result)? Ripple carry Carr y select Carr y lookahead Speculative carr y requires a second clock cycle if carry guess was wrong None of the above Page 3 of 7

4 7. You have been hired to optimize a program operating on normal IEEE 754 floats so it will execute a little faster. Par t of the code looks like: float a[n];... float sum=0; float prod=1; int i; for (i=0; i<n; ++i) { sum = sum + a[i]; prod = prod * a[i]; } However, you happen to know that the particular processor it is running on has a special instruction that makes loops that count down faster than ones that count up. So, you rewr ite the code as: float a[n];... float sum=0; float prod=1; int i; for (i=n-1; i>=0; --i) { sum = sum + a[i]; prod = prod * a[i]; } The new code runs faster, but your boss has a problem with the new version. Assuming none of the float values go out of range, what s bother ing her? It doesn t get the same value for sum because the order of additions is changed. 8. For this question, mar k all that apply. Consider the figure shown at the end of this exam. Which of the following four control lines is a don t care while executing an xor instr uction? Branch must be 0 RegDst must be 1 ALUSrc must be 0 MemRead must be 0 MemToReg must be 0 None of these are don t cares! Page 4 of 7

5 9. For this question, mar k all that apply. Consider the figure shown at the end of this exam (the same one used in the previous question). For this single-cycle implementation, suppose we were to probe a few of the control signals and found that for a particular clock cycle, ALUSrc=0, MemtoReg=0, RegWrite=0, and MemRead=0. Which of the following MIPS instructions might have been executing? lw No: ALUSrc=1, MEMtoReg=1, RegWrite=1, MemRead=1 sw No: ALUSrc=1 beq Yes! add No: RegWrite=1 addi No: ALUSrc=1, RegWrite=1 10. For this question, mar k all that apply. Consider the figure shown at the end of this exam (the same one in the previous two questions). For this single-cycle implementation, which of the following control signals cannot have the same value for the ori, lw, and sw instr uctions? Branch None are branches ALUsrc ALUSrc=1 for all of these]fr RegDst RegDst=0 is needed by ori and lw, and sw doesn t care MemRead 1for lw, 0for ori and sw MemToReg 0for ori, 1 for lw, swdoesn t care Page 5 of 7

6 11. Assuming the following code is executed using 32-bit IEEE 754 floating-point, what does this code do? float f = 0; int i; for (i=0; i< ; ++i) { ++f; } if (i == f) printf("yes!\n"); else printf("no!\n"); The for loop executes the body times. However, f stops incrementing at around 2ˆ24 -- when the value of f differs from 1 by more than we have bits in the mantissa. Thus, it prints "No!" and a newline. 12. Imagine a 32-by-32-bit hardware multiplier using Booth s algor ithm, as we discussed in class. Suppose we need to compute 63*63, 51*51, and 42*42. Which of these three multiplications would you expect would take the fewest clock cycles? Why? 63 is one subtract: (64<<6)-(64<<0) 51 is four add/subtract 42 is three adds 13. What is the effect of executing the MIPS subroutine f?.data x:.word 42.word 601.word 13.word 100.word 380.text f: la $t0, x lw $t1, 4($t0) addi $t1, $t1, 4 sw $t1, 0($t0) jr $ra It s essentially like: x[0] = x[1]+4; Which means it replaces 42 with 605. Page 6 of 7

7 14. Using only MIPS instructions listed on the last page of this exam, write assembly code to implement the following C code. Var iables should be placed in the registers with the same name, i.e., t0 is kept in the register named $t0; other t registers may beused as temporar ies. Comment any non-obvious things you do. t0 = t1 + (t2 & t3); and $tx,$t2,$t3 add $t0,$t1,$tx where $tx is any of$t0, $t4, $t5, etc. 15. Given the following logic array diagram, show the connections needed to make X = (A AND C) OR (B AND D) OR (NOT(A) AND NOT(B) AND NOT(C)) A B C D X Y Z Page 7 of 7

8 Reference Information Feel free to separate (and discard) this sheet from your exam. It is intended as a reference only. MIPS Instructions (a subset) add addu addi addiu and andi or ori sub subi xor xori lui slt beq bne j jal jr lw sw r1,immediate r1,r2,label r1,r2,label label label r1 r1,offset(r2) r1,offset(r2) Note that for this exam, you may use li and/or la even though they are not really instr uctions.

9 Single-Cycle Implementation Architecture EE380 Spring 2014 Exam 1 Answer Key

ECE Exam I - Solutions February 19 th, :00 pm 4:25pm

ECE Exam I - Solutions February 19 th, :00 pm 4:25pm ECE 3056 Exam I - Solutions February 19 th, 2015 3:00 pm 4:25pm 1. (35 pts) Consider the following block of SPIM code. The text segment starts at 0x00400000 and the data segment starts at 0x10010000..data