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1 Chapter 2: Instructions: Language of the Computer Computer Architecture CS

2 Instructions: To command a computer s hardware you must speak it s language The computer s language is called instruction The computer s vocabulary is called Instruction set MIPS Instruction set Architecture used by NEC, Nintendo, Cisco, Silicon Graphics, Sony, Other SPARC Hitachi SH PowerPC Motorola 68K MIPS IA-32 ARM Computer Architecture CS

3 Operations of Computer Hardware MIPS Arithmetic Instruct a computer to add two variables b and c and store the result in a: add a, b, c MIPS Arithmetic Instruction Format: Must have 3 Operands always Order of operands is rigid Instruction performs one operation Design Principle 1: Simplicity favors regularity. Computer Architecture CS

4 MIPS Arithmetic examples C code: a = b + c + d; MIPS code: add a, b, c add a, a, d C code: a = b + c + d + e; MIPS code: add a, b, c # puts sum of b and c in a add a, a, d add a, a, e C code d = a e; MIPS code: sub d, a, e Computer Architecture CS

5 MIPS Arithmetic Compiling complex C assignments C code: f = (g + h) (i + j); MIPS code: add t, g, h add t1, i, j sub f, t, t1 MIPS arithmetic instruction operates on two source operands and places the result in one destination operand Computer Architecture CS

6 MIPS Arithmetic Operands (computer Hardware) Arithmetic instructions operands must be registers Restricted to 32 registers Compiler associates variables with registers The 3 variable operands must be chosen from one of the 32 Registers Why are we limited to 32 Registers: Design Principle 2: Smaller is Faster Effective use of register is key to program performance What about programs with lots of variables? ( we will talk about this shortly) Computer Architecture CS

7 MIPS Arithmetic Convention Registers that correspond to variables: \$s, \$s1, \$s2.. Temporary Registers: \$t, \$t1, \$t2.. C code: f = (g + h) (i + j) f -> \$s, g -> \$s1, h -> \$s2, i -> \$s3, j -> \$s4 add \$t, \$s1, \$s2 add \$t1, \$s3, \$s4 sub \$s, \$t, \$t1 Computer Architecture CS

8 MIPS Arithmetic Memory Operand Data Structures (arrays, and structures) Stored in memory Not enough registers to hold them Memory data items must be transferred to registers for Arithmetic operations MIPS instruction set Includes Data Transfer Instructions Computer Architecture CS

9 Memory Organization Conceptually a 1-D array with an Address scheme Address is index to array Memory width (w) is 8 bits of data (1 byte) --- word Index points to a byte of memory Computer Architecture CS

10 Memory Organization Registers Vs. Memory The size of MIPS word is 32 bits or 4 bytes MIPS Register has larger word than memory 32 bits of data bits of data 32 bits of data 32 bits of data 32 bits of data Each MIPS word start at address that is a multiple of bytes -> byte address words -> byte address Computer Architecture CS

11 MIPS Arithmetic Data Transfer Instructions Load word (lw) and Store word (sw) Instruction: C code: MIPS code: A[12] = h + A[8]; lw \$t, 32(\$s3) add \$t, \$s2, \$t sw \$t, 48(\$s3) Destination Destination What is wrong with: add 48(\$S3), \$s2, 32(\$s3)? Computer Architecture CS

12 MIPS So far MIPS Load words but address bytes Performs arithmetic on registers only MIPS Instructions Meaning add \$s1, \$s2, \$s3 \$s1 = \$s2 + \$s3 sub \$s1, \$s2, \$s3 \$s1 = \$s2 - \$s3 lw \$s1, 1(\$s2) \$s1 = Memory[\$s2 + 1] sw \$s1, 1(\$s2) Memory[\$s2 +1] = \$s1 Computer Architecture CS

13 Machine Language Instructions Arithmetic Instructions MIPS Instructions: Example: add \$t, \$s1, \$s2 # \$t = \$s1 + \$s2 Registers represented by numbers: \$t -> 8; \$s1 -> 17; \$s2 -> 18 Instruction Format (R-Type): op rs rt rd shamt funct Computer Architecture CS

14 Machine Language Instructions Arithmetic Instructions add \$t, \$s1, \$s2 op rs rt rd shamt funct MIPS Instructions: 32 bits long Computer Architecture CS

15 Machine Language Instructions Data Transfer Instructions MIPS Instructions: Example: lw \$t, 32(\$3) # \$t gets A[8] Registers represented by numbers: Instruction Format (I-Type): op rs rt Constant Or Address bits 5 bits 5 bits I-Type Instructions: 32 bits long bit number Design Principle 4: Good design demands a compromises Computer Architecture CS

16 Machine Language Example: C- code: A[3] = h + A[3]; MIPS code: lw \$t, 12 (\$t1) add \$t, \$s2, \$t sw \$t, 12(\$t1) op rs rt rd addr/ funct shamt Offset Computer Architecture CS

17 Machine Language Example: C- code: A[3] = h + A[3]; Machine Language op rs rt rd addr/ funct shamt Computer Architecture CS

18 Machine Language Let s Summarize Example: C- code: A[3] = h + A[3]; MIPS code: lw \$t, 12 (\$t1) add \$t, \$s2, \$t sw \$t, 12(\$t1) op rs rt rd addr/ funct shamt op rs rt rd addr/ funct shamt Computer Architecture CS

19 Machine Language Instructions Branch Instructions MIPS conditional branch instructions: beq \$s1, \$s2, L1 bne \$s1, \$s2, L1 L1: Example: if ( i == j) f = g + h; - Variables: f, g, h, i, j registers: \$s, \$s1, \$s2, \$s3, \$s4 bne \$s3, \$s4, Label add \$s, \$s1, \$s2 Label: Computer Architecture CS

20 Machine Language Instructions Branch Instructions MIPS unconditional branch instructions: j Label j Exit Example: if ( i == j) f = g + h; else f = g h; - Variables: f, g, h, i, j registers: \$s, \$s1, \$s2, \$s3, \$s4 bne \$s3, \$s4 Else #go to Else if i!= j add \$s, \$s1, \$s2 j Exit Else: sub \$s, \$s1, \$s2 Exit: Computer Architecture CS

21 Machine Language Instructions Branch Instructions Instruction Format (J -Type): op 26 bit number J -Type Instructions: 32 bits long Computer Architecture CS

22 Machine Language Instructions Compare Instructions if \$s3 < \$s4 then \$t = 1 else \$t = slt \$t, \$s3, \$s4 Computer Architecture CS

23 Machine Language Instructions Compare Instructions if \$s3 < then \$t = 1 else \$t = slt \$t, \$s3, \$zero \$zero maps to Register ( we will talk about constants shortly) Assembler also needs a register to perform instructions Computer Architecture CS

24 MIPS register convention Name Register number Usage \$zero the constant value \$v-\$v1 2-3 values for results and expression evaluation \$a-\$a3 4-7 arguments \$t-\$t temporaries \$s-\$s saved \$t8-\$t more temporaries \$gp 28 global pointer \$sp 29 stack pointer \$fp 3 frame pointer \$ra 31 return address Register 1 (\$at) reserved for assembler, for operating system Computer Architecture CS

25 Constants C code: x = x + 5; y = y + 1; z = z - 15; Some constants are loaded from memory to registers. Some hard-wired to registers ( \$zero) MIPS Instructions: addi \$29, \$29, 4 slti \$8, \$18, 1 Design Principle 5: Make the common case fast. Computer Architecture CS

26 Let s summarize MIPS simple instructions all 32 bits wide very structured, no unnecessary baggage only three instruction formats R I J op rs rt rd shamt funct op rs rt 16 bit address op 26 bit address - rely on compiler to achieve performance Computer Architecture CS

27 Let s summarize Branches and Jumps Instructions: bne \$t4,\$t5,label beq \$t4,\$t5,label j Label Next instruction is at Label if \$t4 \$t5 Next instruction is at Label if \$t4 = \$t5 Next instruction is at Label Formats: op rs rt 16 bit address op 26 bit address Computer Architecture CS

28 Let s summarize MIPS operands Name Example Comments \$s-\$s7, \$t-\$t9, \$zero, Fast locations for data. In MIPS, data must be in registers to perform 32 registers \$a-\$a3, \$v-\$v1, \$gp, arithmetic. MIPS register \$zero alw ays equals. Register \$at is \$fp, \$sp, \$ra, \$at reserved for the assembler to handle large constants. Memory[], Accessed only by data transfer instructions. MIPS uses byte addresses, so 2 3 memory Memory[4],..., sequential w ords differ by 4. Memory holds data structures, such as arrays, words Memory[ ] and spilled registers MIPS assembly language Category Instruction Example Meaning Comments add add \$s1, \$s2, \$s3 \$s1 = \$s2 + \$s3 Three operands; data in registers Arithmetic subtract sub \$s1, \$s2, \$s3 \$s1 = \$s2 - \$s3 Three operands; data in registers add immediate addi \$s1, \$s2, 1 \$s1 = \$s2 + 1 Used to add constants load w ord lw \$s1, 1(\$s2) \$s1 = Memory[\$s2 + 1]Word from memory to register store w ord sw \$s1, 1(\$s2) Memory[\$s2 + 1] = \$s1 Word from register to memory Data transfer load byte lb \$s1, 1(\$s2) \$s1 = Memory[\$s2 + 1]Byte from memory to register store byte sb \$s1, 1(\$s2) Memory[\$s2 + 1] = \$s1 Byte from register to memory branch on equal beq \$s1, \$s2, 25 if (\$s1 == \$s2) go to Equal test and branch L branch on not equal bne \$s1, \$s2, 25 if (\$s1!= \$s2) go to Conditional L branch set on less than slt \$s1, \$s2, \$s3 if (\$s2 < \$s3) \$s1 = 1; else \$s1 = set less than immediate slti \$s1, \$s2, 1 if (\$s2 < 1) \$s1 = 1; else \$s1 = Not equal test and Branch Compare less than; for beq, bne Compare less than constant Computer Architecture CS

29 addi \$v, \$zero lw \$v1, (\$a) sw \$v1, (\$a1) addi \$a, \$a, 4 addi \$a1, \$a1, 4 beq \$v1, \$zero, loop op rs rt rd addr/ funct shamt L/4 Computer Architecture CS

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