The IIT standard cell library Version 2.1
|
|
|
- Alan Perry
- 6 years ago
- Views:
Transcription
1 The IIT standard cell library Version 2.1 Highlights - Support for AMI 0.35um library, including pads - Added Primetime and Pathmill support to IIT ASIC Flow - Support for stacked vias (for Virtuoso and Magic7) - IIT ASIC Flow now fully supports Magic AMI 0.5 still supports Magic Magic 7.3 techfiles and setup instructions included - All libraries now include Sue Schematics - Many bug fixes in the schematics - LVS of device widths now possible with Virtuoso and Gemini - Added new script iitcells_ext2sim for easier netlisting with Magic - Encounter and Silicon Ensemble now output DSPF for Primetime - Encounter flow offers o timing-driven placement and routing o static timing analysis (renders Primetime optional) o clock tree synthesis o in-place-optimization and netlist modifications o Geometry and Connection Verification (DRC) - Release is now structured into three main blocks o./lib All library files o./flow The IIT ASIC flow (script templates for most major tools) o./ref_designs Reference Designs to verify and demonstrate usage - The flow and reference design parts are optional for those only interested in the libraries Where are the files located? Library Path Comments AMI 0.5um./flow/ami05 Or ami05.stacks - Default LEF file excludes stacked vias - Use ami05.stacks for stacked vias - Pad synthesis no longer supported (insert padframe in RTL code) AMI 0.35um./flow/ami035 - Includes TSMC 0.35um Pads - Uses stacked vias, use with Magic 7.3 TSMC 0.25um./flow/tsmc025 - Uses stacked vias, use with Magic 7.3 TSMC 0.18um./flow/tsmc018 - Now uses 6 metal layers - Uses stacked vias, use with Magic 7.3
2 The IIT ASIC Design Flow RTL Code (to include Pads if pads are desired) Synthesis Script Timing Libs Synthesis Gatelevel Netlist design.vh Toplevel Constraints Design.sdc Silicon Ensemble (old flow) Encounter (new flow) Layout final.gds2 Post routing timing report Primetime Parasitics DSPF
3 What does the new IIT Encounter Flow Include? Gatelevel Netlist Toplevel Constraints Design Import Floorplanning Placement In-place Optimization I Clock-tree Synthesis In-place Optimization II Timing-driven Routing Design Output Final netlist final.v Layout final.gds2 Timing Reports
4 How to setup a new design? 1. Simulate and test all Verilog RTL code 2. Make a run directory, e.g. seultra or encounter 3. Copy templates into that directory, e.g. cp /import/cad2/iit_stdcells/flow/tsmc018/*./encounter How to run Synthesis with Synopsys Design Compiler 1. Customize compile_dc.scr a. Specify the names of all Verilog files b. Specify the toplevel names c. Specify the target clock frequency (in MHz) d. Specify the name of the clock pin e. Specify the input and output delays (or accept the default value of 1ns) 2. Run dc_shell f compile_dc.scr 3. The results a. The gate-level netlist (.vh) b. The toplevlel timing constraints (.sdc) c. Timing report: timing.rep d. Area report: cell.rep e. Power report: power.rep How to run Synthesis with Cadence BuildGates 1. Customize compile_bgx.scr a. Specify the names of all Verilog files b. Specify the toplevel names c. Specify the target clock frequency (in MHz) d. Specify the name of the clock pin e. Specify the input and output delays (or accept the default value of 1ns) 2. Run bgx_shell f compile_bgx.scr 3. The results a. The gate-level netlist (.vh) b. The toplevlel timing constraints (.sdc) c. Timing report: timing.rep d. Area report: cell.rep e. Power report: power.rep How to place&route with Silicon Ensemble (old flow) 1. Customize seultra.scr 2. Run se_shell f seultra.scr 3. The results a. Layout file final.gds2
5 How to place&route with Encounter (new flow) 1. Customize encounter.conf a. Enter the toplevel name at the top b. Uncomment the encounter.io line if there are pads 2. Run encounter init encounter.tcl 3. Either enter win to open the GUI with the chip or exit to quit 4. The results a. Layout file final.gds2 b. Final netlist.v c. Final timing report: timing.rep.5.final d. Other timing reports from various place&route stages: timing.rep* How to create a Magic 6.5 Layout (only AMI 0.5um) 1. If used seultra : run iitcells_se2magic 2. If used encounter: run iitcells_enc2magic Note: only works with ami05, not ami05.stacks, due to stacked via issues How to create a Magic 7.3 Layout (all technologies) 3. If used seultra : run iitcells_se2magic7 4. If used encounter: run iitcells_enc2magic7 How to create a Cadence Layout 1. If used seultra : run iitcells_se2icfb 2. If used encounter: run iitcells_enc2icfb How to run a design with pads 1. Insert pads in the RTL code of your design (see the example designs) 2. Simulate the RTL code to make sure it still works 3. Run Synthesis as usual 4. For Silicon Ensemble: no change necessary 5. For Encounter a. Uncomment the encounter.io line in encounter.conf b. Make sure the name in encounter.io match the pads in the RTL code c. You can modify the encounter.io file to specify pads locations d. Now run Encounter as usual What if I am using AMI 0.5um but I want stacked vias 1. Stacked vias make routing much easier because a. The router can change layers without stair cases b. The router can connect to the cell anywhere, not just on the pin c. Everything except the pin used to be an obstruction, even though it was still part of the net and valid for connection 2. Use./flow/ami05.stacks instead of./flow/ami05
6 3. Run as usual 4. Use Magic 7.3, not Magic 6.5 as your layout editor How to run LVS with Sue against Magic? 1. A./sue folder is automatically created by iitcells_xxx2magicx 2. Use sue to create a.sim netlist from the sue schematic 3. If pads are being used, manually add one instance each of PADVDD and PADGND (this is because the verilog import cannot import those) 4. To netlist an extracted Magic layout: a. Do :ext in Magic to extract the layout b. Do iitcells_ext2sim layout_name lambda e.g. iitcells_ext2sim nrd_ Note that this will create nrd_05.sim and nrd_05_norc.sim Use the _norc.sim file for Gemini LVS 5. Now run LVS using Gemini gemini./magic/netlist_norc.sim./sue/netlist.sim Installing Magic Download the latest version from 2. Configure and compile the source code./configure --prefix=/net/magic without-opengl make make install (Put your desired target path for prefix. At IIT we disabled Open-GL because of a local issue. Be sure to try it with Open-GL (default). If you use Solaris 8, IIT can provide pre-compiled binaries of Magic 7.3) 3. To obtain a command line version of ext2sim do this: make veryclean./configure --without-tcl make cp ext2sim/ext2sim /net/magic-7.3/bin (This compiles the code again but does not install anything. Simply grab the ext2sim binary and put it wherever you want it). 4. Set $CAD_HOME to the magic install directory and add $CAD_HOME/bin to your path (typically in.cshrc): setenv CAD_HOME /net/magic-7.3 set path = ($CAD_HOME/bin $path) 5. The techfiles are included in the IIT Asic flow release in /flow/techfiles. Copy them to $CAD_HOME/lib/magic/sys. To define a default techfile, create a symbolic link called scmos.tech to your desired target default file. 6. If you would like to keep your keyboard definitions from an older Magic installation, simply copy $CAD_HOME/lib/magic/sys/.magic from the old to the new magic installation. 7. If you are not compiling a new version of irsim, you need to copy anxhelper to $CAD_HOME/bin for irsim to be able to open an analyzer window.
7 8. If you don t want the TCL command window, start magic with magic nocon. Known Problems and Solutions 1. Silicon Ensemble leaves gaps between pads This tools has a tendency to leave small gaps between the corner cells and pad rows. Use a layout editor to verify and move the pads if necessary. 2. Sue schematics with pads are missing PADVDD and PADGND Due to a limitation of v2sue, cells with no pins cannot be imported into Sue. That includes the corners, supply pads and spacer pads. This also means that LVS with device width comparison will fail, but normal LVS will still work. The user has to manually add PADVDD and PADGND to the schematic to get matching LVS.
CPE/EE 427, CPE 527, VLSI Design I: Tutorial #4, Standard cell design flow (from verilog to layout, 8-bit accumulator)
CPE/EE 427, CPE 527, VLSI Design I: Tutorial #4, Standard cell design flow (from verilog to layout, 8-bit accumulator) Joel Wilder, Aleksandar Milenkovic, ECE Dept., The University of Alabama in Huntsville
Logic Synthesis. Logic Synthesis. Gate-Level Optimization. Logic Synthesis Flow. Logic Synthesis. = Translation+ Optimization+ Mapping
Logic Synthesis Logic Synthesis = Translation+ Optimization+ Mapping Logic Synthesis 2 Gate-Level Optimization Logic Synthesis Flow 3 4 Design Compiler Procedure Logic Synthesis Input/Output 5 6 Design
CPE/EE 427, CPE 527, VLSI Design I: Tutorial #3, Standard cell design flow (from schematic to layout, 8-bit accumulator)
CPE/EE 427, CPE 527, VLSI Design I: Tutorial #3, Standard cell design flow (from schematic to layout, 8-bit accumulator) Joel Wilder, Aleksandar Milenkovic, ECE Dept., The University of Alabama in Huntsville
An overview of standard cell based digital VLSI design
An overview of standard cell based digital VLSI design Implementation of the first generation AsAP processor Zhiyi Yu and Tinoosh Mohsenin VCL Laboratory UC Davis Outline Overview of standard cellbased
Synthesis and APR Tools Tutorial
Synthesis and APR Tools Tutorial (Last updated: Oct. 26, 2008) Introduction This tutorial will get you familiarized with the design flow of synthesizing and place and routing a Verilog module. All the
CPE/EE 427, CPE 527, VLSI Design I: Tutorial #3, Standard cell design flow (from schematic to layout, 8-bit accumulator)
CPE/EE 427, CPE 527, VLSI Design I: Tutorial #3, Standard cell design flow (from schematic to layout, 8-bit accumulator) Joel Wilder, Aleksandar Milenkovic, ECE Dept., The University of Alabama in Huntsville
EE 330 Laboratory Experiment Number 11
EE 330 Laboratory Experiment Number 11 Design and Simulation of Digital Circuits using Hardware Description Languages Fall 2017 Contents Purpose:... 3 Background... 3 Part 1: Inverter... 4 1.1 Simulating
CPE/EE 427, CPE 527, VLSI Design I: VHDL design simulation, synthesis, and ASIC flow, Laboratory #8,
CPE/EE 427, CPE 527, VLSI Design I: VHDL design simulation, synthesis, and ASIC flow, Laboratory #8, Joel Wilder and Aleksandar Milenkovic, ECE Dept., The University of Alabama in Huntsville 1. INTRODUCTION
Physical Placement with Cadence SoCEncounter 7.1
Physical Placement with Cadence SoCEncounter 7.1 Joachim Rodrigues Department of Electrical and Information Technology Lund University Lund, Sweden November 2008 Address for correspondence: Joachim Rodrigues
An Overview of Standard Cell Based Digital VLSI Design
An Overview of Standard Cell Based Digital VLSI Design With examples taken from the implementation of the 36-core AsAP1 chip and the 1000-core KiloCore chip Zhiyi Yu, Tinoosh Mohsenin, Aaron Stillmaker,
EE 330 Laboratory Experiment Number 11 Design and Simulation of Digital Circuits using Hardware Description Languages
EE 330 Laboratory Experiment Number 11 Design and Simulation of Digital Circuits using Hardware Description Languages Fall 2015 Purpose: The purpose of this experiment is to develop methods for using Hardware
Laboratory 6. - Using Encounter for Automatic Place and Route. By Mulong Li, 2013
CME 342 (VLSI Circuit Design) Laboratory 6 - Using Encounter for Automatic Place and Route By Mulong Li, 2013 Reference: Digital VLSI Chip Design with Cadence and Synopsys CAD Tools, Erik Brunvand Background
Part B. Dengxue Yan Washington University in St. Louis
Tools Tutorials Part B Dengxue Yan Washington University in St. Louis Tools mainly used in this class Synopsys VCS Simulation Synopsys Design Compiler Generate gate-level netlist Cadence Encounter placing
Tutorial for Encounter
Tutorial for Encounter STEP 1: Login to the Linux system on Linuxlab server. Start a terminal (the shell prompt). (If you don t know how to login to Linuxlab server, look at here) Click here to open a
EE 330 Laboratory Experiment Number 11 Design, Simulation and Layout of Digital Circuits using Hardware Description Languages
EE 330 Laboratory Experiment Number 11 Design, Simulation and Layout of Digital Circuits using Hardware Description Languages Purpose: The purpose of this experiment is to develop methods for using Hardware
ASIC Physical Design Top-Level Chip Layout
ASIC Physical Design Top-Level Chip Layout References: M. Smith, Application Specific Integrated Circuits, Chap. 16 Cadence Virtuoso User Manual Top-level IC design process Typically done before individual
Cell-Based IC Physical Design & Verification SOC Encounter. Advisor : 李昆忠 Presenter : 蕭智元
Cell-Based IC Physical Design & Verification SOC Encounter Advisor : 李昆忠 Presenter : 蕭智元 Reference: SOC Encounter Training Manual, 2007, edited by CIC. Introduction We ll use some EDA tools to transform
Tutorial for Cadence SOC Encounter Place & Route
Tutorial for Cadence SOC Encounter Place & Route For Encounter RTL-to-GDSII System 13.15 T. Manikas, Southern Methodist University, 3/9/15 Contents 1 Preliminary Setup... 1 1.1 Helpful Hints... 1 2 Starting
Cadence On-Line Document
Cadence On-Line Document 1 Purpose: Use Cadence On-Line Document to look up command/syntax in SoC Encounter. 2 Cadence On-Line Document An on-line searching system which can be used to inquire about LEF/DEF
EECS 627, Lab Assignment 3
EECS 627, Lab Assignment 3 1 Introduction In this lab assignment, we will use Cadence ICFB and Calibre to become familiar with the process of DRC/LVS checks on a design. So far, we have placed and routed
Cell-Based Design Flow. TA : 吳廸優
Cell-Based Design Flow TA : 吳廸優 dywu@viplab.cs.nctu.edu.tw 1 Outline Overview Design Flow Stage 1 RTL Development Synthesis Gate Level Simulation Design Flow Stage 2 Placement and Routing Post Layout Simulation
CADENCE TUTORIAL. San Diego State University, Department of Electrical and Computer Engineering. Amith Dharwadkar and Ashkan Ashrafi
CADENCE TUTORIAL San Diego State University, Department of Electrical and Computer Engineering Amith Dharwadkar and Ashkan Ashrafi 1 Contents 1) 2) 3) 4) 5) 6) Introduction 3 Connecting to the Volta server..4
Creating LEF File. Abstract Generation: Creating LEF Tutorial File Release Date: 01/13/2004. Export GDS:
Creating LEF Tutorial 1-1 - Creating LEF File Abstract Generation: Export GDS: Abstract generator comes as a part of the Silicon Ensemble package. As such, it cannot directly read ICFB library databases.
CMOS VLSI Design Lab 3: Controller Design and Verification
CMOS VLSI Design Lab 3: Controller Design and Verification The controller for your MIPS processor is responsible for generating the signals to the datapath to fetch and execute each instruction. It lacks
Standard Cell Based Design Flow Using Modelsim, Buildgates, and Silicon Ensemble
Arifur Rahman, Spring 2004, Polytechnic University, NY Standard Cell Based Design Flow Using Modelsim, Buildgates, and Silicon Ensemble Mapped Netlist Back Annotation using SDF File and mapped netlist
PrimeTime: Introduction to Static Timing Analysis Workshop
i-1 PrimeTime: Introduction to Static Timing Analysis Workshop Synopsys Customer Education Services 2002 Synopsys, Inc. All Rights Reserved PrimeTime: Introduction to Static 34000-000-S16 Timing Analysis
Place & Route: Using Silicon Ensemble
Place & Route: Using Silicon Ensemble Introduction In a typical digital design flow, hardware description language is used to model a design and verify desired behavior. Once the desired functionality
CMOS VLSI Design Lab 3: Controller Design and Verification
CMOS VLSI Design Lab 3: Controller Design and Verification The controller for your MIPS processor is responsible for generating the signals to the datapath to fetch and execute each instruction. It lacks
Logic synthesis and Place and Route Tutorial Page 1
Logic synthesis and Place and Route Tutorial Page 1 Standard Cell ASIC Design flow: A designer uses predesigned logic cells such as AND gate, NOR gate, etc. These gates are called Standard Cells. The advantage
TUTORIAL II ECE 555 / 755 Updated on September 11 th 2006 CADENCE LAYOUT AND PARASITIC EXTRACTION
TUTORIAL II ECE 555 / 755 Updated on September 11 th 2006 CADENCE LAYOUT AND PARASITIC EXTRACTION After finishing a schematic of your design (Tutorial-I), the next step is creating masks which are for
CMOS VLSI Design Lab 3: Controller Design and Verification
CMOS VLSI Design Lab 3: Controller Design and Verification The controller for your MIPS processor is responsible for generating the signals to the datapath to fetch and execute each instruction. It lacks
ECE425: Introduction to VLSI System Design Machine Problem 3 Due: 11:59pm Friday, Dec. 15 th 2017
ECE425: Introduction to VLSI System Design Machine Problem 3 Due: 11:59pm Friday, Dec. 15 th 2017 In this MP, you will use automated tools to synthesize the controller module from your MP2 project into
The SOCks Design Platform. Johannes Grad
The SOCks Design Platform Johannes Grad System-on-Chip (SoC) Design Combines all elements of a computer onto a single chip Microprocessor Memory Address- and Databus Periphery Application specific logic
Synthesizable FPGA Fabrics Targetable by the VTR CAD Tool
Synthesizable FPGA Fabrics Targetable by the VTR CAD Tool Jin Hee Kim and Jason Anderson FPL 2015 London, UK September 3, 2015 2 Motivation for Synthesizable FPGA Trend towards ASIC design flow Design
EECS 627, Lab Assignment 2
EECS 627, Lab Assignment 2 1 Introduction In this lab assignment, you will extend the process of designing your multiplier chip. You will add two more blocks (a pseudo-random test pattern generator and
Tutorial 2 Automatic Placement & Routing
Tutorial 2 Automatic Placement & Routing Please follow the instructions found under Setup on the CADTA main page before starting this tutorial. 1.1. Start Encounter Log on to a VLSI server using your EE
AMIS CDNLive Paper: A DFII Based Place and Route Interface
Table of Contents Chapter 1.0 Overview Chapter 2.0 Implementation Chapter 3.0 Digital Integration Form Chapter 4.0 To P&R Tab Chapter 5.0 From P&R Tab Chapter 6.0 Summary 1/17 Introduction Chapter 1: Overview
Agenda. Presentation Team: Agenda: Pascal Bolzhauser, Key Developer, Lothar Linhard, VP Engineering,
Welcome JAN 2009 Agenda Presentation Team: Pascal Bolzhauser, Key Developer, pascal@concept.de Lothar Linhard, VP Engineering, lothar427@concept.de Agenda: Company Overview Products: GateVision RTLVision
Concurrent, OA-based Mixed-signal Implementation
Concurrent, OA-based Mixed-signal Implementation Mladen Nizic Eng. Director, Mixed-signal Solution 2011, Cadence Design Systems, Inc. All rights reserved worldwide. Mixed-Signal Design Challenges Traditional
Outline. SoC Encounter Flow. Typical Backend Design Flow. Digital IC-Project and Verification. Place and Route. Backend ASIC Design flow
Outline Digital IC-Project and Verification Deepak Dasalukunte Backend ASIC Design flow General steps Input files Floorplanning Placement Clock-synthesis Routing Typical Backend Design Flow SoC Encounter
Creating Verilog Tutorial Netlist Release Date: 01/13/2005(Version 2)
Creating Verilog Tutorial 2-1 - Creating a verilog netlist for a schematic: The verilog netlist is necessary for automatic layout (placement and routing) tools. It contains information about the I/O pins
TRILOBYTE SYSTEMS. Consistent Timing Constraints with PrimeTime. Steve Golson Trilobyte Systems.
TRILOBYTE SYSTEMS Consistent Timing Constraints with PrimeTime Steve Golson Trilobyte Systems http://www.trilobyte.com 2 Physical implementation Rule #1 Do not change the functionality Rule #2 Meet the
Batch Processing: The Complete Synthesize, Place, and Route Flow
Batch Processing: The Complete Synthesize, Place, and Route Flow Daniel Liu, John Lee, Puneet Gupta University of California, Los Angeles, NanoCAD Lab {daniel,lee,puneet}@ee.ucla.edu Abstract Design automation
Tutorial 2.(b) : Synthesizing your design using the Synopsys Design Compiler ( For DFT Flow)
Tutorial 2.(b) : Synthesizing your design using the Synopsys Design Compiler ( For DFT Flow) Objectives: In this tutorial you will learrn to use Synopsys Design Compiler (DC) to perform hardware synthesis
CS 4120 Hardware Description Languages and Synthesis Homework 6: Introduction to Cadence Silicon Ensemble
CS 4120 Hardware Description Languages and Synthesis Homework 6: Introduction to Cadence Silicon Ensemble 0. Introduction In this homework, you will be introduced to a Place and Route tool called Silicon
UNIVERSITY OF WATERLOO
UNIVERSITY OF WATERLOO UW ASIC DESIGN TEAM: Cadence Tutorial Description: Part I: Layout & DRC of a CMOS inverter. Part II: Extraction & LVS of a CMOS inverter. Part III: Post-Layout Simulation. The Cadence
Digital IC- Project 1. Place and Route. Oskar Andersson. Oskar Andersson, EIT, LTH, Digital IC project and Verifica=on
Digital IC- Project 1 Oskar Andersson Outline Backend ASIC Design flow (Physical Design) General steps Input files Floorplanning Placement ClockTree- synthesis Rou=ng Typical Backend Design Flow Synthesis
AMS DESIGN METHODOLOGY
OVER VIEW CADENCE ANALOG/ MIXED-SIGNAL DESIGN METHODOLOGY The Cadence Analog/Mixed-Signal (AMS) Design Methodology employs advanced Cadence Virtuoso custom design technologies and leverages silicon-accurate
SystemC-to-Layout ASIC Flow Walkthrough
SystemC-to-Layout ASIC Flow Walkthrough 20.6.2015 Running the Demo You can execute the flow automatically by executing the csh shell script: csh run_asic_demo.csh The script runs all tools in a sequence.
HOMEWORK 10 CMPEN 411 Due: 4/28/ :30pm
HOMEWORK 10 CMPEN 411 Due: 4/28/2016 11:30pm Instruction First, fabrication ready the full 8 bit RISC microprocessor chip: redesign the chip (its components) to fit the entire chip fitted into the 40 pin
CMOS VLSI Design Lab 4: Full Chip Assembly
CMOS VLSI Design Lab 4: Full Chip Assembly In this final lab, you will assemble and simulate your entire MIPS microprocessor! You will build your top level chip cell by connecting the datapath, aludec,
Partitioning for Better Synthesis Results
3 Partitioning for Better Synthesis Results Learning Objectives After completing this lab, you should be able to: Use the group and ungroup commands to repartition a design within Design Analyzer Analyze
VLSI Lab Tutorial 3. Virtuoso Layout Editing Introduction
VLSI Lab Tutorial 3 Virtuoso Layout Editing Introduction 1.0 Introduction The purpose of this lab tutorial is to guide you through the design process in creating a custom IC layout for your CMOS inverter
Chip Core. Final Assembly. Core Sizes. Connecting Core to Pads. Core. Pad Ring The connection to the outside world
Final Assembly Your final project chip consists of a core and a pad ring Core is the guts Pad ring (or pad frame) connects the guts to the outside world It s critical to do a functional simulation of your
Cell-Based Design Flow. 林丞蔚
Cell-Based Design Flow 林丞蔚 cultom@viplab.cs.nctu.edu.tw 1 Outline Overview Design Flow 1 RTL Development Synthesis Gate Level Simulation Design Flow 2 Placement and Routing Example Design IC Contest 2006
ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS)
ESE 570 Cadence Lab Assignment 2: Introduction to Spectre, Manual Layout Drawing and Post Layout Simulation (PLS) Objective Part A: To become acquainted with Spectre (or HSpice) by simulating an inverter,
FABRICATION TECHNOLOGIES
FABRICATION TECHNOLOGIES DSP Processor Design Approaches Full custom Standard cell** higher performance lower energy (power) lower per-part cost Gate array* FPGA* Programmable DSP Programmable general
Final Assembly. Chip Core
Final Assembly Your final project chip consists of a core and a pad ring Core is the guts Pad ring (or pad frame) connects the guts to the outside world It s critical to do a functional simulation of your
Cadence Tutorial 2: Layout, DRC/LVS and Circuit Simulation with Extracted Parasitics
Cadence Tutorial 2: Layout, DRC/LVS and Circuit Simulation with Extracted Parasitics Introduction This tutorial describes how to generate a mask layout in the Cadence Virtuoso Layout Editor. Use of DIVA
Tutorial I: Cadence Innovus ECE6133: Physical Design Automation of VLSI Systems Georgia Institute of Technology Prof. Sung Kyu Lim
Tutorial I: Cadence Innovus ECE6133: Physical Design Automation of VLSI Systems Georgia Institute of Technology Prof. Sung Kyu Lim I. Setup for Cadence Innovus 1. Copy the following files into your working
Instruction on padframe
Instruction on padframe The padframe is a 40-pins padframe for the AMI ABN 1.6um process from MOSIS located at http://www.mosis.org/cell-libraries/scn16-pads/. You should download the CIF file from the
MOSAID Semiconductor
MOSAID Semiconductor Fabr-IC (A Single-Chip Gigabit Ethernet Switch With Integrated Memory) @Hot Chips Dave Brown Chief Architect July 4, 2001 Fabr-IC Feature summary 2 Gig ports 1 gig port for stacking
Pipelined MIPS CPU Synthesis and On-Die Representation ECE472 Joseph Crop Stewart Myers
Pipelined MIPS CPU Synthesis and On-Die Representation ECE472 Joseph Crop Stewart Myers 2008 Table of Contents Introduction... 3 Steps Taken and Simulation... 3 Pitfalls... 8 Simulated Delay... 9 APPENDIX
Silicon Virtual Prototyping: The New Cockpit for Nanometer Chip Design
Silicon Virtual Prototyping: The New Cockpit for Nanometer Chip Design Wei-Jin Dai, Dennis Huang, Chin-Chih Chang, Michel Courtoy Cadence Design Systems, Inc. Abstract A design methodology for the implementation
Synopsys Custom Designer Tutorial for a chip integra7on using the University of Utah Standard Cell Libraries In ON Semiconductor 0.
Synopsys Custom Designer Tutorial for a chip integra7on using the University of Utah Standard Cell Libraries In ON Semiconductor 0.5u C5 CMOS Version 6.0 Overview This tutorial will take you through the
Abstract Editor (Last updated: Oct. 23, 2008)
Abstract Editor (Last updated: Oct. 23, 2008) Abstract Editor Tutorial This tutorial has been created to discuss all of the steps needed to create an abstract Library Exchange Format (LEF) file for custom
Bits and Pieces of CS250 s Toolflow
Bits and Pieces of CS250 s Toolflow CS250 Tutorial 2 (Version 092509a) September 25, 2009 Yunsup Lee In this tutorial you will learn what each VLSI tools used in class are meant to do, how they flow, file
Virtuoso Custom Design Platform GXL. Open Database. PDKs. Constraint Management. Customer IP
Virtuoso Custom Design Platform GL The Cadence Virtuoso custom design platform is the industry s leading design system for complete front-to-back analog, RF, mixed-signal, and custom digital design. The
Digital System Design Lecture 2: Design. Amir Masoud Gharehbaghi
Digital System Design Lecture 2: Design Amir Masoud Gharehbaghi amgh@mehr.sharif.edu Table of Contents Design Methodologies Overview of IC Design Flow Hardware Description Languages Brief History of HDLs
Prepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology
Prepared by Dr. Ulkuhan Guler GT-Bionics Lab Georgia Institute of Technology OUTLINE Introduction Mapping for Schematic and Layout Connectivity Generate Layout from Schematic Connectivity Some Useful Features
The Microprocessor as a Microcosm:
The Microprocessor as a Microcosm: A Hands-On Approach to VLSI Design Education David Harris David_Harris@hmc.edu November 2002 Harvey Mudd College Claremont, CA Outline Introduction Course Organization
HOMEWORK 9 CMPEN 411 Due: 4/12/ :30pm
HOMEWORK 9 CMPEN 411 Due: 4/12/2016 11:30pm Learning Objective Complete the full 8 bit RISC microprocessor chip design by placing the processor core design into the 40 pin 'tiny' chip pad frame. Do verify
Bits and Pieces of CS250 s Toolflow
Bits and Pieces of CS250 s Toolflow CS250 Tutorial 2 (Version 091210a) September 12, 2010 Yunsup Lee In this tutorial you will learn what each VLSI tools used in class are meant to do, how they flow, file
Design Solutions in Foundry Environment. by Michael Rubin Agilent Technologies
Design Solutions in Foundry Environment by Michael Rubin Agilent Technologies Presenter: Michael Rubin RFIC Engineer, R&D, Agilent Technologies former EDA Engineering Manager Agilent assignee at Chartered
ECE471/571 Energy Efficient VLSI Design Project 2 Cadence Setup and Creation of an Inverter Due Date 11:30 am on Friday, February 2 nd, 2018
ECE471/571 Energy Efficient VLSI Design Project 2 Cadence Setup and Creation of an Inverter Due Date 11:30 am on Friday, February 2 nd, 2018 Introduction This project will first walk you through the setup
Design Flow for a ASIC design in the rad hard CERN-IBM library
Design Flow for a ASIC design in the rad hard CERN-IBM library May 21, 2001 5:11 pm A. Kluge 1.0 License Server cadstat or cadstat17 summarizes the use of the licenses. With lmremove name_of_license user_host_entries(from
Graphics: Alexandra Nolte, Gesine Marwedel, Universität Dortmund. RTL Synthesis
Graphics: Alexandra Nolte, Gesine Marwedel, 2003 Universität Dortmund RTL Synthesis Purpose of HDLs Purpose of Hardware Description Languages: Capture design in Register Transfer Language form i.e. All
Tutorial for Altera DE1 and Quartus II
Tutorial for Altera DE1 and Quartus II Qin-Zhong Ye December, 2013 This tutorial teaches you the basic steps to use Quartus II version 13.0 to program Altera s FPGA, Cyclone II EP2C20 on the Development
DIGITAL SANDBOX WORKSHOP Summer Digital Sandbox Mission
DIGITAL SANDBOX WORKSHOP Summer 2004 Sandbox CAD Support Digital Sandbox Mission The virtual SoC design support facility provides "industrial strength" hardware, software, EDA tools, workflows, and technical
EECE 285 VLSI Design. Cadence Tutorial EECE 285 VLSI. By: Kevin Dick Co-author: Jeff Kauppila Co-author: Dr. Arthur Witulski
Cadence Tutorial EECE 285 VLSI By: Kevin Dick Co-author: Jeff Kauppila Co-author: Dr. Arthur Witulski 1 Table of Contents Purpose of Cadence 1) The Purpose of Cadence pg. 4 Linux 1) The Purpose of Linux
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Lab #2: Layout and Simulation
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Lab #2: Layout and Simulation NTU IC541CA 1 Assumed Knowledge This lab assumes use of the Electric
CADENCE SETUP. ECE4430-Analog IC Design
CADENCE SETUP This short tutorial shows how to configure Cadence to use the NCSU Cadence Design Kit (CDK) with access to the ON Semiconductor C5 0.5-µm and the TSMC 0.35-µm CMOS processes libraries. In
RTL Coding General Concepts
RTL Coding General Concepts Typical Digital System 2 Components of a Digital System Printed circuit board (PCB) Embedded d software microprocessor microcontroller digital signal processor (DSP) ASIC Programmable
Using makemem template
Using makemem template V1.2 November 18, 2004 Modified by Erik Brunvand for CS/EE 6710 Nov 2006 This document describes how to set up to use makemem the ROM and SRAM generator. It also gives an example
Towards Automation of ASIC TSMC 0.18 m Standard Cell Library Development
BRADLEY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING AT VIRGINIA POLYTECHNIQUE INSTITUTE AND STATE UNIVERSITY Towards Automation of ASIC TSMC 0.18 m Standard Cell Library Development DJIGBENOU, Jeannette
ECE471/571 Energy Ecient VLSI Design
ECE471/571 Energy Ecient VLSI Design Project 2 Cadence Setup and Creation of an Inverter Due Date 11:30pm on Friday, January 30 th 2015 Introduction This project will rst walk you through the setup for
Custom Design Formal Equivalence Checking Based on Symbolic Simulation. Overview. Verification Scope. Create Verilog model. Behavioral Verilog
DATASHEET Custom Design Formal Equivalence Checking Based on Symbolic Simulation High-quality equivalence checking for full-custom designs Overview is an equivalence checker for full custom designs. It
Design rule illustrations for the AMI C5N process can be found at:
Cadence Tutorial B: Layout, DRC, Extraction, and LVS Created for the MSU VLSI program by Professor A. Mason and the AMSaC lab group. Revised by C Young & Waqar A Qureshi -FS08 Document Contents Introduction
GUIDELINES FOR USE SMIC 0.18 micron, 1.8 V high-density synchronous single port SRAM IP blocks compiler
GUIDELINES FOR USE SMIC 0.18 micron, 1.8 V high-density synchronous single port SRAM IP blocks compiler Ver. 1.0 November 2010 www.ntlab.com CONTENT 1. DESCRIPTION OF THE COMPILER... 3 1.1 GENERAL CHARACTERISTICS
Getting a Quick Start 2
2 Getting a Quick Start 2 This chapter walks you through the basic synthesis design flow (shown in Figure 2-1). You use the same basic flow for both design exploration and design implementation. The following
Synopsys ASIC Tutorial
Synopsys ASIC Tutorial Version 11.0 Updated November 30, 2015 Linux log in and tutorial Synthesis with dc_shell Timing Area Chip implementaeon with icc_shell Placement RouEng Clock tree Finishing Chip
Laker 3 Custom Design Tools
Datasheet Laker 3 Custom Design Tools Laker 3 Custom Design Tools The Laker 3 Custom Design Tools form a unified front-to-back environment for custom circuit design and layout. They deliver a complete
EE115C Digital Electronic Circuits. Tutorial 4: Schematic-driven Layout (Virtuoso XL)
EE115C Digital Electronic Circuits Tutorial 4: Schematic-driven Layout (Virtuoso XL) This tutorial will demonstrate schematic-driven layout on the example of a 2-input NAND gate. Simple Layout (that won
Lecture 11 Logic Synthesis, Part 2
Lecture 11 Logic Synthesis, Part 2 Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese461/ Write Synthesizable Code Use meaningful names for signals and variables
EE183 LAB TUTORIAL. Introduction. Projects. Design Entry
EE183 LAB TUTORIAL Introduction You will be using several CAD tools to implement your designs in EE183. The purpose of this lab tutorial is to introduce you to the tools that you will be using, Xilinx
101-1 Under-Graduate Project Digital IC Design Flow
101-1 Under-Graduate Project Digital IC Design Flow Speaker: Ming-Chun Hsiao Adviser: Prof. An-Yeu Wu Date: 2012/9/25 ACCESS IC LAB Outline Introduction to Integrated Circuit IC Design Flow Verilog HDL
THERMAL GRADIENT AND IR DROP AWARE DESIGN FLOW FOR ANALOG-INTENSIVE ASICS
THERMAL GRADIENT AND IR DROP AWARE DESIGN FLOW FOR ANALOG-INTENSIVE ASICS Pacific MicroCHIP Corp. AIMS-CAT November, 2009 OUTLINE Motivation Thermal Gradient Impact Simulation Methodology Results Accurate
Actel Libero TM Integrated Design Environment v2.3 Structural Schematic Flow Design Tutorial
Actel Libero TM Integrated Design Environment v2.3 Structural Schematic Flow Design Tutorial 1 Table of Contents Design Flow in Libero TM IDE v2.3 Step 1 - Design Creation 3 Step 2 - Design Verification
ECE 425: Introduction to VLSI System Design Machine Problem 0 Due: Friday 11:59pm, Sep. 15th, 2017
ECE 425: Introduction to VLSI System Design Machine Problem 0 Due: Friday 11:59pm, Sep. 15th, 2017 You will spend most of your lab time using the Virtuoso design tools from Cadence Design Systems. Virtuoso
UG0787 User Guide PolarFire FPGA Block Flow
UG0787 User Guide PolarFire FPGA Block Flow NOTE: PDF files are intended to be viewed on the printed page; links and cross-references in this PDF file may point to external files and generate an error