Cell-Based IC Physical Design & Verification SOC Encounter. Advisor : 李昆忠 Presenter : 蕭智元
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1 Cell-Based IC Physical Design & Verification SOC Encounter Advisor : 李昆忠 Presenter : 蕭智元 Reference: SOC Encounter Training Manual, 2007, edited by CIC.
2 Introduction We ll use some EDA tools to transform synthesized design to layout Tools SOC Encounter: Floorplanningand APR icfb: Cell replacement with layout Calibre: DRC, LVS Layout. 2
3 Prepare File Unix% cp -r /home4/classuser/sys0701/sys0701ta1/soce. Library Physical Library (.lef) Timing Library (.lib) User Data Gate-Level netlist (.v) SDC constraints (.sdc) IO constraint (.ioc) Layout. 3
4 Gate-Level netlist (1/3) Synthesized RTL code assign statement is not allowed. To solve this, typing set_fix_multiple_port_nets all buffer_constants in command window before compile. *cell* problem. To solve this, change_names rule verilog verbose -hierarchy in command window after compile. Layout. 4
5 Gate-Level netlist (2/3) *cell* problem Layout. 5
6 Gate-Level netlist (3/3) When Verilogfile is ready Put all verilogfile (CHIP.v) into SOC_tutor/vlog Adding I/O pads into CHIP.v input pad :PDIDGZ output pad :PDO02CDG Layout. 6
7 SDC Constraint Make use of the dc constraint Make sure the port name Layout. 7
8 IO Constraint (1/3) Layout. 8
9 IO Constraint (2/3) Pad: CORNER0 NW Pad: PAD_RESET N Pad: PAD_CoreVDD N Pad: PAD_IOVDD1 N Pad: CORNER2 SE Pad: PAD_CLK S Pad: PAD_CoreVSS S Pad: PAD_IOGND1 S Pad: CORNER1 NE Pad: PAD_O2 W Pad: PAD_IOVDD W Pad: PAD_O3 W Pad: CORNER3 SW Pad: PAD_O0 E Pad: PAD_IOVSS E Pad: PAD_O1 E Layout. 9
10 IO Constraint (3/3) Pad: CORNER0 NW PCORNERDGZ Pad: PAD_CoreVDD N PVDD1DGZ Pad: PAD_CoreVSS S PVSS1DGZ Pad: PAD_IOVDD S PVDD2DGZ Pad: PAD_IOVSS E PVSS2DGZ Put a pair of PAD POWER PAD about every 7 I/O pads. Layout. 10
11 Starting SOC Encounter In /SOC_tutor directory, type encounter Menu bar Artwork window Layout. 11
12 Import Your Design (1/6) Design Design Import Fill CHIP Choose CHIP.v Choose Layout.. Layout. 12 Press Add to add file
13 Import Your Design (2/6) Choose Library/lib/slow.lib and Library/lib/tpz013g3wc.lib Choose Library/lib/fast.lib and Library/lib/tpz013lt.lib Choose Library/lib/typical.lib and Library/lib/tpz013g3tc.lib Layout. 13
14 Import Your Design (3/6) 1 Layout. 14
15 Import Your Design (4/6) CHIP.sdc & CHIP.ioc : Layout_Design/ Layout. 15
16 Import Your Design (5/6) Layout. 16
17 Import Your Design (6/6) Layout. 17
18 Global Net Connect (1/2) Floorplan Connect Global Net Fill in VDD Fill in VDD Press Add to List Layout. 18
19 Global Net Connect (2/2) 1. Choose Nets, and fill in VDD. Press Add to List. 2. Choose Tie High. Press Add to List 6 datas 3. Choose Pins, and fill in GND. Fill in GND into To Global Net. Press Add to List. 4. Choose Nets, and fill in GND. Press Add to List. 5. Choose Tie Low. Press Add to List Press Apply and Check, see if there is any error Layout. 19
20 Specify Floorplan (1/3) Floorplan Specify Floorplan Fill in 1 and 0.7 All fill in 70 Layout. 20
21 Specify Floorplan (2/3) Layout. 21
22 Specify Floorplan (3/3) Design Save Design Layout. 22
23 Powerplan (1/6) Power Power Planning Add Rings VSS and VDD only Layer of Top and Bottom: ME5 Layer of Left and Right: ME4 Width: 8 Press Update Layout. 23
24 Powerplan (2/6) Switch to Advanced Choose Use wire group And Interleaving Number of bits: 3 Layout. 24
25 Powerplan (3/6) Layout. 25
26 Powerplan (4/6) Route Special Route VSS and VDD only Pad pins only Layout. 26
27 Powerplan (5/6) Layout. 27
28 Powerplan (6/6) Design Save Design Layout. 28
29 Place (1/2) Place Standard Cell And Blocks Prototyping: fast Full: complete Choose two of these Layout. 29
30 Place (2/2) Layout. 30
31 Trail Route (1/2) Route Trail Route Layout. 31
32 Trail Route (2/2) Layout. 32
33 Trail Route: Time Analysis (1/2) Timing Specify Analysis Condition Specify RC Extraction Mode Choose two of these Layout. 33
34 Trail Route: Time Analysis (2/2) Timing Extract RC, and press OK Timing Timing Analysis, and press OK Terminal Check the Slack If there is some negative Timing Slack, you can Timing Optimization If still negative, you must synthesis again Layout. 34
35 Check Place Check Placement Press OK Layout. 35
36 Trail Route Design Save Design Layout. 36
37 Clock Tree Synthesis (1/3) Clock Create Clock Tree Spec Fill in clkbuf Fill in clkinv Save to CHIP.ctstch Clock Specify Clock Tree Press OK Layout. 37
38 Clock Tree Synthesis (2/3) Clock Synthesize Clock tree Press OK Layout. 38
39 Clock Tree Synthesis (3/3) Design Save Design Layout. 39
40 Connect follpower Route Special Route.. 1.Standard cell pins 2.pass ok Layout. 40
41 Connect follpower Layout. 41
42 Add io filler Type source addiofiller_tpz.cmd in terminal Layout. 42
43 NanoRoute (1/2) Route NanoRoute Route.. Choose two of these Press Attribute Layout. 43
44 NanoRoute (2/2) Choose two of these Fill in 10 Choose 1 Choose TRUE Layout. 44
45 Timing Analysis (1/4) Timing Specify Analysis Condition Specify Operating Condition/PVT Layout. 45
46 Timing Analysis (2/4) Timing Specify Analysis Condition Specify RC Extraction Mode Choose Assume Metal Fill Choose Detail Layout. 46
47 Timing Analysis (3/4) Timing Extract RC OK Timing Timing Analysis Layout. 47
48 Timing Analysis (4/4) Terminal Check the Slack If there is some negative Timing Slack, you can Timing Optimization If still negative, you must synthesis again Layout. 48
49 Add Filler (1/2) Place Filler Add.. In Add Filler Form, press select Press Add Select all Layout. 49
50 Add Filler (2/2) Layout. 50
51 Check Verify Connectivity Verify Geometry Place Check placement Layout. 51
52 Save Design Step 1. Design Save Design File name : finish.enc Step 2. Design Save GDS Output Stream File : CHIP.gds Map File : streamout.map Units Step 3. Design Save Netlist File name : CHIP_lvs.v Step 4. Design Save DEF File name : CHIP.def Step 5. Design Exit Layout. 52
53 Prepare for Verification Stream In Design Stream Out Design Layout. 53
54 Stream In Design (1/3) Copy CHIP.gds to directory icfb Source the file source /usr/cad/mentor/cic/calibre.cshrc icfb & Workstation /Library/icfb directory Layout. 54
55 Stream In Design (2/3) File Import Stream CHIP.gds CHIP Virtuoso4.4_0.13um_Ver2.1a.1.tf Layout. 55
56 Stream In Design (3/3) File Import Stream Input File: tpz013g3.gds (the file is in the GDSII directory) Top Cell Name: empty Press OK File Import Stream Input File: tsmc13gfsg_fram.gds (the file is in the GDSII directory) Top Cell Name: empty Press OK Layout. 56
57 Stream Out Design File Export Stream CHIP CHIP layout CHIP.gds2 Layout. 57
58 Design Check DRC LVS Layout. 58
59 DRC Copy CHIP.gds2 from directory icfb to verify/drc Edit file Calibre-drc-cur Replace Layout PATH to Layout PATH CHIP.gds2 Replace Layout PRIMARY to Layout PRIMARY CHIP Execute Calibre calibre -drc -hier Calibre-drc-cur Check result Open file drc.summary, it should be no errors Layout. 59
60 LVS (1/3) Copy CHIP.gds2 to directory LVS Copy CHIP_lvs.v to directory LVS Transform CHIP_lvs.v to spice format v2lvs -v CHIP_lvs.v -l tsmc13gfsg_fram_lvs.v -o CHIP.spi -s tsmc13gfsg_fram_lvs.spi s1 VDD s0 GND Layout. 60
61 LVS (2/3) Edit file Calibre-lvs-cur Replace SOURCE PRIMARY to SOURCE PRIMARY CHIP Replace SOURCE PATH to SOURCE PATH CHIP.spi Replace Layout PRIMARY to Layout PRIMARY CHIP Replace Layout PATH to Layout PATH CHIP.gds2 Layout. 61
62 LVS (3/3) Execute Calibre calibre -lvs -spice layout.spi -hier -auto Calibre-lvs-cur Layout. 62
63 Result Check result Open file lvs.report If there is a smile, the result of LVS is correct Layout. 63
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