Introduction to CMOS VLSI Design. Lecture 2: MIPS Processor Example. David Harris. Harvey Mudd College Spring Outline

Size: px

Start display at page:

Download "Introduction to CMOS VLSI Design. Lecture 2: MIPS Processor Example. David Harris. Harvey Mudd College Spring Outline"

Brice Walsh
5 years ago
Views:

1 Introduction to CMOS VLSI Design Lecture 2: MIPS Processor Exmple Dvid Hrris Hrvey Mudd College Spring 24 Outline Design Prtitioning MIPS Processor Exmple Architecture Microrchitecture Logic Design Circuit Design Physicl Design Fbriction, Pckging, Testing Slide 2

2 Activity 2 Sketch stick digrm for 4-input NOR gte Slide 3 Activity 2 Sketch stick digrm for 4-input NOR gte VDD A B C D Y GND Slide 4 2

3 Coping with Complexity How to design System-on-Chip? Mny millions (soon billions!) of trnsistors Tens to hundreds of engineers Structured Design Design Prtitioning Slide 5 Structured Design Hierrchy: Divide nd Conquer Recursively system into modules Regulrity Reuse modules wherever possible Ex: Stndrd cell librry Modulrity: well-formed interfces Allows modules to be treted s blck boxes Loclity Physicl nd temporl Slide 6 3

4 Design Prtitioning Architecture: User s perspective, wht does it do? set, registers MIPS, x86, Alph, PIC, ARM, Microrchitecture Single cycle, multcycle, pipelined, supersclr? Logic: how re functionl blocks constructed Ripple crry, crry lookhed, crry select dders Circuit: how re trnsistors used Complementry CMOS, pss trnsistors, domino Physicl: chip lyout Dtpths, memories, rndom logic Slide 7 Gjski Y-Chrt Slide 8 4

5 MIPS Architecture Exmple: subset of MIPS processor rchitecture Drwn from Ptterson & Hennessy MIPS is 32-bit rchitecture with 32 registers Consider 8-bit subset using 8-bit dtpth Only implement 8 registers ($ - $7) $ hrdwired to 8-bit progrm counter Slide 9 Set Slide 5

Encoding 32-bit instruction encoding Requires four cycles to fetch on 8-bit dtpth formt exmple encoding 6 5 5 5 5 6 R dd $rd, $r, $rb r rb rd

6 Encoding 32-bit instruction encoding Requires four cycles to fetch on 8-bit dtpth formt exmple encoding R dd $rd, $r, $rb r rb rd funct I beq $r, $rb, imm op r rb imm 6 26 J j dest op dest Slide f = ; f - = - f n = f n- + f n-2 f =,, 2, 3, 5, 8, 3, Fiboncci (C) Slide 2 6

7 Fiboncci (Assembly) st sttement: n = 8 How do we trnslte this to ssembly? Slide 3 Fiboncci (Assembly) Slide 4 7

8 Fiboncci (Binry) st sttement: ddi $3, $, 8 How do we trnslte this to mchine lnguge? Hint: use instruction encodings below formt exmple encoding R dd $rd, $r, $rb r rb rd funct I beq $r, $rb, imm 6 op r rb imm 6 26 J j dest op dest Slide 5 Fiboncci (Binry) Mchine lnguge progrm Slide 6 8

9 MIPS Microrchitecture Multicycle µrchitecture from Ptterson & Hennessy PCEn PCWriteCond PCWrite IorD Outputs MemRed MemWrite Control MemtoReg PCSource ALUOp ALUSrcB ALUSrcA RegWrite PC M ux Address Write dt Memory MemDt [3:26] [25 : 2] [2 : 6] [5 : ] register [7: ] Memory dt register IRWrite[3:] [5: ] Op [5: ] M u x M u x RegDst [5: ] 6 8 Shift left 2 Red register Red register 2 Write register Write dt Registers Red dt Red dt 2 A B M u 2 x 3 M ux ALU control Zero ALU ALU result ALUControl Jump ddress ALUOut 2 M u x [5 : ] Slide 7 Multicycle Controller fetch MemRed ALUSrcA = IorD = IRWrite3 ALUSrcB = ALUOp = PCWrite PCSource = MemRed ALUSrcA = IorD = IRWrite2 ALUSrcB = ALUOp = PCWrite PCSource = 2 MemRed ALUSrcA = IorD = IRWrite ALUSrcB = ALUOp = PCWrite PCSource = 3 MemRed ALUSrcA = IorD = IRWrite ALUSrcB = ALUOp = PCWrite PCSource = decode/ register fetch 4 ALUSrcA = ALUSrcB = ALUOp = Reset Memory ddress computtion 5 ALUSrcA = ALUSrcB = ALUOp = (Op = 'L B ') or (Op = 'S B ') Execution 9 ALUSrcA = ALUSrcB = ALUOp= (Op = R-type) Brnch Jump completion completion 2 ALUSrcA = ALUSrcB = PCWrite ALUOp = PCSource = PCWriteCond PCSource = (Op = 'BEQ') (Op = 'J') 6 (Op = 'LB') (Op = 'S B') Memory ccess 8 Memory ccess R-type completion MemRed IorD = MemWrite IorD = RegDst = RegWrite MemtoReg = 7 Write-bck step RegDst= RegWrite MemtoReg = Slide 8 9

10 PC PCEn M ux Address Write dt Memory MemDt register Memory dt register PCWriteCond PCWrite IorD MemRed MemWrite MemtoReg IRWrite[3:] Outputs Control Op [5: ] M u x PCSource ALUOp ALUSrcB ALUSrcA RegWrite RegDst [5: ] 6 8 Shift left 2 [3:26] [25 : 2] [2 : 6] M [5 : ] ux [5: ] [7 : ] Red register Red Red register 2 dt Registers Write Red register dt 2 Write dt [5: ] A B 2 3 M u x ALU control Zero ALU ALU result ALUControl Jump ddress ALUOut M u x 2 Logic Design Strt t top level Hierrchiclly decompose MIPS into units Top-level interfce crystl oscilltor 2-phse clock genertor ph ph2 reset memred memwrite MIPS processor dr writedt memdt externl memory Slide 9 Block Digrm memwrite memred Mu x controller luop[:] lucontrol ph op[5:] zero lusrc lusrcb[:] pcen pcsource[:] memtoreg regdst iord regwrite irwrite[3:] funct[5:] lucontrol[2:] ph2 reset dr[7:] dtpth writedt[7:] memdt[7:] Slide 2

11 Hierrchicl Design mips controller lucontrol dtpth stndrd cell librry bitslice zipper lu inv4x flop rmslice fulldder or2 nd2 mux4 nor2 inv nnd2 mux2 tri Slide 2 HDLs Hrdwre Description Lnguges Widely used in logic design Verilog nd VHDL Describe hrdwre using code Document logic functions Simulte logic before building Synthesize code into gtes nd lyout Requires librry of stndrd cells Slide 22

12 Verilog Exmple module fulldder(input, b, c, output s, cout); b b c cout c crry sum sum s(, b, c, s); s fulldder crry c(, b, c, cout); cout s endmodule module crry(input, b, c, output cout) ssign cout = (&b) (&c) (b&c); endmodule Slide 23 Circuit Design How should logic be implemented? NANDs nd NORs vs. ANDs nd ORs? Fn-in nd fn-out? How wide should trnsistors be? These choices ffect speed, re, power Logic synthesis mkes these choices for you Good enough for mny pplictions Hnd-crfted circuits re still better Slide 24 2

13 Exmple: Crry Logic ssign cout = (&b) (&c) (b&c); Trnsistors? Gte Delys? Slide 25 Exmple: Crry Logic ssign cout = (&b) (&c) (b&c); b c b c g g2 g3 x y z g4 cout Trnsistors? Gte Delys? Slide 26 3

14 Exmple: Crry Logic ssign cout = (&b) (&c) (b&c); p c c n b p3 n3 b p2 i3 i n2 b b p4 i4 p5 cn n5 i2 n4 p6 n6 cout Trnsistors? Gte Delys? Slide 27 Gte-level Netlist module crry(input, b, c, output cout) wire x, y, z; nd g(x,, b); nd g2(y,, c); nd g3(z, b, c); or g4(cout, x, y, z); endmodule b c b c g g2 g3 x y z g4 cout Slide 28 4

15 Trnsistor-Level Netlist module crry(input, b, c, output cout) wire i, i2, i3, i4, cn; trnif n(i,, ); trnif n2(i,, b); trnif n3(cn, i, c); trnif n4(i2,, b); trnif n5(cn, i2, ); trnif p(i3,, ); trnif p2(i3,, b); trnif p3(cn, i3, c); trnif p4(i4,, b); trnif p5(cn, i4, ); trnif n6(cout,, cn); trnif p6(cout,, cn); endmodule p c c n b p2 p3 i3 n3 i b n2 b b p4 i4 p5 cn n5 i2 n4 p6 n6 cout Slide 29 SPICE Netlist.SUBCKT CARRY A B C COUT VDD GND MN I A GND GND NMOS W=U L=.8U AD=.3P AS=.5P MN2 I B GND GND NMOS W=U L=.8U AD=.3P AS=.5P MN3 CN C I GND NMOS W=U L=.8U AD=.5P AS=.5P MN4 I2 B GND GND NMOS W=U L=.8U AD=.5P AS=.5P MN5 CN A I2 GND NMOS W=U L=.8U AD=.5P AS=.5P MP I3 A VDD VDD PMOS W=2U L=.8U AD=.6P AS= P MP2 I3 B VDD VDD PMOS W=2U L=.8U AD=.6P AS=P MP3 CN C I3 VDD PMOS W=2U L=.8U AD=P AS=P MP4 I4 B VDD VDD PMOS W=2U L=.8U AD=.3P AS=P MP5 CN A I4 VDD PMOS W=2U L=.8U AD=P AS=.3P MN6 COUT CN GND GND NMOS W=2U L=.8U AD=P AS=P MP6 COUT CN VDD VDD PMOS W=4U L=.8U AD=2P AS=2P CI I GND 2FF CI3 I3 GND 3FF CA A GND 4FF CB B GND 4FF CC C GND 2FF CCN CN GND 4FF CCOUT COUT GND 2FF.ENDS Slide 3 5

16 Physicl Design Floorpln Stndrd cells Plce & route Dtpths Slice plnning Are estimtion Slide 3 MIPS Floorpln I/O pds mips (4.6 Mλ2) 5 λ I/O pds 35 λ 69 λ control 5 λ x 4 λ (.6 Mλ2) wiring chnnel: 3 trcks = 24 λ zipper 27 λ x 25 λ dtpth 27 λ x 5 λ (2.8 Mλ2) lucontrol 2 λ x λ (2 kλ2) I/O pds bitslice 27 λ x λ 27 λ 35 λ I/O pds 5 λ Slide 32 6

17 MIPS Lyout Slide 33 Stndrd Cells Uniform cell height Uniform well height M V DD nd GND rils M2 Access to I/Os Well / substrte tps Exploits regulrity Slide 34 7

Synthesized Controller Synthesize HDL into gte-level netlist Plce & Route using stndrd cell librry Slide 35 Pitch Mtching Synthesized controller re is mostly wires Design is smller if wires run

18 Synthesized Controller Synthesize HDL into gte-level netlist Plce & Route using stndrd cell librry Slide 35 Pitch Mtching Synthesized controller re is mostly wires Design is smller if wires run through/over cells Smller = fster, lower power s well! Design snp-together cells for dtpths nd rrys Pln wires into cells A A A A B Connect by butment A A A A B Exploits loclity A A A A B Tkes lots of effort A A A A B C C D Slide 36 8

Slide 37 Slice Plns Slice pln for bitslice Cell

19 MIPS Dtpth 8-bit dtpth built from 8 bitslices (regulrity) Zipper t top drives control signls to dtpth Slide 37 Slice Plns Slice pln for bitslice Cell ordering, dimensions, wiring trcks Arrnge cells for wiring loclity Slide 38 9

nother block you lredy designed Or estimte from trnsistor

20 MIPS ALU Arithmetic / Logic Unit is prt of bitslice Slide 39 Are Estimtion Need re estimtes to mke floorpln Compre to nother block you lredy designed Or estimte from trnsistor counts Budget room for lrge wiring trcks Your milege my vry! Slide 4 2

21 Design Verifiction Fbriction is slow & expensive Specifiction MOSIS.6µm: $, 3 months Stte of rt: $M, month Architecture Debugging chips is very hrd Design Limited visibility into opertion Logic Prove design is right before building! Design Logic simultion Circuit Design Ckt. simultion / forml verifiction Lyout vs. schemtic comprison Physicl Design Design & electricl rule checks Verifiction is > 5% of effort on most chips! = = = = Function Function Function Function Timing Power Slide 4 Fbriction & Pckging Tpeout finl lyout Fbriction 6, 8, 2 wfers Optimized for throughput, not ltency ( weeks!) Cut into individul dice Pckging Bond gold wires from die I/O pds to pckge Slide 42 2

22 Testing Test tht chip opertes Design errors Mnufcturing errors A single dust prticle or wfer defect kills die Yields from 9% to < % Depends on die size, mturity of process Test ech prt before shipping to customer Slide 43 22

Introduction to CMOS VLSI Design Lecture 2: MIPS Processor Example

Introduction to CMOS VLSI Design Lecture 2: MIPS Processor Example David Harris Harvey Mudd College Spring 2004 Outline Design Partitioning MIPS Processor Example Architecture Microarchitecture Logic Design