K2 40GE QSFP+ Higher Speed Ethernet Load Module

Transcription

1 K2 40GE QSFP+ Higher Speed Ethernet Lad Mdule Ixia s K2 40-Gigabit Ethernet (GE) Quad Small Frm-factr Pluggable (QSFP+) SFF-8436-cmplaint test mdule is the wrld s first-t-market layer 1 thrugh 7 measurement and analysis test slutin using a native QSFP+ MSA interface. The K2 QSFP+ lad mdule is an essential tl fr the develpment f 40GE netwrk devices such as ruters, switches, server netwrk interface cards (NICs), cnverged netwrk adapters (CNAs), and semicnductr cmmunicatins devices. K2 lad mdules measure and analyze the perfrmance f IEEE 802.3bastandard higher speed Ethernet (HSE) devices at line rate. The K2 interface is cmpatible with Ixia s chassis and brad range f Ethernet interfaces, allwing real-wrld, full prduct testing in a single bx. As part f Ixia s K2 family f HSE prducts, the 40GE QSFP+ lad mdule has the same feature set, test applicatin, and autmatin capabilities as Ixia s first-t-market 40GE and 100GE test mdules with the CFP MSA interface. HSE40GEQSFP1-01, 40GE QSFP+ Lad Mdule Ixia was an active participant in the HSE standardizatin effrt and assisted in develping the new physical cding sublayer (PCS) lanes distributin methdlgy, a key enabler f the new HSE technlgy. Highlights Industry's first 40GE IP test slutin fr layer 2 thrugh 7 12 prts per XM12 chassis (10 rack munt units) Industry s first cmmerciallyavailable PCS Lanes test system Checks cmpliance and perfrmance against the IEEE 802.3ba with a full array f statistics and realtime errr indicatrs Injects and tracks errrs in lane markers, 64/66b paylads, and synchrnizatin bits with cntrls fr different cnfiguratins f errr injectins Cmplete standardcmpliance testing fr the PCS Unframed BERT supprt with individual PCS lanes BERT test and errr injectin ver a wide range f PRBS patterns, including standard PMD supprt. A full set f BERT-related and bit errr rati (BER) statistics are available. Generates and analyses full 40GE line rate traffic Tracks and analyzes up t 1 millin flws per prt Cmprehensive layer 2-7 testing with integrated data plane and cntrl plane traffic generatin and analysis. Ixia s K2 lad mdules are valuable tls fr develpers wh are integrating firmware and sftware int new electrnics hardware, r integrating ptical transceivers int their netwrk devices and systems, especially unframed BERT test capabilities. Ixia s K2 mdules validate and benchmark the perfrmance limits f these netwrk devices by emplying layer 1, 2 and 3 stress testing; virtual scalability testing; and negative testing. Ixia s K2 lad mdules ensure that netwrk devices interperate with ther manufacturers devices Agura Rad Calabasas, CA USA Tel Dcument N.: Rev. D December Page 1

2 Key Features Industry's first 40GE IP test slutin fr layer 2 thrugh 7 12 prts per XM12 chassis (10 rack munt units) Cmpatible with XM12 ( ) and XM12 High Perfrmance chassis ( ) 2 prts per XM2 ( ) desktp chassis Industry s first cmmercially-available PCS Lanes test system Checks cmpliance and perfrmance against the IEEE 802.3ba with a full array f statistics and real-time errr indicatrs Injects and tracks errrs in lane markers, 64/66b paylads, and synchrnizatin bits with cntrls fr different cnfiguratins f errr injectins Cmplete standard-cmpliance testing fr the PCS Unframed BERT supprt with individual PCS lanes BERT test and errr injectin ver a wide range f PRBS patterns, including standard PMD supprt. A full set f BERT-related and bit errr rati (BER) statistics are available. Generates and analyses full 40GE line rate traffic Tracks and analyzes up t 1 millin flws per prt fr: Real-time latency Inter-arrival time Packet lss Data integrity Sequence checking Packet capture Cmprehensive layer 2-7 testing with integrated data plane and cntrl plane traffic generatin and analysis. Page 2

3 Specificatins Feature 40 Gigabit Ethernet Lad mdule HSE40GEQSFP1-01 Number f prts per mdule 1 Number f chassis slts per mdule 1 Maximum prts per chassis: XM12 XM12 High Perfrmance XM2 Desktp Supprted transceivers/cables Per-prt CPU speed and memry Per-prt capture buffer Interface prtcl Layer 2/3 ruting prtcl emulatin Layer 4-7 applicatin traffic testing Number f transmit flws per prt (sequential values) Number f transmit flws per prt (nn-sequential values) Number f trackable receive flws Number f stream definitins per prt QSFP+ SFF-8436 (fr cpper and ptical cables) 1 GHz / 2GB 700MB 40GE per IEEE 802.3ba standard, 40GBASE-R LAN Yes Yes Billins 1 millin 1 millin 512 In packet stream (sequential) r advanced stream (interleaved) mde, each stream definitin can generate millins f unique traffic flws. Page 3

4 Table UDF entries Packet flw statistics Transmit engine Receive engine User defined field features Filters Data field per stream Statistics and rates (cunter size: 64 bits) Errr generatin Latency measurement reslutin Latency self-calibratin MDIO Transmit line clck adjustment Clck IN/OUT 1 millin Cmprehensive packet editing functin fr emulating large numbers f sphisticated flws. Entries f up t 256 bytes, using lists f values can be specified and placed at designated ffsets within a stream. Each list cnsists f an ffset, a size, and a list f values in a table frmat. Track ver 1 millin flws Wire-speed packet generatin with timestamps, sequence numbers, data integrity signature, and packet grup signatures Wire-speed packet filtering, capturing, real-time latency and inter-arrival time fr each packet grup, data integrity, and sequence checking Fixed, increment r decrement by user-defined step, value lists, range lists, cascade, randm, and chained 48-bit surce/destinatin address, 2x128-bit user-definable pattern and ffset, frame length range, CRC errr, data integrity errr, sequence checking errr (small, big, reverse) Fixed, increment r decrement by user-defined step, value lists, range lists, cascade, randm, and chained Link state, line speed, frames sent, valid frames received, bytes sent/received, fragments, undersize, versize, CRC errrs, VLAN tagged frames, 6 userdefined stats, capture trigger (UDS 3), capture filter (UDS 4), user-defined stat 5, user-defined stat 6, 8 QS cunters, data integrity frames, data integrity errrs, sequence checking frames, sequence checking errrs, ARP, and ping requests and replies CRC (gd/bad/nne), undersize, versize 2.5 nansecnds and is cmpatible with all f Ixia s 10GbE, 1GbE fiber, and 10/100/1000Mbps Ethernet, ATM, and packet ver SONET lad mdules Ability t calibrate and remve inherent latency frm any MSA-cmpliant 40GE CFP transceiver MDIO supprt is prvided fr CFP MSA cmpliant transceivers Ability t adjust the parts per millin (ppm) line frequency ver a range f -100 t +100 ppm The lad mdule prvides tw pairs f female SMA caxial cnnectrs ne fr clck input and ne fr clck utput t allw the device under test (DUT) t frequency-lck with the lad mdule interface. When running ff an external clck surce, the clck input signal must meet the requirements listed in the current Ixia Hardware and Reference Manual. Page 4

5 Layer 1 BERT capability The lad mdule supprts the fllwing BERT features n 40Gb/s speeds: User-selected PRBS pattern fr each PCS Lane User selects frm a wide range f PRBS data patterns t be transmitted (true and cmplement) with the ability t invert the patterns Send single, cntinuus, and expnentially cntrlled amunts f errr injectin Wide range f statistics, including: Pattern Lck Pattern Transmitted Pattern Received Ttal Number f Bits Sent and Received Ttal Number f Errrs Sent and Received Bit Errr Rati (BER) Number f Mismatched 1 s and 0 s Lane Stats Gruping per lambda fr SMF and MMF 40GE based n IEEE 802.3ba-defined physical medium dependent (PMD). 40GE physical cding sublayer (PCS) test features: Per PCS lane, transmit lane mapping Per PCS lane, skew insertin capability Per PCS lane, lane marker, r lane marker and paylad errr injectins Per PCS lane, receive lanes statistics IPv4, IPv6, UDP, TCP checksum Frame length cntrls Preamble view Link fault signaling IEEE 802.3ba-cmpliant PCS transmit and receive side test capabilities Supprts all cmbinatins f PCS lane mapping: Default, Increment, Decrement, Randm, and Custm User selectable frm zer up t 3 micrsecnds f PCS lane skew insertin n the transmit side User-selectable ability t inject errrs int the PCS Lane Marker and simultaneusly int PCS Lane Marker and Paylad fields. This includes the ability t inject sync bit errrs int the Lane Marker and Paylad. User can cntrl the PCS lane, number r errrs, and perid cunt; and manage the repetitin f the injected errrs. PCS Sync Header and Lane Marker Lck, Lane Marker mapping, Relative lane deskew up t 52 micrsecnds, Sync Header and PCS Lane Marker Errr cunters, indicatrs fr Lss f Synch Header and Lane Marker, BIP8 errrs Hardware checksum generatin and verificatin Fixed, randm, weighted randm, r increment by user-defined step, randm, weighted randm Allws the user t select t view and edit the preamble cntents Generate lcal and remte faults with cntrls fr the number f faults and rder f faults, plus the ability t select the ptin t have the transmit prt ignre link faults frm a remte link partner Page 5

6 Operating temperature range 41 F t 95 F (5 C t 35 C), ambient air i Applicatin Supprt IxExplrer TM : Layer 2-3 wire-speed traffic generatin and analysis and layer 1 BERT and IEEE 802.3ba HSE PCS Lanes testing. IxAutmate TM : Autmated test envirnment fr layer 2-3 data and cntrl plane testing, includes RFC-based test suites IxNetwrk TM : Prvides wire-rate traffic generatin with service mdeling that builds realistic, dynamicallycntrllable data-plane traffic. IxNetwrk ffers the industry's best test slutin fr functinal and perfrmance testing by using cmprehensive emulatin fr ruting, switching, MPLS, IP multicast, bradband, authenticatin, carrier Ethernet, and data center bridging prtcls. IxLad TM : A scalable slutin fr testing cnverged multiplay services, applicatin delivery platfrms, and security devices and systems. IxLad emulates data, vice, and vide subscribers and assciated prtcls t ensure quality f experience (QE). IxLad als applies malware and distributed denial f service (DDS) attacks fr security effectiveness and accuracy testing. Tcl API: Custm user script develpment fr layer 1-7 testing Prduct Ordering Infrmatin GE QSFP+ lad mdule HSE40GEQSFP1-01, 40GE Lad Mdule, 1-prt, 1-slt with the QSFP+ pluggable interface fr multimde fiber, 850nm, r QSFP+ cpper cables fr the XM12-02 ( ) and XM2-02 ( ) chassis with L2/3 data plane and perfrmance testing, IEEE 802.3ba PCS and unframed BERT test capability, and ruting emulatin and prtcl test supprt. i When an HSE lad mdule is installed in an XM12 chassis, the maximum perating temperature f the chassis is 35 C (ambient air). Page 6