Embedded Systems 1: Course Presentation

Transcription

1 October 2017 Embedded Systems 1: Course Presentation Davide Zoni PhD webpage: home.deib.polimi.it/zoni

2 About me Education: PostDoC (March 2014 now) PhD Student ( Jan 2011 Dec 2013 ) M.S. Degree Politecnico di Milano (2010) Visiting: ARM Cambridge (UK) 2015 UCY (Cyprus) 2015 UPV (Valencia SPAIN) 2013 and 2014 Research Topics: On chip interconnect, Cache coherence and hierarchy RTL design, simulation and verification Hardware side side channel coutermeasures 2

3 3 Contacts & Places Prof. William Fornaciari (Professor in charge) webpage: home.deib.polimi.it/fornacia Office: Building 20 first floor Davide Zoni PhD phone: webpage: home.deib.polimi.it/zoni My Office Campus bassini (eg building) First floor, room 004

4 A short list of Embedded Systems 4

5 5 Some Embedded Systems Topics Multi cores Analysis Power/performance optimization Thermal/performance optimization Application oriented design Simulation On chip interconnect Cache Hierarchy Design FPGA prototyping Run time policies Application oriented design Embedded devices Microcontroller' peripherals Wireless sensor networks (WSN)

6 6 What do you expect from this course?

7 Course Outline On chip Communication (3 hours): Bus Networks on Chip Architectural Simulation (5 hours): Event Driven Execution Model Cycle accurate simulators: GEM5 Design Space Exploration (DSE) RTL Design Verification and Simulation (12 hours): Design Organization RTL Simulation Model SystemVerilog For Synthesis (Verilog 2001 subset) Combinatorial and sequential logic, state machines SystemVerilog for Verification (Verilog 2001 subset) Writing testbenches Testbench DUT model Invited talks: GPU architecture, on going MS thesis, STMicroelectronics 7

8 Objectives of this part of the course Hands on with the most common issues in the design of high end embedded multi cores Design, Simulation and Verification aspects On chip communication Architectural Exploration (DSE) Research/Company Approach Project presentation Get involved in realistic design and evaluation problems Team working 8

9 9 Tentative schedule Introduction + On Chip Bus/Networks 3 hours Architectural Simulation with Gem5 3 hours Design Space Exploration using GEM5 2 hours SystemVerilog for Design 3 hours SystemVerilog for Verification 3 hours SystemVerilog with Vivado 3 hours SystemVerilog FSM from Past Exams 3 hours Project Presentation 2 hours ? (Before Xmas?) Written Exam 2 hours

10 The Multi Core Revolution 10

11 11 The Power Performance Gap Heterogeneous Processors Tile-GX 10 0 Tilera-64 # of cores Intel Polaris(80-core) Gap Intel Single-chip cloud computer 4 Intel IBM Cell Larrabee Performance Sun Intel Core i5, i Time Time

12 12 Goal: Better performance Design Issues and Constraints Power Thermal Reliability

13 13 Market: More Performance and Energy Efficiency Users Same experience with any device Multi tasking Demanding tasks (graphic apps) Multiple Running Applications Compete for resources Quality of Service (QoS) Different priority levels Embedded Multi Cores Limited resources Optimized power consumption

14 Market: The Smartphone/Tablet Scenario 14 The embedded GPU raw computational power increases at each generation Market asks for even higher resolution Portable device should be able to reproduce media contents smoothly, at native resolution FHD resolution: 32bit*1920*1080=8MB/frame 25 fps 200MB/s CPU0 CPUn GPU L1 0 L1 n L1 L2 On chip interconnect Main Memory CPU Prepares the vertexes and texture addresses Signal the GPU GPU Elaborate the scene and store it back to memory Signal the CPU LCD Controller Get the frame and display it at fixed rate

15 Power Trends and Issues 15 Desktop/Server: Today some of the most powerful microprocessor chips can dissipate Watts, for an average power density of Watts per sqare centimeter. Local hot spots on the die can be several times higher than this number. Low Power Methodology Manual, 2007 Smartphone/Tablet: For battery powered, hand held devices, the numbers are smaller but the problem just as serious. Battery life peaked in Since then the battery life reduced due as the features have been added faster than power has been reduced ITRS Datacenter/HPC: The total power consumption of microprocessor chips presents a significant problem for server farms, where infrastructure costs can equal the cost of the computer themselves. Low Power Methodology Manual, 2007

16 CMOS Technology Evolution 16 Thermal and Cooling Issues Michael Keating Davidd Flynn et. al., Low Power Methodology Manual, ARM&Synopsis, 2007

17 Reliability and Process Variability Issues 17 Small Transistor = more transistor per chip Thermal issues Increasing heat High leakage High power dissipation Design Issues Increasing complexity Escaped bugs Technology Issues Parametric Variations Soft/Hard Errors

18 Technology VS Design Paradox Technology scaling leads to fragile transistors Reliable system design: Providing digital design solutions that deliver the Reliable systems built on an unreliable silicon substrate Electronic devices must be reliable to be successful 18

19 Reliability: Hard Faults VS Escaped Bugs Escaped Bugs Hard Fault 19 Irreversible physical change Latent manufacturing defects Thermal issues and over voltage can induce them Design errors Increase with the device complexity Dozens in current designs Intel named their solution as a specification update Verification Formal methods No simulation required Specific design properties are evaluated RTL simulation Ad hoc test to assess the design semantic Current HDL support assert and checkers Check here Intel P4

20 RTL Simulation: Bug Inspection Static View (design time) Escaped Bugs Seems unavoidable in complex designs 500M transistors and above 5M FlipFlops 20 Verified (bug free) Verification is time consuming and constrained to the time to market Dynamic View (Run time) Verified (bug free) Possible Escaped bugs End user experience Possible Escaped bugs Design works Escaped bugs: subtle and not easily triggered They eventually go unnoticed for the entire life of the device

21 The Multi cores: Rethink the Processor Design 21 Key concepts Split the complexity (fewer bugs) Split the power consumption Simplify the design of reliable methodology to face HW faults Ease performance/power prediction Explicit Parallelism Coremulticore FUcore Design Issues: a Fresh View is Required Memory/cache hierarchy Coherence protocols Interconnect Power Cache 4 3 Large Core Small Core Performance Power = 1/4 Performance = 1/2 1 1 C1 C2 Cache C3 C

22 22 The design problem: On chip interconnect and Cache hierarchy Bandwidth, arbitration, Quality of Service (QoS), latency Low power, small footprint from low (single task/dedicated) to high end (multi core) embedded systems

23 Microcontrollers: STM32F4Discovery ARM M4 23

24 Embedded CPUs: mor1kx SoC 24 OpenSource OpenRisc1000 compliant 3 6 stage pipeline Wishbone Bus Configurable FPU Configurable Icache/Dcache Multi core available OptimSoC NoC based PolimiMCore SCA design Coherence Bus Based Both memory and interconnect strongly affect the SoC performance: +20% using a split instr/data bus +30% with caches vs w/o caches

25 HighEnd Multicore: Sun Niagara T OpenSource (Verilog) 8 in order CPUs 4 way HW multithreading Up to 32 parallel threads of execution The interconnect forces the floorplan Enhanced versions: T2 (2007), T3 (2008), T4 (2011), T5 (2013)

26 26 HighEnd ManyCore: Intel SCC 48 Pentium CPUs 2D mesh State of the art VC based routers Message passing / no HW coherence Multiple Voltage Islands 1VDD per tile (2CPUs per tile) 1NoC Vdd island The interconnect shapes the floorplan The NoC power consumption is within 20% of the SoC

27 Multi core: On chip Architectural View On chip CPU0 L1 0 CPU1 L1 1 CPUn L1 n On chip interconnect On chip interconnect Point to Point Bus/Crossbar NoC Traffic type Coherence traffic Message passing L2 0 L2 1 L2 n On chip interconnect Off chip Main Memory 27 Additional control traffic from user space if supported Heterogeneous Multi Cores GPUs, HW Accelerators How (inter)connected Coherence support NOTE: The memory controller can be on chip in current and future solutions

28 28 Available Solutions to the On chip Interconnect Design Problem

29 On chip Interconnect Architecture: Point2Point29 Scheduler component is required Requests/responses routing No master 2 master communication No data sharing on the interconnect Scalability/Performance issues CPU0 CPU1 CPUn L1 0 L1 1 L1 n Sched Sched Sched The link count grows as n*(n 1) Full throughput between each master/slave pair Reliability issues On chip Single faulty link prevents the communication Sched Sched Sched L2 0 L2 1 L2 n On chip interconnect Off chip Main Memory

30 30 On chip Interconnect Architecture: Bus Single shared communication medium Data sharing Any attached master can observe the on the bus data Contention grows with the attached masters onto the bus Reliability issues CPU0 CPU1 CPUn L1 0 L1 1 L1 n Exploited property for the snooping coherence protocol family Scalability/Performance issues Arbitration request On chip L2 0 L2 1 L2 n On chip interconnect Single point of failure Off chip Main Memory

31 31 On chip Interconnect Architecture: Xbar Single shared communication medium Arbitration request More complex and bus arbiters Data sharing Exploited property for the snooping coherence protocol family Scalability/Performance issues Any attached master can observe the on the bus data Better performance with higher power and area On chip CPU0 CPU1 CPUn L1 0 L1 1 L1 n L2 0 L2 1 L2 n On chip interconnect Reliability issues Off chip redundancy Main Memory

32 32 On chip Interconnect Architecture: NoC Distributed interconnect Reduced resource contention Still requires the Data sharing No data sharing, since no assumptions can be made on the taken path from source to destination Directory based coherence protocols Scalability/Performance issues Higher latencies than on chip bus Fully scalable On chip CPU0 CPU1 CPUn L1 0 L1 1 L1 n R R R R R R R R L2 0 L2 1 L2 n On chip interconnect Reliability issues Fully reliable (multiple paths for the same source destination pair) Off chip Main Memory

33 33 On chip Data Types Coherence Traffic Message Passing Data User Data

34 Multi core: Interconnect Traffic On chip CPU0 CPU1 CPUn L1 0 L1 1 L1 n The interconnect always routes Data/Instructions On chip interconnect L2 0 L2 1 L2 n On chip interconnect Off chip Main Memory 34 HW/SW coherence only shapes the traffic volume and intensity A load/store is elaborated in a packet suitable for the interconnect Both the coherent and message passing architectures share the same high level data protocol Request response Request forward response

35 Multi core: On Chip Bus Scalability Example CPU0 CPU1 Some parameters: CPUn L2 0 L2 1 L2 n Main Required bandwidth? Well, at the L2 the generated coherence events: Misses Dirty replacements 2 GHz CPUs, 2 IPC 33% memory operations, 2% of which miss in L2 50% of evictions are dirty Some results: Memory 35 (0.33 * 0.02) + (0.33 * 0.02 * 0.50)) = 0.01 events/insn 0.01 events/insns * 2 insn/cycle * 2 cycle/ns = 0.04 events/ns Request: 0.04 events/ns * 4B/event = 0.16 GB/s = 160 MB/s Data response: 0.04 events/ns * 64 B/event = 2.56 GB/s What about scalability? That s 2.5 GB/s... per processor With 16 processors, that 40 GB/s! With 128 processors, that s 320 GB/s!!

36 Wrapping up: Interconnect and Memory Real case scenario Adapteva board dual core arm A9 coupled with the Parallela 16 core coprocessor [Epiphany III 16 core 65nm (E16G301)] (~100 online) 36 E16G301 TECHCAL SPECS 16 High Performance RISC CPU Cores 1 GHz Operating Frequency 32 GFLOPS Peak Performance (2float op/core/cycle) ((4B*2)*2)*16=256B/cycle *10^9cycles/s =256GB/s Interconnect 512GB/s Local Memory Bandwidth 64GB/s Network On Chip Bisection Bandwidth 8 GB/s Off Chip Bandwidth 0.5 MB On Chip Distributed Shared Memory (32KB per core) No Data Coherence Additional Technical Specs 2 Watt Maximum Chip Power Consumption IEEE Floating Point Instruction Set Fully featured ANSI C/C++ programmable GNU/Eclipse based tool chain Source synchronous LVDS off chip links for host or direct chip to chip interfacing. Chip to chip links for integrating up to 64 chips on a single board 324 ball 15x15mm flip chip BGA

37 The Final Goal of this Course: Top Down View 37 System level optimization and simulation Savings System Tools: cycle accurate simulators (GEM5) System level trade off analysis and DSE: Cache hierarchy, CPU/Interconnect freq RTL Behavioral RTL Behavioral Tools: IcarusVerilog, Xsim RTL module design and verification Pre synthesis, testbench design RTL Post Synthesis RTL Post Synthesis Tools: Cadence/Xilinx Front end Optimize clock, critical path, module fan out Power, area, timing estimates Place&Route and SPICE level Physical Tools: Cadence/Xilinx Back end Optimize clock, critical path, module fan out Get final power area timing estimates