New Mul(- Time Programmable Embedded NVM IP Provides SoC Designers New Architecture Op(ons

Transcription

1 New Mul(- Time Programmable Embedded NVM IP Provides SoC Designers New Architecture Op(ons

2 Kilopass Corporate Overview Logic NVM Innovator Proven & Patented Embedded NVM in CMOS Broadly Adopted Key Markets Key Usages Kilopass founded 2001, standard CMOS possible, Gox breakdown < BVj Conceived at the right Fme, when 0.18um came to market 58 patents granted/pending, including fundamental patents on 1T, 2T, and 3.5T anf- fuse 0.18um to 40nm qualified and in producfon; 28HKMG in development Foundry agnosfc: Dongbu, GlobalFoundries, Grace, IBM, Samsung, SMIC, Tower, TSMC, UMC 100+ customers, 300+design ins, 2 billion units shipped Analog: audio tuners, clock chips, PMU, LED lighfng AutomoFve: DSP, I/O connecfvity, micro sensor systems Mobility: PA, RF transceiver, baseband, DDI, CIS Consumer: media & app processors, PC mulfmedia Small capacity (< 256Kb): ConfiguraFon, yield recovery, security keys, code patching of ROM Large capacity (> 512Kb) : Code storage 2

3 The Problem: Today s Embedded MTP Technologies Cannot Scale and Costly Shortcomings of today s MTP Technologies eflash Logic NVM MTP Itera Technology FloaFng gate FloaFng gate Oxide Breakdown Scalability No, up to 90nm Kind of, up to 130nm, stretch to 65nm Yes, 28nm and below Endurance (MTP) Up to 100K 10-10K Up to 1K AddiFonal Step , UV, Bake Wafer Adder 25% - 40% 5% 0% Bit Count 32b- 8Mb 128b 8Kb 32b - 1Mb Access Time (ns) 40-50ns 70ns 20ns 8Kb 40nm n/a n/a 0.6mm^2 Flash is flexible, but not readily available below 90nm and economically not feasible for many consumer and mobile applicafons Logic NVM MTP have small bit count and big footprint, not economical in advance nodes or not available Itera strikes balance with small foot print, enough endurance for 50% of the consumer and mobile applicafons, and process scalable 3 0

4 OTP NVM on Standard CMOS Easily Scales 4

5 Evolution of Antifuse Technology from OTP to MTP 1000 Timing Counter/ Yield/ Security/Program Code/Boot Code Endurance Code Storage Code for MPU, Storage DSP, FPGA, & SOC ($100M) Yield/Trimming/Configuration Analog/MS Chips Security ID/ Configuration SOC 180nm 90nm 40nm 20nm Bitcell Area (Normalized)

6 Itera Ideal for High Volume Consumer and Mobile Complex SOCs Applica(on Usage Endurance Total Market Size (2014) Consumer: ApplicaFon Processor, Media Processor, Image signal processor Counters, Time Stamps, Code Storage, Security Keys <100 cycles 1B units Mobile ApplicaFon Processor (GPS, Tablets, Netbooks, MID) Security Keys, Counters, Code Storage cycles 300M units WLAN SOC; MFR (mulf funcfon radio, combined several wireless standards) Prototyping, Trimming, CalibraFon, Code Storage cycles 3B units Imaging (image sensors, touch screen ctl, printer controllers) Time Stamp, Trimming, Code Storage cycles 1B units Patchable Program Storage microcode updates Counters how many Fmes a device was powered up or BIOS updated Time Stamps when was the oil last changed Trimming AdjusFng to environment, age, etc Security keys revocafon of access 6

7 How Many Erase Cycles are actually needed? Customers commonly ask for higher endurance capabilifes than needed. For example: PC 128Gbyte solid state drive with a 1 million endurance cycles and a maximum write speed of 80M bytes / sec. gives the endurance life 50 years Take 100 images (12Mbyte each) per day using a 1G flash card (100,000 write endurance) flash card in a camera gives ~ 200 years The quesfon needs to be asked What level of endurance does them applicafon really need? How many Fmes will the device is actually need to be recalibrated? Does the firmware really need to be updated 10,000 Fmes? Is the ability to change the password (or fingerprint) 100,000 a reasonable requirement? 7

8 Example 1: Counter Architecture (counts to n*m) 8

9 Example 2: Redundant Array Algorithm 9

10 Example 3: Redundant Sector Mapping Algorithm 10

11 Why Kilopass can implement a MTP solu(on be[er The same reason that you buy IP for lots of other blocks. Beser to focus your resources on your experfse and let the experts in the IP fields build the other blocks. Standard blocks are more portable. Fully qualified IP. 11

12 Where Does Itera Fit in The System? System Bus Peripheral Bridge OCP Bridge Peripheral A Peripheral B Itera 12

13 Interface Signals &'(($ *)%"% &)%"% 8"$- &-.(!"#$% *-.(',,#+" 1%$'"2 3*,4+$#( 155(-$&$(6*)7 &'(($*+%,#!"#$%$&"'()*++($,- %"./"'&(0%*+(-$&$ */#

14 XIP: Execute in Place SoC Flash SoC NVM Data rate limited by I/O pin count Data rate up to 320Mb/s with quad I/O, but typically 66Mb/s for typical SPI interface 40 cycles before first byte of data Data rate not limited by I/O Data rate up to 1600Mb/s Minimal data latency; 2 cycles Saving on power and area 14

15 Interface Timing 15

16 The Solu(on: Itera Features and Benefits Applica(on Broadens NVM storage capacity from OTP to MTP with up to 1K cycles of endurance Target SOCs include MFR, CIS, media processors, applicafon processors, baseband Usages include Fme stamp, counters, code storage, trimming, key, etc Performance Demonstrated write cycles endurance up to 1K cycles at high temp ; proven quality and reliability Enables XIP with 24X higher data rate than serial SPI EEPROM and Flash Power Low standby power and acfve power for mobile applicafons Plus, faster wake up, become acfve with embedded Cost Reduces overall BOM by replacing sflash or seeprom Up to 70% savings over serial EEPROM and Flash Standard OCP interface to simplify integrafon BIST to simplify manufacturing test Flexibility and Security of Supply Available inifally at 40nm in all major pure play foundries: TSMC, GF, and UMC Manufactured in standard logic CMOS; no extra mask steps or costs 16

17 Measurable Benefits of Itera seeprom Image Sensor ADC Image Signal Processor Forma_ng and Encoding Reduce Form Factor Save BOM cost Replace $2B sflash/ EEPROM Image Sensor ADC MTP Image Signal Processor Forma_ng and Encoding Benefits Customer Parameters Result Cost savings from EEPROM/S- Flash 1. 64Kb of external EEPROM ($0.29/chip, plus ~ $0.05 in system overhead) = $0.34/chip in BOM cost. 2. Average $3,500/wafer cost over 3 years of product life 3. 10M chips per year in producfon volume 1. Savings of $6.3M /year ($10.2M vs. $3.9M) 2. Reduces board form factor 3. 8X higher performance than discrete Flash 17

18 Conclusion Shrinking Process Feature Size Increase Embedded NVM Use Embedded MTP Offers Alterna(ve to Off- Chip EEPROM and Flash Cost and Performance Driving Increased Embedded MTP Use Itera 1K Cycle MTP Capability Offers A[rac(ve Solu(on 18