A 256kb 6T Self-Tuning SRAM with Extended 0.38V-1.2V Operating Range using Multiple Read/Write Assists and V MIN Tracking Canary Sensors

Transcription

1 A 256kb 6T Self-Tuning SRAM with Extended 0.38V-1.2V Operating Range using Multiple Read/Write Assists and V MIN Tracking Canary Sensors *Arijit Banerjee, *Ningxi Liu, *Harsh N. Patel, *Benton H. Calhoun *Electrical and Computer Engineering University of Virginia, Charlottesville ** John Poulton, **C. Thomas Gray ** Nvidia, Durham, North Carolina

2 Motivation IoE market rapidly growing IoE= Internet of Everything 2

3 Motivation IoE market rapidly growing Battery recharge and replacement problems [Source: Google image search] IoE= Internet of Everything 3

4 Motivation IoE market rapidly growing Battery recharge and replacement problems [Source: Google image search] Soln: ULP wide-range DVS IoE= Internet of Everything, ULP= Ultra-low Power, DVS=Dynamic Voltage Scaling 4

5 Bottleneck in ULP wide-v DD Range V MIN guard-banding in 6Ts 5

6 Bottleneck in ULP wide-v DD Range V MIN guard-banding in 6Ts SRAM V MIN DVS bottleneck SoC V MIN bottleneck DC-DC V DD Core SRAM 6

7 Bottleneck in ULP wide-v DD Range V MIN guard-banding in 6Ts SRAM V MIN DVS bottleneck SoC DC-DC V DD Peri DC-DC V DD Array Dual rail SRAMs SoC level tradeoffs Core SRAM 7

8 Bottleneck in ULP wide-v DD Range V MIN guard-banding in 6Ts SRAM V MIN DVS bottleneck SoC DC-DC V DD Peri DC-DC V DD Array Dual rail SRAMs SoC level tradeoffs Core SRAM Different solutions across applications 8

9 SRAM V MIN Issues SRAM Solutions for ULP Applications Trading off performance and area Performance [Source : Cliff Hou, TSMC, ISSCC 2017] 9

10 Scope of 6T SRAM Improvements Peripheral assist for V MIN improvement Normalized SRAM write energy per cycle at V MIN % 30.7% 36% 51.5% TT SS SF FS FF 28nm TT_80C at V MIN (without assist) [Source: A. Banerjee. et al. ISQED 2014] 10

11 Scope of 6T SRAM Improvements Peripheral assist for V MIN improvement Lower V MIN guard-band Normalized SRAM write energy per cycle at V MIN Tracking V MIN could save energy 36% 30.7% 42.2% 51.5% TT SS SF FS FF 28nm TT_80C at V MIN (without assist) [Source: A. Banerjee. et al. ISQED 2014] 11

12 Scope of 6T SRAM Improvements Peripheral assist for V MIN improvement Lower V MIN guard-band Proposed Solution Combined assist 1 and Canary based V MIN tracking 2 reducing guardbanding Normalized SRAM write energy per cycle at V MIN Tracking V MIN could save energy 36% 30.7% 42.2% 51.5% TT SS SF FS FF 28nm TT_80C at V MIN (without assist) [ 1 E. Karl et al., 2012; 2 A. Banerjee et al. 2015] [Source: A. Banerjee. et al. ISQED 2014] 12

13 Agenda Canary SRAM Sensors Peripheral Assists and Reverse Assists 256kb Self-tuning SRAM Architecture Experiments & Results Comparison Conclusion 13

14 Canary SRAM Sensors [Source: Canary SRAM a sensor or detector 14

15 Canary SRAM Sensors [Source: Canary SRAM a sensor or detector Fails earlier than the population of SRAM bits 15

16 Canary SRAM Sensors [Source: Canary SRAM a sensor or detector Fails earlier than the population of SRAM bits Prior work was in SRAM DRV* tracking 1 1 [J. Wang, and B. H. Calhoun, CICC, 2007], *DRV=Data retention voltage; 16

17 Agenda Canary SRAM Sensors Peripheral Assists and Reverse Assists 256kb Self-tuning SRAM Architecture Experiments & Results Comparison Conclusion 17

18 Peripheral Assists and Reverse Assist What is a peripheral assist (PA) in SRAM context? An auxiliary circuit that improve read/write-ability 18

19 Peripheral Assists and Reverse Assist What is a peripheral assist (PA) in SRAM context? An auxiliary circuit that improve read/write-ability What is reverse assist? An auxiliary circuit that degrades read/write-ability SRAM bitcell + Reverse Assist = SRAM bitcell 19

20 Occurrences Example: SRAM write V MIN Distribution with Reverse Assist Settings (RAS) SRAM Write V MIN Distribution Canary write V MIN distribution shifts right with increasing RAS A B C Write V MIN [Source: A. Banerjee. et al. ISQED 2014] 20

21 Input and Output Design Metrics Input Metrics N Number of SRAM bits on a chip Y SRAM Core SRAM target yield C Number of canary SRAM bits F th Canary failure threshold condition V RA (RAS 1 ) Canary BL type reverse assist voltage Output Metrics P fc Canary SRAM chip failure probability [Source: A. Banerjee. et al. ISQED 2014] 1 RAS=Reverse assist settings; F th = Failure threshold condition 21

22 Agenda Canary SRAM Sensors Peripheral Assists and Reverse Assists 256kb Self-tuning SRAM Architecture Experiments & Results Comparison Conclusion 22

23 TRACK 256kb Self-tuning SRAM Architecture Off-Chip CLK_IN LDO V DD On-Chip LDO_CTRL Frequency to digital converter (FDC) V DDOUT 256kb 6T SRAM with canaries Assist Controller (ASC) Canary BIST (CBIST) Enable signals for WLB 1, NBL 2, VDDB 3 DIN, ADDR DOUT 1 WLB=Wordline Boost, 2 NBL=Negative Bitline, 3 VDDB=Vdd Boost. 23

24 V MIN Self-tuning Operation 24

25 Agenda Canary SRAM Sensors Peripheral Assists and Reverse Assists 256kb Self-tuning SRAM Architecture Experiments & Results Comparison Conclusion 25

26 Experiments and Results SRAM + PAs = Max 240mV V MIN improvements Does not eliminate V MIN guard-bands PA=Peripheral assists 26

27 V MIN Lowering using Combined Read/Write Assists 90 percentile worst case V MIN Measured CDF showing V MIN improvement w/ combined assist 27

28 Experiments and Results SRAM + PAs + Canaries = Arbitrary guardband lowering can save 1444X active power SRAM + PAs + Canaries = 12.4X leakage savings PA=Peripheral assists 28

29 Active Power Reduction using Combined Assist and Guard-band Lowering Canary Tracking Actual chip V MIN 90 percentile worst case V MIN Combined Assists Measured active power improvements 29

30 Active Power Reduction using Combined Assist and Guard-band Lowering Canary Tracking Actual chip V MIN 90 percentile worst case V MIN Combined Assists Canary Tracking Measured active power improvements 30

31 Active Power Reduction using Combined Assist and Guard-band Lowering Canary Tracking Actual chip V MIN 90 percentile worst case V MIN Combined Assists Canary Tracking Measured active power improvements 31

32 Leakage Power Reduction using Combined Assist and Canary Tracking Actual chip V MIN 1.2V Measured leakage power improvements 32

33 Canary V MIN 130nm Bulk Fth=1500, RAS=011 Measured canary V MIN tracking across frequencies 33

34 Canary V MIN 130nm Bulk Fth=1500, RAS=011 Measured canary V MIN tracking across frequencies 34

35 Canary V MIN 130nm Bulk Fth=1500, RAS=011 Measured canary V MIN tracking across frequencies 35

36 Scalability of Canary 32nm FDSOI Simulation results of canary based V MIN Tracking at TT corner 36

37 Overhead Canary area overhead only 0.77% (array) Combined assist area overhead 2.8% in SRAM Total system components without BISTs 1.8% Onetime canary tuning (matching the worst case SRAM bitcell) overhead Running ~ 90/282 cycles/v DD granularity per frequency/temp change for full 512b/2kb canaries 37

38 Agenda Canary SRAM Sensors Peripheral Assists and Reverse Assists 256kb Self-tuning SRAM Architecture Experiments & Results Comparison Conclusion 38

39 Comparison VLSI 15 This work ISSCC 15 VLSI 14 ISSCC 12 Memory Features DVS/VMIN Features Technology 14nm 130nm 28nm 180nm 22nm Cell type 8T 6T 6T 8T 6T Capacity 288kb 256kb 256kb 16KB 576KB DVS range 1-0.3V (700mV) V (850mV) V (320mV) V (1200mV) V (375mV) V MIN Tracking N Y N N N V MIN 0.3V 0.38V 0.58V 0.6V 0.7V Supply / Power Sub-VT Operation N Y N N N Max power Reduction X X - 39

40 Conclusion A wide DVS range (1.2V-0.38V) with lower SRAM V MIN (0.38V) achieved using multiple assists (write/read) across supplies Canary sensors track SRAM V MIN for margin guard-band minimization Demonstrated a reliable and an adaptive SRAM system selecting optimal V DD and assist techniques for ULP IoE enablement 40

41 Acknowledgements Advisor: Professor Ben Calhoun UVa Colleagues: Harsh Patel, Ningxi Liu, Farah Yahya, Divya A. K., Kevin Leach, Dilip Vasudevan, Terry Tigner Nvidia Colleagues: Tom Gray and John Poulton These projects was supported in part by NVIDIA through the DARPA PERFECT program 41

42 Thank You 42