R8810LV. RDC RISC DSP Controller R8810LV. RDC RISC DSP Controller. 16-Bit RISC Microcontroller User s Manual

Transcription

1 RDC RISC DSP Controller R1LV R1LV 1-Bit RISC Microcontroller User s Manual RDC RISC DSP Controller, Ltd Tel Fax

2 RDC RISC DSP Controller R1LV Contents page - Features Block Diagram Pin Configuration PQFP and LQFP Pin-Out Table Pin Description Basic Application System Block Oscillator Characteristics Read/Write timing Diagram Execution Unit = General Register = Segment Register = Instruction Pointer and Status Flags Register = Address Generation Peripheral Control Block Register System Clock Block Reset Bus Interface Unit = Memory and I/O Interface = Data Bus = Wait States = Bus Hold Chip Select Unit = UCS = LCS = MCSx = PCSx Interrupt Controller Unit = Master Mode and Slave Mode = Interrupt Vector, Type and Priority = Interrupt Request = Interrupt Acknowledge = Programming Register

3 RDC RISC DSP Controller R1LV - DMA Unit = DMA Operation = External Request Timer Control Unit = Watchdog Timer = Timer/Counter Unit Output Mode Asynchronous Serial Port Synchronous Serial Port = Synchronous Serial Port Operation PIO Unit = PIO Multi-Function Pin list Table PSRAM Control Unit Instruction Set Opcodes and Clock Cycle = R1LV Execution Timings DC Characteristics AC Characteristics Package Information Revision History

4 RDC RISC DSP Controller R1LV 1-Bit Microcontroller with -bit external data bus Features Five-stages pipeline RISC architecture Static Design & Synthesizable design Bus interface - Multiplexed address and Data bus which compatible with C1 microprocessor - Supports nonmultiplexed address bus [A19 : A] - 1M byte memory address space - K byte I/O space Software compatible with the C1 Support one Asynchronous serial channel & one Synchronous serial channel Supports 32 PIO pins PSRAM (Pseudo static RAM) interface with auto-refresh control Three independent 1-bit timers and Timer 1 can be programed as a watchdog timer The Interrupt controller with five maskable external interrupts and one nonmaskable external interrupt Two independent DMA channels Programble chip-select logic for Memory or I/O bus cycle decoder Programmable wait-state generator Block Diagram INT2/INTA INT1/SELECT CLKOUTA INT3/INTA1/IRQ TMROUT TMROUT1 CLKOUTB INT INT NMI TMRIN TMRIN1 DRQ DRQ1 VCC GND X1 X2 Clock and Power Management Interrupt Control Unit Timer Control Unit DMA Unit RST LCS/ONCE MCS3/RFSH MCS2-MCS Chip Select Unit Instruction Queue (bits) UCS/ONCE1 PCS3-PCS PCS/A1 PCS/A2 PSRAM Control Unit Instruction Decoder Control Signal Micro ROM PIO Unit ARDY SRDY S2~S DT/R DEN Refresh Control Unit Register File General, Segment, Eflag Register EA / LA Address Asynchronous Serial Port TXD RXD HOLD HLDA S/CLKDIV2 UZI Bus Interface Unit ALU (Special, Logic, Adder, BSF) Execution Unit Synchronous Serial Interface RD A19~A AD~AD AO1~AO ALE WB WR RFSH/ADEN SCLK SDENSDEN1 SDATA

5 RDC RISC DSP Controller R1LV Rev:1.1 Pin Configuration (PQFP) R1LV Microcontroller SDEN1/PIO23 SDEN/PIO22 SCLK/PIO2 ALE ARDY GND X1 X2 VCC CLKOUTA CLKOUTB GND A19/PIO9 A1/PIO VCC A1/PIO A1 A1 A1 A13 A12 A11 A1 A9 A A A A A A3 A2 A1 VCC A GND GND HLDA HOLD SRDY/PIO NMI INT/PIO3 INT VCC CND VCC GND TMRIN1/PIO TMROUT1/PIO1 TMROUT/PIO1 TMRIN/PIO11 DRQ1/PIO13 DRQ/PIO12 AD AO AD1 AO9 AD2 AO1 AD3 AO11 AD AO12 AD GND AO13 AD VCC AO1 AD AO1 TXD/PIO2 RXD/PIO2 SDATA/PIO21 INT3/INTA1/IRQ UCS/ONCE1 LCS/ONCE PCS2/PIO1 S/CLKDIV2/PIO29 DT/R/PIO DEN/PIO MCS/PIO1 MCS1/PIO1 INT2/INTA/PIO31 PCS/A2/PIO2 PCS/A1/PIO3 PCS3/PIO19 PCS1/PIO1 PCS/PIO1 MCS2/PIO2 MCS3/RFSH/PIO2 RST UZI/PIO2 RFSH2/ADEN WB WR RD S2 S1 S INT1/SELECT

6 RDC RISC DSP Controller R1LV Rev:1.1 (LQFP) R1LV AD AO AD1 AO9 AD2 AO1 AD3 AO11 AD AO12 AD GND AO13 AD VCC AO1 AD AO1 S/CLKDIV2/PIO29 UZI/PIO2 TXD/PIO2 RXD/PIO2 SDATA/PIO21 SDEN1/PIO23 SDEN/PIO22 SCLK/PIO2 BHE/ADEN WR RD ALE ARDY S2 S1 S GND X1 X2 VCC CLKOUTA CLKOUTB GND A19/PIO9 A1/PIO VCC A1/PIO A1 A1 A1 A13 A12 A11 A9 A1 A A A A A A3 A2 VCC A A1 GND HOLD HLDA SRDY/PIO NMI INT/PIO3 INT VCC GND VCC GND TMRIN1/PIO TMROUT/PIO1 TMRIN/PIO11 TMROUT1/PIO1 DRQ1/PIO13 DRQ/PIO12 GND DT/R/PIO INT3/INTA1/IRQ INT2/INTA/PIO31 INT1/SELECT UCS/ONCE1 LCS/ONCE PCS/A2/PIO2 PCS/A1/PIO3 PCS3/PIO19 PCS2/PIO1 PCS1/PIO1 PCS/PIO1 RST DEN/PIO MCS3/RFSH/PIO2 WB MCS/PIO1 MCS1/PIO1 MCS2/PIO2

7 RDC RISC DSP Controller R1LV R1LV Pin Number Comparison Table Pin name LQFP Pin No. PQFP Pin No. Pin name LQFP Pin No. PQFP Pin No. AD 1 A AO 2 9 A AD1 3 A9 3 3 AO9 1 A 31 AD2 2 A 32 AO1 3 A 33 AD3 A 3 AO11 A 3 AD 9 A3 9 3 AO12 1 A2 3 AD 11 VCC 1 3 GND 12 9 A AO A 3 AD 1 91 GND 1 VCC 1 92 GND 2 AO WB 3 AD 1 9 HLDA AO1 1 9 HOLD S/ UZI /PI O SRDY/PI O 9 UZI /PI O2 2 9 NMI TXD/PI O DT/R /PI O RXD/PI O DEN /PI O 2 9 SDATA/PI O MCS /PI O1 3 SDEN1/PI O MCS 1/PI O1 1 SDEN/PI O I NT/ PI O3 2 SCLK/PI O2 2 3 I NT3/ INTA 1/I RQ 3 RFSH 2 / ADEN 2 I NT2/ INTA /PI O31 WR 2 I NT1/SELECT RD 29 I NT 9 ALE 3 UCS/ CNCE1 ARDY 31 LCS/ CNCE 1 S S PCS /A2/PI O2 2 9 PCS /A1/PI O3 3 S 3 11 VCC 31 GND 3 12 PCS 3/PI O19 2 X PCS 2 /PI O1 3 X2 3 1 GND VCC 3 1 PCS 1/PI O1 CLKOUTA 39 1 PCS /PI O1 9 CLKOUTB 1 VCC 9 GND 1 1 MCS 2 /PI O2 91 A19/PI O MCS 3/ RFSH/PI O A1/PI O 3 2 GND 93 VCC 21 RST 9 1 A1/PI O 22 TMRI N1/PI O 9 2 A1 23 TMROUT1/PI O1 9 3 A1 2 TMROUT/PI O1 9 A1 2 TMRI N/PI O11 9 A DRQ1/PI O13 99 A12 2 DRQ/PI O12 1 Rev:1.1

8 RDC RISC DSP Controller R1LV Pin Description Pin No.(PQFP) Symbol Type Description 1, 21, 3, 1,, 92 VCC Input System power: +3.3 volt power supply. 12, 1, 1, 2,,, 9 GND Input System ground. 1 RST Input* Reset input. When RST is asserted, the CPU immediately terminate all operation, clears the internal registers & logic, and the address transfers to the reset address FFFFh. 13 X1 Input Input to the oscillator amplifier. 1 X2 Output Output from the inverting oscillator amplifier. 1 CLKOUTA Output Clock output A. The CLKOUTA operation is the same as crystal input frequency (X1). CLKOUTA remains active during reset and bus hold conditions. 1 CLKOUTB Output Clock output B. The CLKOUTB operation is the same as crystal input frequency (X1). CLKOUTB remains active during reset and bus hold conditions. 1 2 SDEN1/PIO23 SDEN/PIO22 Synchronous Serial Port Interface Serial data enables. Active-high. These pins enable data transfers of the synchronous serial interface. SDEN1 for port1, Output/Input SDEN for port. Synchronous serial data clock. This pin provides the shift clock 3 SCLK/PIO2 Output/Input to an external device. SCLK=X1/2,, or 1 depending on register setting. This pin held high during the UART inactive. 1 SDATA/PIO21 Input/Output 9 TXD/PIO2 Output/Input Synchronous serial data. This pin provides the shift data to or receives a serial data from an external device. Asynchronous Serial Port Interface Transmit data. This pin transmits asynchronous serial data from the UART of the microcontroller. 99 RXD Input Receive data. This pin receives asynchronous serial data. Bus Interface For RFSH 2 feature, this pin actice low to indicate a DRAM refresh bus cycle. For ADEN feature, when this pin is held high on power-on reset the address portion of the AD bus can be disabled or enabled by DA bit in the LMCS and UMCS register during RFSH 2 / ADEN Output/Input LCS or UCS bus cycle access. The RFSH 2 / ADEN with a internal weak pull-up resister, so no external pull-up resister is reqired. The AD bus always drives both address and data during LCS or UCS bus cycle access, if the WR Output RD Output ALE Output RFSH 2 / ADEN pin with external pull-low resister during reset. Write strobe. This pin indicates that the data on the bus is to be written into a memory or an I/O device. WR is active during T2, T3 and Tw of any write cycle, floats during a bus hold or reset. Read Strobe. Active low signal which indicates that the microcontroller is performing a memory or I/O read cycle. RD floats during bus hold or reset. Address latch enable. Active high. This pin indicates that an address output on the AD bus. Address is guaranteed to be valid on the trailing edge of ALE. This pin is tri-stated during Rev:1.1

9 RDC RISC DSP Controller R1LV ARDY Input ,,,2,,, 91,9 9,1,3,,,9 93,9 S2 S1 S A19/PIO9 A1/PIO A1/PIO A1-A2 A1, A AD-AD AO-AO1 Output Output/Input 3 WB Output HLDA Output ONCE mode and is never floating during a bus hold or reset. Asynchronous ready. This pin performs the microcontroller that the address memory space or I/O device will complete a data transfer. The ARDY pin accepts a rising edge that is asynchronous to CLKOUTA and is active high. The falling edge of ARDY must be synchronized to CLKOUTA. Tie ARDY high, the microcontroller is always asserted in the ready condition. If the ARDY is not used, tie this pin low to yield control to SRDY. Both SRDY and ARDY should be tied to high if the system need not assert wait state by externality. Bus cycle status. These pins are encoded to indicate the bus status. S 2 can be used as memory or I/O indicator. S 1 can be used as DT/ R indicator. These pins are floating during hold and reset. Bus Cycle Encoding Description S2 S1 S Bus Cycle Interrupt acknowledge Read data from I/O Write data to I/O Halt Instruction fetch Read data from memory Write data to memory Passive Address bus. Non-multiplex memory or I/O address. The A bus is one-half of a CLKOUTA period earlier than the AD bus. These pins are high-impedance during bus hold or reset. The multiplexed address and data bus for memory or I/O accessing. The address is present during the t1 clock phase, and the data bus phase is in t2-t cycle. The address phase of the AD bus can be disabled when the Input/Output BHE / ADEN pin with external pull-low resister during reset. The AD bus is in high-impedance state during bus hold or reset condition and this bus also be used to load system configuration information (with pull-up or pull-low resister) into the RESCON(Fh) register when the reset input from low go high. Address Only Bus, In the multiplexed address bus, the AO1 Output AO combine with the AD AD to form a 1 bit address bus. These pins are floating during a bus hold or reset. Write Byte. This pin active low to indicate a write cycle on the bus. It is floating during reset. Bus hold acknowledge. Active high. The microcontroller will issue a HLDA in response to a HOLD request by external bus master at the end of T or Ti. When the microcontroller is in hold status (HLDA is high), the AD1-D, A19-A, WR, RD, DEN, S - S 1, S, BHE, DT/ R, WHB and WLB are floating, and the UCS, LCS, PCS - PCS, MCS3 - MCS and PCS 3 - PCS will be drive high. After HOLD is detected as being low, the microcontroller will lower HLDA. 9 Rev:1.1

10 RDC RISC DSP Controller R1LV HOLD Input SRDY/PIO Input/Output DT/ R /PIO Output/Input Bus hold request. Active high. This pin indicates that another bus master is requesting the local bus. Synchronous ready. This pin performs the microcontroller that the address memory space or I/O device will complete a data transfer. The SRDY pin accepts a falling edge that is asynchronous to CLKOUTA and is active high. SRDY is accomplished by elimination of the one-half clock period required to internally synchronize ARDY. Tie SRDY high the microcontroller is always assert in the ready condition. If the SRDY is not used, tie this pin low to yield control to ARDY. Both SRDY and ARDY should be tied to high if the system need not assert wait state by externality. Data transmit or receive. This pin indicates the direction of data flow through an external data-bus transceiver. DT/ R low, the microcontroller receives data. When DT/R is asserted high, the microcontroller writes data to the data bus. Data enable. This pin is provided as a data bus transceiver 9 DEN /PIO output enable. DEN is asserted during memory and I/O access. Output/Input DEN is drived high when DT/ R changes state. It is floating during bus hold or reset condition. Bus cycle status bit/clock divided by 2. For S feature, this pin is low to indicate a microcontroller-initiated bus cycle or high to indicate a DMA-initiated bus cycle during T2, T3, Tw 9 S/ CLKDIV 2 /PIO29 Output/Input 9 UZI /PIO2 Output/Input 1 9 MCS /PIO1 MCS 1/PIO1 MCS 2 /PIO2 MCS 3 / RFSH /PIO2 UCS / ONCE 1 LCS / ONCE and T. For CLKDIV 2 feature. The internal clock of microcontroller is the external clock be divided by 2. (CLKOUTA, CLKOUTB=X1/2), if this pin held low during power-on reset. The pin is sampled on the rising edge of RST. Upper zero indicate. This pin is the logical OR of the inverted A19-A1. It asserts in the T1 and is held throughout the cycle. Chip Select Unit Interface Output/Input Output/Input Output/Input Midrange memory chip selects. For MCS feature, these pins are active low when enable the MMCS(Ah) register to access a memory. The address ranges are programmable. MCS3 - MCS are held high during bus hold. When programming LMCS(A2h) register, pin9 is as arfsh pin to auto refresh the PSRAM. Upper memory chip select/once mode request 1. For UCS feature, this pin acts low when system accesses the defined portion memory block of the upper 12K bytes (h- FFFFFh) memory region. UCS default acted address region is from Fh to FFFFFh after power-on reset. The address range acting UCS is programmed by software. For ONCE 1 feature. If ONCE and ONCE 1 are sampled low on the rising edge of RST. The microcontroller enters ONCE mode. In ONCE mode, all pins are high-impedance. This pin incorporates weakly pull-up resistor. Lower memory chip select/once mode request. For LCS feature, this pin acts low when the microcontroller accesses the defined portion memory block of the lower 12K (h- FFFFh) memory region. The address range acting LCS is 1 Rev:1.1

11 RDC RISC DSP Controller R1LV PCS /A2/PIO2 PCS /A1/PIO3 PCS 3 /PIO19 PCS 2 /PIO1 PCS 1/PIO1 PCS /PIO1 programmed by software. For ONCE feature, see UCS / ONCE 1 description. This pin incorporates weakly pull-up register. Peripheral chip selects/latched address bit. For PCS feature, these pins act low when the microcontroller accesses the fifth or sixth region of the peripheral memory (I/O or memory space). The base address of PCS is programmable. These pins Output/Input assert with the AD address bus and are not float during bus hold. For latched address bit feature. These pins output the latched address A2, A1 when cleared the EX bit in the MCS and PCS auxiliary register. The A2, A1 retains previous latched data during bus hold. Peripheral chip selects. These pins act low when the microcontroller accesses the defined memory area of the peripheral memory block (I/O or memory address). For I/O accessed, the base address can be programmed in the region Output/Input h to FFFFh. For memory address access, the base address can be located in the 1M byte memory address region. These pins assert with the multiplexed AD address bus and are not float during bus hold. Interrupt Control Unit Interface NMI Input Nonmaskable Interrupt. The NMI is the highest priority hardware interrupt and is nonmaskable. When this pin is asserted (NMI transition from low to high), the microcontroller always transfers the address bus to the location specified by the nonmaskable interrupt vector in the microcontroller interrupt vector table. The NMI pin must be asserted for at least one CLKOUTA period to guarantee that the interrupt is recognized. Maskable interrupt request. Act high. This pin indicates that an interrupt request has occurred. The microcontroller will jump to the INT address vector to execute the service routine 2 INT/PIO3 Input/Output if the INT is enable. The interrupt input can be configured to be either edge- or level-triggered. The requesting device must holt the INT until the request is acknowledged to guarantee interrupt recognition. Maskable interrupt request 3/interrupt acknowledge 1/slave interrupt request. For INT3 feature, except the difference interrupt line and interrupt address vector, the function of INT3 is the same as INT. 3 INT3/ INTA 1 /IRQ Input/Output For INTA1feature, in cascade mode or special fully-nested mode, this pin corresponds the INT1. For IRQ feature, when the microcontroller is as a slave device, this pin issues an interrupt request to the master interrupt INT2/ INTA /PIO31 Input/Output INT1/ SELECT Input/Output controller. Maskable interrupt request 2/interrupt acknowledge. For INT2 feature, except the difference interrupt line and interrupt address vector, the function of INT2 is the same as INT. For INTA feature, in cascade mode or special fully-nested mode, this pin corresponds the INT. Maskable interrupt request 1/slave select. For INT1 feature, except the difference interrupt line and interrupt address vector, the function of INT1 is the same as INT. 11 Rev:1.1

12 RDC RISC DSP Controller R1LV Notes: INT Input 2 3 TMRIN1/PIO TMRIN/PIO11 TMROUT1/PIO1 TMROUT/PIO1 DRQ1/PIO13 DRQ/PIO12 For SELECT feature, when the microcontroller is as a slave device, this pin is drived from the master interrupt controller decoding. This pin acts to indicate that an interrupt appears on the address and data bus. The INT must act before SELECT acts when the interrupt type appears on the bus. Maskable interrupt request. Except the interrupt line and interrupt address vector, the function of INT is the same as INT. Timer Control Unit Interface Timer input. These pins can be as clock or control signal input, which depend upon the programmed timer mode. After Input/Output internally synchronizing low to high transitions on TMRIN, the timer controller increments. These pins must be pull-up if not being used. Timer output. Depending on timer mode select these pins Output/Input provide single pulse or continuous waveform. The duty cycle of the waveform can be programmable. These pins are floated during a bus hold or reset. DMA Unit Interface Input/Output DMA request. These pins are asserted high by an external device when the device is ready for DMA channel 1 or channel to perform a transfer. These pins are level-triggered and internally synchronized. The DRQ signals must remain act until finish serviced and are not latched. 1.When enable the PIO Data register, there are 32 MUX definition pins can be as a PIO pin. For example, the DRD1/PIO13 (pin) can be as a PIO13 when enable the PIO Data register. 2.The PIO status during Power-On reset : PIO1, PIO1, PIO22, PIO23 are input with pull-down, PIO to PIO9 are normal operation and the others are input with pull-up. 12 Rev:1.1

13 RDC RISC DSP Controller R1LV Basic Application System Block Flash ROM X1 AD-AD A19-A Data() Address X2 WR RD WE OE UCS CE SRAM RS232 Level Converter Serial port R1LV Data() Address WE Timer-1 LCS OE CE INTx VCC 1K DMA PIO PCSx Peripheral Data Address CS 1uF RST WE OE BASIC APPLICATION SYSTEM BLOCK (A) Flash ROM DEN G D-D Data() X1 DT/R DIR Address X2 AD-AD UCS Transciver WE OE CE SRAM RS232 Level Converter Serial port Timer-1 R1LV AD-AD AO1-AO A19-A1 ALE LCS A19-A Latch Data() Address WE OE CE INTx VCC DMA PIO Peripheral Data Address 1K PCSx CS RST WR WE 1uF RD OE BASIC APPLICATION SYSTEM BLOCK (B) 13 Rev:1.1

14 RDC RISC DSP Controller R1LV Oscillator Characteristics C1 C2 Rf X1 X2 R1LV L C3 2PF For fundamental -mode crystal: C pF ± 2% ; C pF ± 2% ; Rf mega-ohm ; C3, L --- Don t care For third-overtone mode crystal: C pF ± 2% ; C pF ± 2% ; C pf ; Rf mega-ohm L uH ± 2% (MHz),.uH ± 2% (33MHz).2uH ± 2% (2MHz), 12uH ± 2% (2MHZ) 1 Rev:1.1

15 RDC RISC DSP Controller R1LV Read/Write timing Diagram T1 T2 T3 T CLKOUTA TW A19:A ADDRESS S AD:AD ADDRESS DATA AO1:AO ADDRESS ALE RD UCS,LCS PCSx,MCSX DEN DT/R S2:S UZI READ CYCLE 1 Rev:1.1

16 RDC RISC DSP Controller R1LV T1 T2 T3 T CLKOUTA TW A19:A ADDRESS S AD:AD ADDRESS DATA AO1:AO ADDRESS ALE WR WB UCS,LCS PCSx,MCSX DEN DT/R S2:S UZI WRITE CYCLE 1 Rev:1.1

17 RDC RISC DSP Controller R1LV Execution Unit General Register The R1 has eight 1-bit general registers. And the AX,BX,CX,DX can be subdivided into two -bit register (AH,AL,BH, BL,CH,CL,DH,DL). The functions of these registers are described as follows. AX : Word Divide, Word Multiply, Word I/O operation. AH : Byte Divide, Byte Multiply, Byte I/O, Decimal Arithmetic, Translate operation. AL : Byte Divide, Byte Multiply operation. BX : Translate operation. CX : Loops, String operation CL : Variable Shift and Rotate operation. DX : Word Divide, Word Multiply, Indirect I/O operation SP : Stack operations (POP, POPA, POPF, PUSH, PUSHA, PUSHF) BP : General-purpose register which can be used to determine offset address of operands in Memory. SI : String operations DI : String operations High Low 1 AX AH AL Accumulator Data Group BX CX BH CH BL CL Base Register Count/Loop/Repeat/Shift DX DH DL Data Index Group and Pointer SP BP SI DI Stack Pointer Base Pointer Source Index Destination Index GENERAL REGISTERS Segment Register R1 has four 1-bit segment registers, CS, DS, SS, ES. The segment registers contain the base addresses (starting location) of these memory segments, and they are immediately addressable for code (CS), data (DS & ES), and stack (SS) memory. CS (Code Segment) : The CS register points to the current code segment, which contains instruction to be fetched. The default location memory space for all instruction is K. The initial value of CS register is FFFFh. 1 Rev:1.1

18 RDC RISC DSP Controller R1LV DS (Data Segment) : The DS register points to the current data segment, which generally contains program variables. The DS register initialize to H. SS (Stack Segment ) : The SS register points to the current stack segment, which is for all stack operations, such as pushes and pops. The stack segment is used for temporary space. The SS register initialize to H. ES (Extra Segment) : The ES register points to the current extra segment which is typically for data storage, such as large string operations and large data structures. The DS register initialize to H. 1 CS Code Segment DS Data Segment SS Stack Segment ES Extra Segment SEGMENT REGISTERS Instruction Pointer and Status Flags Register IP (Instruction Pointer) : The IP is a 1-bit register and it contains the offset of the next instruction to be fetched. Software can not to direct access the IP register and this register is updated by the Bus Interface Unit. It can change, be saved or be restored as a result of program execution. The IP register initialize to H and the CS:IP starting execution address is at FFFFH. Processor Status Flags Registers FLAGS Reset Value : h Reserved OF DF IF TF SF ZF Res AF Res PF Res CF These flags reflect the status after the Execution Unit is executed. Bit 1-12 : Reserved Bit 11: OF, Overflow Flag. An arithmetic overflow has occurred, this flag will be set. Bit 1 : DF, Direction Flag. If this flag is set, the string instructions are increment address process. If DF is cleared, the string instructions are decrement address process. Refer the STD and CLD instructions for how to set and clear the DF flag. Bit 9 : IF, Interrupt-Enable Flag. Refer the STI and CLI instructions for how to set and clear the IF flag. Set to 1 : The CPU enables the maskable interrupt request. 1 Rev:1.1

19 RDC RISC DSP Controller R1LV Set to : The CPU disables the maskable interrupt request. Bit : TF, Trace Flag. Set to enable single-step mode for debugging; Clear to disable the single-step mode. If an application program sets the TF flag using POPF or IRET instruction, a debug exception is generated after the instruction (The CPU automatically generates an interrupt after each instruction) that follows the POPF or IRET instruction. Bit : SF, Sign Flag. If this flag is set, the high-order bit of the result of an operation is 1,indicating it is negative. Bit : ZF, Zero Flag. The result of operation is zero, this flag is set. Bit : Reserved Bit : AF, Auxiliary Flag. If this flag is set, there has been a carry from the low nibble to the high or a borrow from the high nibble to the low nibble of the AL general-purpose register. Used in BCD operation. Bit 3: Reserved. Bit 2: PF, Parity Flag. The result of low-order bits operation has even parity, this flag is set. Bit 1: Reserved Bit : CF, Carry Flag. If CF is set, there has been a carry out or a borrow into the high-order bit of the instruction result. Address generation The Execution Unit generates a 2-bit physical address to Bus Interface Unit by the Address Generation. Memory is organized in sets of segments. Each segment contains a 1 bits value. Memory is addressed using a two-component address that consists of a 1-bit segment and 1-bit offset. The Physical Address Generation figure describes how the logical address transfers to the physical address. Shift left bits 1 2 F 9 1 Segment Base Logical Address 1 2 F Offset F A 2 19 Physical Address TO Memory Physical Address Generation 19 Rev:1.1

20 RDC R1LV RISC DSP Controller Peripheral Control Block Register The peripheral control block can be mapped into either memory or I/O space which is to program the FEh register. And it starts at FFh in I/O space when reset the microprocessor. The following table is the definition of all the peripheral Control Block Register, and the detail description will arrange on the relation Block Unit. Offset Offset Register Name Page (HEX) (HEX) Register Name Page FE Peripheral Control Block Relocation Register 21 Timer 2 Mode / Control Register F Reset Configuration Register 2 2 Timer 2 Maxcount Compare A Register 1 F Processor Release Level Register 21 Timer 2 Count Register 1 F PDCON Register 22 E Timer 1 Mode / Control Register E Enable RCU Register C Timer 1 Maxcount Compare B Register E2 Clock Prescaler Register A Timer 1 Maxcount Compare A Register E Memory Partition Register Timer 1 Count Register DA DMA 1 Control Register 2 Timer Mode / Control Register D DMA 1 Transfer Count Register Timer Maxcount Compare B Register D DMA 1 Destination Address High Register 2 Timer Maxcount Compare A Register D DMA 1 Destination Address Low Register Timer Count Register D2 DMA 1 Source Address High Register Serial Port Interrupt Control Register 3 D DMA 1 Source Address Low Register 2 Watchdog Timer Control Register 1 CA DMA Control Register 1 INT Control Register 3 C DMA Transfer Count Register 1 3E INT3 Control Register 39 C DMA Destination Address High Register 1 3C INT2 Control Register 39 C DMA Destination Address Low Register 2 3A INT1 Control Register C2 DMA Source Address High Register 2 3 INT Control Register C DMA Source Address Low Register 2 3 DMA 1 Interrupt Control Register 1 A PCS and MCS Auxiliary Register 32 3 DMA Interrupt Control Register 2 A Midrange Memory Chip Select Register Timer Interrupt Control Register 2 A Peripheral Chip Select Register 33 3 Interrupt Status Register 3 A2 Low Memory Chip Select Register 3 2E Interrupt Request Register A Upper Memory Chip Select Register 29 2C In-service Register Serial Port Baud Rate Divisor Register 2A Priority Mask Register Serial Port Receive Register 2 Interrupt Mask Register Serial Port Transmit Register 2 Poll Status Register 2 Serial Port Status Register 2 Poll Register Serial Port Control Register 3 22 End-of-Interrupt A PIO Data 1 Register 2 2 Interrupt Vector Register 9 PIO Direction 1 Register 2 1 Synchronous Serial Receive Register PIO Mode 1 Register 2 1 Synchronous Serial Transmit Register PIO Data Register 3 1 Synchronous Serial Transmit 1 Register 2 PIO Direction Register 3 12 Synchronous Serial Enable Register PIO Mode Register 3 1 Synchronous Serial Status Register 2 Rev:1.1

21 RDC RISC DSP Controller R1LV Peripheral Control Block Relocation Register: Offset : FEh Reset Value : 2FFh Res S/M Res M/IO R19 - R The peripheral control block is mapped into either memory or I/O space by programming this register. When the other chip selects (PCSx ormcsx ) are programmed to zero wait states and ignore the external ready, the PCSx ormcsx can overlap the control block. Bit 1: Reserved Bit 1: S/M, Slave/Master Configures the interrupt controller set : Master mode, set 1: Slaved mode Bit 13 : Reserved Bit 12: M/ IO, Memory/IO space. At reset, this bit is set to and the PCB map start at FFh in I/O space. set 1- The peripheral control block (PCB) is located in memory space. set - The PCB is located in I/O space. Bit 11- : R19-R, Relocation Address Bits The upper address bits of the PCB base address. The lower eight bits default to h. When the PCB is mapped to I/O space, the R19-R1 must be programmed to b. Processor Release Level Register Offset : Fh Reset Value : 3 2 D9h 1 PRL Read only register that specifies the processor release version and RDC identify number Bit 1- : Processor version 1h : version A, 2h : version B, 3h : version C, h : version D Bit - : RDC identify number - D9h 21 Rev:1.1

22 RDC RISC DSP Controller R1LV System Clock Block PSEN(Fh.1) enable/disable Microprocessor Internal Clock X1 X2 CLKIN CLKIN or CLKIN/2 CLK CLOCK Divisior (CLK/2-CLK/12) MUX CLKOUTA CLKIN/2 Select Divisor Select F2-F(Fh.2-Fh.) CAD(Fh.) CAF(Fh.9) S/CLKDIV2 MUX CLKOUTB CBD(Fh.1) CBF(Fh.11) System Clock Power-Save Control Register Offset : Fh Reset Value : h PSEN CBF CBD CAF CAD F2 F1 F Bit 1: PSEN, Enable Power-save Mode. This bit is cleared by hardware when an external interrupt occurs. This bit dose not be changed when software interrupts (INT instruction) and exceptions occurs. Set 1: enable power-save mode and divides the internal operating clock by the value in F2-F. Bit1-12: Reserved Bit 11: CBF, CLKOUTB Output Frequency selection. Set 1: CLKOUTB output frequency is same as crystal input frequency. Set : CLKOUTB output frequency is from the clock divisor, which frequency is same as that of microprocessor internal clock. Bit 1 : CBD, CLKOUTB Drive Disable Set 1: Disable the CLKOUTB. This pin will be three-state. Set : Enable the CLKOUTB. Bit 9: CAF, CLKOUTA Output Frequency selection. Set 1: CLKOUTA output frequency is same as crystal input frequency. Set : CLKOUTB output frequency is from the clock divisor, which frequency is same as that of microprocessor internal clock. Bit : CAD, CLKOUTA Drive Disable. Set 1: Disable the CLKOUTA. This pin will be three-state. 22

23 RDC RISC DSP Controller R1LV Set : Enable the CLKOUTA. Bit -3 : Reserved Bit 2-: F2- F, Clock Divisor Select. F2, F1, F Divider Factor,, ---- Divide by 1,, Divide by 2, 1, ---- Divide by, 1, Divide by 1,, ---- Divide by 1 1,, Divide by 32 1, 1, ---- Divide by 1, 1, Divide by 12 Reset Processor initialization is accomplished with activation of the RST pin. To reset the processor, this pin should be held low for at least seven oscillator periods. The Reset Status Figure shows the status of therst pin and others relation pins. WhenRST from low go high, the state of input pin (with weakly pull-up or pull-down) will be latched, and each pin will perform the individual function. The AD-AD, AO1-AO will be latched into the register Fh. UCS / ONCE 1, LCS / ONCE enter ONCE mode (All of the pins will floating except X1, X2) when with pull-low resisters. The input clock will be divided by 2 when S/ CLKDIV 2 with pull-low resister. The AD-AD, AO1-AO will not drive the address phase during UCS, LCS cycle if BHE / ADEN with pull-low resister 23

24 RDC RISC DSP Controller R1LV CLKOUTA RST A19-A (float) min T ffff S (input) AD-AD (input) f ea AO1-AO (input) ff ALE (float) RD (float) BHE (input) UCS (input) DEN (float) DT/R (float) S2-S (float) Reset Status Reset Configuration Register Offset : Fh Reset Value : AD1-AD RC Bit 1- : RC,Reset Configuration AO1-AO, AD-AD. The (AO1 to AO, AD to AD) must with weakly pull-up or pull-down resistors to correspond the contents when (AO1 to AO, AD to AD) be latched into this register during the RST pin from low go high. And the value of the reset configuration register provides the system information when software read this register. This register is read only and the contents remain valid until the next processor reset. 2

25 RDC RISC DSP Controller R1LV Bus Interface Unit The bus interface unit drives address, data, status and control information to define a bus cycle. The bus A19-A are nonmultiplex memory or I/O address. The AD-AD are multiplexed address and data bus for memory or I/O accessing. The S2 - S 1 are encoded to indicate the bus status, which is described in the Pin Description table in page. The Basic Application System Block (page ) and Read/Write Timing Diagram (page 12) describe the basic bus operation. Memory and I/O interface The memory space consists of 1M bytes and the I/O space consists of k bytes. Memory devices exchange information with the CPU during memory read, memory write and instruction fetch bus cycles. I/O read and I/O write bus cycles use a separate I/O address space. Only IN/OUT instruction can access I/O address space, and information must be transferred between the peripheral device and the AX register. The first 2 bytes of I/O space can be accessed directly by the I/O instructions. The entire k bytes I/O address space can be accessed indirectly, through the DX register. I/O instructions always force address A19-A1 to low level. FFFFFH Memory Space 1M Bytes FFFFH I/O Space K Bytes Memory and I/O Space 1M Bytes FFFFF FFFFE 2 1 First Bus Cycle (X) Second Bus Cycle (X+1) A19: D: A19: D: A19: D: -Bit Data Bus Word Transfers Data Bus Physical Data Bus Models The memory address space data bus is physically implemented as one bank of 1M bytes. Address lines A19-A select a specific byte within the bank. Byte transfers to even or odd addresses transfer information in one bus cycle. Word transfers to 2

26 RDC RISC DSP Controller R1LV even or odd addresses transfer information in two bus cycles. The Bus Interface Unit automatically converts the word access into two consecutive byte accesses, making the operation transparent to the programmer. For word transfers, the word address defines the first byte transferred. The second byte transfer occurs from the word address plus one. Wait States SRDY R2 bit in control registers D Q Bus Ready ARDY CLKOUTA D Q Falling Edge CLKOUTA Falling Edge CLKOUTA Wait-state block Diagram Watit State Counter Wait states extend the data phase of the bus cycle. The ARDY or SRDY input with high level will insert wait states. And user also can inserts wait state by programmed the internal chip select registers. The R2 bit of UMCS ( offset Ah) default is low, so each one of the ARDY or SRDY should in ready state (with pull high resistor) when at power on reset or external reset. The wait state counter value is decided by the R1,R bits in each chip select register. There are five group R2,R1,R bits in the registers offset Ah, A2h, Ah, Ah, Ah. Each group is independent. Case1 Case2 Case3 T1 T2 TW T2 T3 TW T3 TW TW T T T CLKOUTA Bus Ready Bus Ready Waveform 2

27 RDC RISC DSP Controller R1LV Bus Hold When the bus hold requested ( HOLD pin active high) by the another bus master, the microprocessor will issue a HLDA in response to a HOLD request at the end of T or Ti. When the microprocessor is in hold status (HLDA is high), the AO1- AO, AD-AD, A19-A, WR, RD, DEN, S1 - S, S, BHE, DT/ R, and WB are floating, and the UCS, LCS, PCS - PCS, MCS3 - MCS and PCS 3 - PCS will be drive high. After HOLD is detected as being low, the microprocessor will lower the HLDA. Case 1 Case 2 Ti T3 Ti T Ti Ti Ti Ti CLKOUTA HOLD HLDA AD:AD Floating AO1:AO Floating A19:A Floating DEN Floating S Floating RD Floating WR Floating DT/R Floating S2:S 2 Floating WLB Floating BUS HOLD ENTER WAVEFORM 2

28 RDC RISC DSP Controller R1LV Case 1 Case 2 Ti Ti Ti Ti Ti Ti Ti T T1 T1 CLKOUTA HOLD HLDA AD:AD Floating DATA AO1:AO Floating Address A19:A Floating ADDRESS DEN Floating S Floating RD Floating WR Floating DT/R Floating S2:S Floating WLB Floating BUS HOLD LEAVE WAVEFORM 2

29 RDC R1LV RISC DSP Controller Chip Select Unit The Chip Select Unit provides 12 programmable chip select pins to access a specific memory or peripheral device. The chip selects are programmed through five peripheral control registers (Ah, A2h, Ah, Ah, Ah). And all of the chip selects can be insert wait states by programmed the peripheral control register. UCS The UCS default to active on reset for program code access. The memory active range is upper 12k (h FFFFFh), which is programmable. And the default memory active range of UCS is k ( Fh FFFFFh). The UCS active to drive low four CLKOUTA oscillators if no wait state inserts. There are three wait-states insert to UCS active cycle on reset. Upper Memory Chip Select Register Offset : Ah Reset Value :F3Bh LB2 - LB DA R2 R1 R Bit 1 : Reserved Bit 1-12 : LB2-LB, Memory block size selection for UCS chip select pin. The UCS chip select pin active region can be configured by the LB2-LB. The default memory block size is from Fh to FFFFFh. LB2, LB1, LB ---- Memory Block size, Start address, End Address 1, 1, k, Fh, FFFFFh 1, 1, k, Eh, FFFFFh 1,, k, Ch, FFFFFh,, k, h, FFFFFh Bit 11- : Reserved Bit : DA, Disable Address. If the BHE / ADEN pin is held high on the rising edge of RST, then the DA bit is valid to enable/disable the address phase of the AD bus. If the BHE / ADEN pin is held low on the rising edge of RST, the AD bus always drive the address and data. Set 1 : Disable the address phase of the AD AD bus cycle when UCS is asserted. The AO1-AO are driven Address bus even the bit is set to 1. Set : Enable the address phase of the AD AD bus cycle when UCS is asserted. Bit -3: Reserved Bit 2 : R2, Ready Mode. This bit is used to configure the ready mode for UCS chip select. Set 1: external ready is ignored. Set : external ready is required. 29

30 RDC RISC DSP Controller R1LV Bit 1- : R1-R, Wait-State value. When R2 is set to, it can inserted wait-state into an access to the UCS memory area. (R1,R) = (,) -- wait-state ; (R1,R) = (,1) -- 1 wait-state (R1,R) = (1,) -- 2 wait-state ; (R1,R) = (1,1) -- 3 wait-state LCS The lower 12k bytes (h-9ffffh) memory region chip selects. The memory active range is programmable, which has no default size on reset. So the A2h register must be programmed first before to access the target memory range. The LCS pin is not active on reset, but any read or write access to the A2h register activates this pin. Low Memory Chip Select Register Offset : A2h Reset Value : UB2 - UB DA PSE R2 R1 R Bit 1: Reserved Bit 1-12 : UB2-UB, Memory block size selection for LCS chip select pin The LCS chip select pin active region can be configured by the UB2-UB. The LCS pin is not active on reset, but any read or write access to the A2h (LMCS) register activates this pin. UB2, UB1, UB ---- Memory Block size, Start address, End Address,, ---- k, h, FFFFh,, k, h, 1FFFFh, 1, k, h, 3FFFFh 1, 1, k, h, FFFFh Bit 11- : Reserved Bit : DA, Disable Address. If the BHE / ADEN pin is held high on the rising edge of RST, then the DA bit is valid to enable/disable the address phase of the AD bus. If the BHE / ADEN pin is held high on the rising edge of RST, the AD bus always drive the address and data. Set 1 : Disable the address phase of the AD AD bus cycle when LCS is asserted. The AO1-AO are driven address bus even the bit is set to 1. Set : Enable the address phase of the AD AD bus cycle when LCS is asserted. Bit : PSE, PSRAM Mode Enable. This bit is used to enable PSRAM support for thelcs chip select memory space. The refresh control unit registers Eh,E2h,Eh must be configured for auto refresh before PSRAM support is enabled. PSE set to 1: PSRAM support is enable PSE set to : PSRAM support is disable Bit -3: Reserved Bit 2 : R2, Ready Mode. This bit is used to configure the ready mode for LCS chip select. 3

31 RDC RISC DSP Controller R1LV Set 1: external ready is ignored. Set : external ready is required. Bit 1- : R1-R, Wait-State value. When R2 is set to, it can inserted wait-state into an access to the LCS memory area. (R1,R) = (,) -- wait-state ; (R1,R) = (,1) -- 1 wait-state (R1,R) = (1,) -- 2 wait-state ; (R1,R) = (1,1) -- 3 wait-state MCSx The memory block of MCS - MCS can be located anywhere within the 1M bytes memory space, exclusive of the areas associated with the UCS and LCS chip selects. The maximum MCSx active memory range is 12k bytes. The MCS chip selects are programmed through two registers Ah and Ah, and these select pins are not active on reset. Both Ah and Ah registers must be accessed with a read or write to activate MCS - MCS. There aren t default value on Ah and Ah registers, so the Ah and Ah must be programmed first before MCS - MCS active. Midranage Memory Chip Select Register Offset : Ah Reset Value : BA19 - BA R2 R1 R Bit 1- : BA19-BA13, Base Address. The BA19-BA13 correspond to bits of the 1M bytes (2-bits) programmable base address of the MCS chip select block. The bits 12 to of the base address are always. The base address can be set to any integer multiple of the size of the memory block size selected in these bits. For example, if the midrange block is 32Kbytes, only the bits BA19 to BA1 can be programmed. So the block address could be locate at 2h or 3h but not in 22h. The base address of the MCS chip select can be set to h only if the LCS chip select is not active. And the MCS chip select address range is not allowed to overlap the LCS chip select address range. The MCS chip select address range also is not allowed to overlap the UCS chip select address range. Bit -3 : Reserved Bit 2: R2, Ready Mode. This bit is configured to enable/disable the wait states inserted for the MCS chip selects. The R1,R bits of this register determine the number of wait state to insert. set to 1: external ready is ignored set to : external ready is required Bit 1- : R1-R, Wait-State value. The R1,R determines the number of wait states inserted into a MCS access. (R1,R) : (1,1) 3 wait states, (1,) 2 wait states, (,1) 1 wait states, (,) wait states 31

32 RDC RISC DSP Controller R1LV PCS and MCS Auxiliary Register Offset : Ah Reset Value : M - M EX MS R2 R1 R Bit 1: Reserved Bit 1-: M-M, MCS Block Size. These bits determines the total block size for the MCS3 - MCS chip selects. Each individual chip select is active for one quarter of the total block size. For example, if the block size is 32K bytes and the base address is located at 2h. The individual active memory address range of MCS3 to MCS is MCS 2h to 21FFF, MCS1-22 to 23FFFh, MCS2-2h to 2FFFh, MCS3-2h to 2FFFh. MCS total block size is defined by M-M, M-M, Total block size, MCSx address active range 1b, k, 2k 1b, 1k, k 1b, 32k, k 1b, k, 1k 1b, 12k, 32k 1b, 2k, k 1b, 12k, 12k Bit : EX, Pin Selector. This bit configures the multiplex output which the PCS - PCS pins as chip selects or A2-A1. Set 1 : PCS, PCS are configured as peripheral chip select pins. Set : PCS is configured as address bit A2, PCS is configured as A1. Bit : MS, Memory or I/O space Selector. Set 1: The PCSx pins are active for memory bus cycle. Set : The PCSx pins are active for I/O bus cycle. Bit -3 : Reserved Bit 2 : R2, Ready Mode. This bit is configured to enable/disable the wait states inserted for the PCS,PCS chip selects. The R1,R bits of this register determine the number of wait state to insert. set to 1: external ready is ignored set to : external ready is required Bit 1- : R1-R, Wait-State value. The R1,R determines the number of wait states inserted into a PCS - PCS access. (R1,R) : (1,1) 3 wait states, (1,) 2 wait states, (,1) 1 wait states, (,) wait states PCSx The peripheral or memory chip selects which are programmed through Ah and Ah register to define these pins. The base address memory block can be located anywhere within the 1M bytes memory space, exclusive of the areas associated 32

33 RDC RISC DSP Controller R1LV with the MCS, LCS and MCS chip elects. If the chip selects are mapped to I/O space, the access range is k bytes. PCS PCS can be configured from wait-state to 3 wait-states. PCS3 PCS can be configured from wait-state to 1 waitstates. Peripheral Chip Select Register Offset : Ah Reset Value : BA19 - BA R3 R2 R1 R Bit 1- : BA19-BA11, Base Address. BA19-BA11 correspond to bit of the 1M bytes (2-bits) programmable base address of thepcs chip select block. When the PCS chip selects are mapped to I/O space, BA19-BA1 must be wrote to b because the I/O address bus in only K bytes (1-bits) wide. PCSx address range: PCS : Base Address - Base Address + FFh PCS1 : Base Address + 1h - Base Address + 1FFh PCS2 : Base Address + 2h - Base Address + 2FFh PCS3 : Base Address + 3h - Base Address + 3FFh PCS : Base Address + h - Base Address + FFh PCS : Base Address + h - Base Address + FFh Bit -: Reserved Bit 3: R3; Bit 1-: R1,R,Wait-State Value. The R3,R1,R determines the number of wait-states inserted into a PCS3 - PCS access. R3, R1, R -- Wait States,, --,, , 1, -- 2, 1, ,, -- 1,, , 1, , 1, Bit 2 : R2, Ready Mode. This bit is configured to enable/disable the wait states inserted for the PCS3 - PCS chip selects. The R3,R1,R bits determine the number of wait state to insert. set to 1: external ready is ignored set to : external ready is required 33

34 RDC R1LV RISC DSP Controller Interrupt Controller Unit There are twelve interrupt requests source connect to the controller: five maskable interrupt pins ( INT INT); one nonmaskable interrupt pin (NMI) ; Six internal unit request source ( Timer, 1,2 ;DMA,1 ; Asynchronous serial unit). Master/Slave Mode Select (FEH.1) Timer/1/2 Interrupt REQ. Timer REQ. INT 1 Interrupt Control Logic Interrupt Type Interrupt REQ. Execation Unit Timer1 REQ. 1 Timer2 REQ. 1 DMA Interrupt REQ. DMA1 Interrupt REQ. INT2 EOI Register 1 Bit INT3 INT Asynchronous Serial Port Acknowledge In-Service Register Acknowledge to DMA, Timer,Serial port Unit 1 Bit Internal Address/Data Bus Interrupt Control Unit Block Diagram Master Mode and Slave Mode The interrupt controller can be programmed as a master or slave mode. (program FEh, bit 1). The master mode has two connections : Fully Nested Mode connection or Cascade Mode connection. INT INT1 INT2 INT3 INT Interrupt Source Interrupt Source Interrupt Source Interrupt Source Interrupt Source R1LV Fully Nested Mode Connections 3

35 RDC RISC DSP Controller R1LV Interrupt Sources INT INT 29 IR INT INTA 29 INTA CAS3-CAS Interrupt Sources CAS3-CAS R1LV INT1 IR 29 Interrupt Sources INTA1 CAS3-CAS 29 INT INTA CAS3-CAS Interrupt Sources Cascade Mode Connection INT 29 INTA R1LV Select Cascade Address Dccode IRQ Slave Mode Connection Interrupt Vector, Type and Priority The following table shows the interrupt vector addresses, type and the priority. The maskable interrupt priority can be changed by programmed the priority register. The Vector addresses for each interrupt are fixed. Interrupt source Interrupt Type Vector Address EOI Type Priority Divide Error Exception h h 1 Trace interrupt 1h h 1-1 * NMI 2h h 1-2 * Breakpoint Interrupt 3h Ch 1 INTO Detected Over Flow Exception h 1h 1 Note 3