Combining TLM & RTL Techniques:

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1 Combining TLM & RTL Techniques: A Silver Bullet for Pre-Silicon HW/SW Integration Frank Schirrmeister EDPS Monterey April 17 th 2014

2 Hardware/Software Systems Software Bare Metal Applications Communications L3 Middleware Operating Systems (OS) Drivers Firmware / HAL Bare Metal Software DSP Software Bare Metal Sofwtare Communications L2 Communications L1 RTOS Drivers Firmware / HAL Modem Comms Application Processor ARM CPU Subsystem Cortex -A15 D D R 3 P H Y Cortex -A15 L2 cache 3. 0 P H Y USB 3.0 Cortex -A P H Y Cortex A-A7 L2 cache Cache Coherent Fabric PCIe Gen 2,3 PHY Application Specific Components 3D GFX High speed, wired interface peripherals DSP A/V SoC Interconnect Fabric Et h er n et P H Y HD MI SAT A MIPI WL AN LTE Other peripherals Apps Accel Modem GP UA IO RT IN Display TC PM I2 U C MI SP PI I Ti Low-speed JT peripheral me AG subsystem r Low speed peripherals FM Receiver GPS Receiver Cellular Modem WiFi Bluetooth RFFE DigRF SDIO DRAM LPDDR LPDDR 2 Motion Sensors LPDDR 3 SLIMbus Power Control SPMI NAND NAND FLASH USB 2.0 emmc 4.5 UFS LLI USB 3.0 OTG Memory Card SD 3.0 SD 4.0 UFS cjtag I2C GBT CSI2 CSI3 Multimedia Processor OCP 2.0 OCP 3.0 Touch Screen Controller SLIMbus Camera Interface Display Driver DSI Audio Interface HDMI 1.4 System on Chip (SOC) System on Printed Circuit Board (PCB) Cadence Design Systems, Inc. All rights reserved.

3 A project schedule, reconstructed Percentage of Project Effort 30% effort Application Software Development Specification Development RTL Development OS Support 10% effort 13% effort Utility Software Development Design Management 54% time 54% time 72% time 21% effort RTL Verification to Netlist 55% time 9% effort Netlist to Tapeout 56% time Post Silicon Validation 11% effort Qualification of IP 45% time Elapsed time as percentage of time from RTL Development to Tapeout RTL Development to Tapeout Cadence Design Systems, Inc. All rights reserved.

Software Development Tools For end users, large #

Run/Real-Time Kernel Drivers System Hardware

Licensed IP; sometimes developed in-house

developed internally PCB Board Integration: PCB

Software Enablement: Emulation, Acceleration,

Verification: Verification IP, Silicon Virtual

5 Where do HW and SW meet, actually? esw Tools Content Apps Middleware Embedded Software Development Tools For end users, large # of developers Often licensed with OS? Run/Real-Time Kernel Drivers System Hardware Assembler, Compiler, Linker, Debugger, EDA Licensed IP; sometimes developed in-house Expected to come with hardware IP, otherwise be developed internally PCB Board Integration: PCB Tool Sets System Design System on Chip Sub-system Software Enablement: Emulation, Acceleration, FPGA based prototyping and Virtual Prototyping Verification: Verification IP, Silicon Virtual Prototype Design: Design IP, Interconnect, Analysis Tools Cadence Design Systems, Inc. All rights reserved.

8 Who is doing what in a Changing World? Networks Operators Operators AT&T AT&T, Verizon Operators Operators Operators HTML Apps Chrome Web Store Chrome Web Store Chrome Web Store Chrome Web Store Device Apps System Middleware Operating System Nokia Ericsson Symbian, Palm OS Nokia, Ericsson, Palm, Samsung Symbian, Palm OS Apple Apps Store Apple iphone Apple Apps Store Google Play Google Motorola Google Android Chrome Book Acer Samsung Google Chrome OS on Linux Google Play Google Nexus 10 Samsung Google Android Google Play Microsoft Nokia Windows Mobile Google Play System Houses Google Android & ChromeOS Drivers Firmware Chip Nokia TI, Qualcomm, Motorola TI, Qualcomm, Freescale Samsung Apple iphone 3GS All Semis Intel Atom N570 Samsung Exynos 5250 All Semis All Semis Sub-System IP ARM big.little, Imagination, MIPS, Tensilica ARC Atom ARM big.little +Mali, Nvidia Kepler, IMG+MIPS, Tensilica, ARC ARM big.little +Mali, Nvidia Kepler, IMG+MIPS, Tensilica, ARC Cadence Design Systems, Inc. All rights reserved.

Who Develops What? New Industry Dynamics!

Pressure Networks HTML Apps Device Apps System

Chip Sub-System IP Growing Responsibilities

Value Stack Software, Integration Subsystems 9

9 Who Develops What? New Industry Dynamics! Infrastructure, Connectivity, Complexity Value Pressure Networks HTML Apps Device Apps System Middleware Operating System Drivers Firmware Chip Sub-System IP Growing Responsibilities Require Us to Address More Portions of the Value Stack Software, Integration Subsystems Cadence Design Systems, Inc. All rights reserved.

There is no One Size Fits All Verification and Software platforms need to

Acceleration Emulation FPGA Prototype Prototyping Board Highest speed Earliest in

Great to debug (but less detail) Easy replication Nonscalable Exhaustive Early RTL

available Mixedabstractions Limited SW execution MHz Range RTL accurate After RTL

accurate After stable RTL is available OK to debug More expensive than software to

hard to replicate 11 2014 Cadence Design Systems, Inc. All rights reserved.

11 There is no One Size Fits All Verification and Software platforms need to interoperate SDK OS Simulation Virtual Platform Formal Analysis HDL Simulation Acceleration Emulation FPGA Prototype Prototyping Board Highest speed Earliest in the flow Ignore hardware Almost at speed Less accurate (or slower) Before RTL Great to debug (but less detail) Easy replication Nonscalable Exhaustive Early RTL Great for IP No SW execution KHz range Accurate Excellent HW debug Broadly available Mixedabstractions Limited SW execution MHz Range RTL accurate After RTL is available Good to debug with full detail Expensive to replicate 10 s of MHz RTL accurate After stable RTL is available OK to debug More expensive than software to replicate Real time speed Fully accurate Post Silicon Difficult to debug Sometimes hard to replicate Cadence Design Systems, Inc. All rights reserved Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and the Cadence logo are trademarks of Cadence Design Systems, Inc. in the United States and other countries. All other trademarks are the property of their respective owners and are not affiliated with Cadence.

12 Timing is Critical for HW/SW Development SoC in System Time for critical bugs in System Environment to be removed System on Chip Sub-System IP Idea to spec RTL Becomes stable Only small gate level changes and ECO s Production Post silicon Validation Spec RTL-Design and IP Integration and Verification IP Qualification Netlist to GDSII Fab Post Si Cadence Design Systems, Inc. All rights reserved.

13 Timing is Critical for Modeling for Software Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS and Drivers (Linux, Android) Bare-metal SW May hold final tape out if bug too critical Classic Post Silicon Testing SW development on chip SoC in System Time for critical bugs in system environment to be removed System on Chip Sub-System IP Idea to spec RTL becomes stable Only small gate level changes and ECOs Production Post-silicon validation Spec RTL-Design and IP Integration and Verification IP Qualification Netlist to GDSII Fab Post Si Cadence Design Systems, Inc. All rights reserved.

14 User Tasks and Requirements Applications (Basic to Angry Birds) Middleware (Graphics, Audio) Software Integration and QA Speed, SW Debug OS and Drivers (Linux, Android) Bare-metal SW SoC in System System on Chip Sub-System IP System Modeling & Trade Offs Time of Availability, Speed, Accuracy Early Software Development Time of Availability,, Speed, SW Debug IP Selection and Design Verification HW Debug, Turnaround Time SoC and Sub-System Verification HW Debug, Turnaround Time, SW Debug, Speed HW-SW Validation: SoC with Bare-Metal Software and OS SW Debug, HW Debug, Speed, Turnaround Time Gate Level & Timing & Power Signoff System and Silicon Validation Speed Spec RTL-Design and IP Integration and Verification IP Qualification Netlist to GDSII Fab Post Si Cadence Design Systems, Inc. All rights reserved.

15 RTL Simulation Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS and Drivers (Linux, Android) Bare-metal SW SoC in System System on Chip Sub-System IP System Modeling & Trade Offs Time of Availability, Speed, Accuracy IP and Sub-system Verification, Gate-Level Engine for Performance Analysis Early Software Development Time of Availability,, Speed, SW Debug IP Selection & Design Verification and VIP HW Debug, Turnaround Time SoC & Sub-System Verification HW Debug, Turnaround Time, SW Debug, Speed Metric-Driven Verification Software Integration and QA Speed, SW Debug HW-SW Validation: SoC with Bare-Metal Software & OS SW Debug, HW Debug, Speed, Turnaround Time Gate Level & Timing & Power Signoff Gate- Level Sim Fast Turnaround Time, Hardware Debug Metric-Driven Verification Debug VIP System & Silicon Validation Speed Spec RTL-Design & IP Integration & Verification IP Qualification Netlist to GDSII Fab Post Si Cadence Design Systems, Inc. All rights reserved. 15

16 Virtual Prototyping Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS and Drivers (Linux, Android) Bare-metal SW SoC in System System on Chip Sub-System IP System Modeling & Trade Offs Time of Availability, Speed, Accuracy Early, SW Debug and Pre RTL SW Development and System Validation HW/SW Debug Software Integration and QA Speed, SW Debug RTL Integration Integrated SW Debug Early Software Development Time of Availability,, Speed, SW Debug Virtual Prototyping IP Selection & Design Verification and VIP HW Debug, Turnaround Time SoC & Sub-System Verification HW Debug, Turnaround Time, SW Debug, Speed Metric-Driven Verification HW-SW Validation: SoC with Bare-Metal Software & OS SW Debug, HW Debug, Speed, Turnaround Time Gate Level & Timing & Power Signoff Gate- Level Sim System & Silicon Validation Speed Spec RTL-Design and IP Integration and Verification IP Qualification Netlist to GDSII Fab Post Si Cadence Design Systems, Inc. All rights reserved. 16

17 Acceleration and Emulation Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS and Drivers (Linux, Android) Bare-metal SW SoC in System System on Chip Sub-System IP System Modeling & Trade Offs Time of Availability, Speed, Accuracy Early Software Development Time of Availability,, Speed, SW Debug Virtual Prototyping IP Selection & Design Verification HW Debug, Turnaround Time SoC & Sub-System Verification HW Debug, Turnaround Time, SW Debug, Speed Acceleration and AVIP Metal-Driven Verification and VIP HW-SW Validation: SoC with Bare-Metal Software & OS SW Debug, HW Debug, Speed, Turnaround Time Emulation PXP Gate Gate Level & Timing & Power Signoff Gate- Level Sim Bring-up time, Speedup over RTL, Early SW, OS and Above SW Bring Up; System Validation on Accurate, Maturing, and Non-stable (RTL) HW Software Integration Accuracy, SW and QA ICE, Speedbridges, Speed, SW Debug Virtualization. Multi-User Access, Power Analysis, Debug Efficiency Acceleration, Gate-Level System & Silicon Validation Speed Spec RTL-Design and IP Integration and Verification IP Qualification Netlist to GDSII Fab Post Si Cadence Design Systems, Inc. All rights reserved. 17

18 FPGA-Based Prototyping Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS and Drivers (Linux, Android) Bare-metal SW SoC in System System on Chip Sub-System IP Low-cost and Faster Pre-silicon SW Development, Regressions, Subsystem Validation on Mature and Stable HW with Real-world Interfaces System Modeling & Trade Offs Time of Availability, Speed, Accuracy Early Software Development Time of Availability,, Speed, SW Debug Virtual Prototyping IP Selection & Design Verification HW Debug, Turnaround Time SoC & Sub-System Verification HW Debug, Turnaround Time, SW Debug, Speed Acceleration and AVIP Metric-Driven Verification and VIP HW-SW Validation: SoC with Bare-Metal Software & OS SW Debug, HW Debug, Speed, Turnaround Time Emulation Software Integration and QA Speed, SW Debug Faster Bring-up Integration Gate Level & Timing & Power Signoff Gate- Level Sim Speedup over Emulation Better Cost, Access FPGA-Based Prototyping System & Silicon Validation Speed Spec RTL-Design and IP Integration and Verification IP Qualification Netlist to GDSII Fab Post Si Cadence Design Systems, Inc. All rights reserved. 18

19 Software Development on the Actual Chip Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS & Drivers (Linux, Android) Bare metal SW SoC in System System on Chip Sub-System IP System Modeling & Trade Offs Time of Availability, Speed, Accuracy Early Software Development Time of Availability,, Speed, SW Debug Virtual Prototyping SoC & Sub-System Verification HW Debug, Turnaround Time, SW Debug, Speed Acceleration and AVIP IP Selection & Design Verification HW Debug, Turnaround Time RTL simulation HW-SW Validation: SoC with Bare-Metal Software & OS SW Debug, HW Debug, Speed, Turnaround Time Emulation Software Integration and QA Speed, SW Debug Gate Level & Timing & Power Signoff Gate- Level Sim FPGA Based Prototyping System & Silicon Validation Speed Chip Spec RTL-Design & IP Integration & Verification IP Qualification Netlist to GDSII Fab Post Si Cadence Design Systems, Inc. All rights reserved.

20 HW/SW Development Care Abouts CONCEPT Software PRODUCT TLM Virtual RTL Simulation RTL Emulation FPGA Based Prototyping Chip SW Development Hardware FPGA-based Prototyping HW/SW Validation Early Software Development Software Debug Acceleration Emulation HW/SW Verification System Speed - + RTL Simulation HW Verification Hardware Accuracy Virtual Prototyping SW Development Hardware Debug and Turn-around-time Cadence Design Systems, Inc. All rights reserved. 20

Integration of Development Engines 21 2014

22 The Challenge of Bug Re-Production Consistent HW/SW Verification Environment Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS & Drivers (Linux, Android) Bare metal SW SoC in System System on Chip Sub-System IP System Modeling & Trade Offs Time of Availability, Speed, Accuracy Early Software Development Time of Availability,, Speed, SW Debug Virtual Prototyping SoC & Sub-System Verification HW Debug, Turnaround Time, SW Debug, Speed Acceleration and AVIP IP Selection & Design Verification HW Debug, Turnaround Time RTL simulation HW-SW Validation: SoC with Bare-Metal Software & OS SW Debug, HW Debug, Speed, Turnaround Time Emulation Software Integration and QA Speed, SW Debug Gate Level & Timing & Power Signoff Gate- Level Sim FPGA Based Prototyping System & Silicon Validation Speed Chip Spec RTL-Design & IP Integration & Verification IP Qualification Netlist to GDSII Fab Post Si Cadence Design Systems, Inc. All rights reserved.

Software Based Testing and Benchmarking Test DB Quality Assurance Tests SoC Stress Tests Graphics Tests Validate

Libraries HAL Drivers Android Linux Graphics Kernel Mode Resources Memory Power Win RT Bring-Up and Validate OS Stack

Bring-up Boot code, Firmware Verify HW/FW Bring-Up FW on SoC SW Development Boot code, device drivers, Kernel, SoC

23 Software Based Testing and Benchmarking Test DB Quality Assurance Tests SoC Stress Tests Graphics Tests Validate HW/SW with OS-based Tests Regression Automation SoC Basic Tests Graphics HAL Drivers Test Linux Graphics Framework Libraries HAL Drivers Android Linux Graphics Kernel Mode Resources Memory Power Win RT Bring-Up and Validate OS Stack with SoC Bring-Up OSs (stock) HW/Firmware Bare-Metal Tests Registers, memory, device drivers, sub-system Firmware Bring-up Boot code, Firmware Verify HW/FW Bring-Up FW on SoC SW Development Boot code, device drivers, Kernel, SoC Drivers Develop SW Modules Color Key Production SW Test / Verification SW Cadence Design Systems, Inc. All rights reserved.

Broadcom Example 1/3 Source: Verification Summit, September

Broadcom Example 2/3 Source: Verification Summit, September

Broadcom Example 3/3 Source: Verification Summit, September

27 Hybrids TLM & Accelerated RTL The Best of Both Worlds Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS and Drivers (Linux, Android) Bare-metal SW SoC in System System on Chip Sub-System IP Early SW Development, OS and Above SW Bring Up and SW- Based System Validation on Accurate Still Maturing, Non-stable (RTL) HW System Modeling & Trade Offs Time of Availability, Speed, Accuracy Early Software Development Time of Availability,, Speed, SW Debug Virtual Prototyping IP Selection & Design Verification HW Debug, Turnaround Time SoC & Sub-System Verification HW Debug, Turnaround Time, SW Debug, Speed Acceleration and AVIP Metric-Driven Verification and VIP HW-SW Validation: SoC with Bare-Metal Software & OS SW Debug, HW Debug, Speed, Turnaround Time Emulation Software Integration and QA Speed, SW Debug Smart Synchronization Gate Level & Timing & Power Signoff Gate- Level Sim Speed, Debug Insight - Get to SW on OS Faster FPGA-Based Prototyping System & Silicon Validation Speed Chip Spec RTL-Design and IP Integration and Verification IP Qualification Netlist to GDSII Fab Post Si Cadence Design Systems, Inc. All rights reserved. 27

28 NVIDIA SW Validation with Palladium/VSP Hybrid OS-based Tests Test Scenarios 2D, 3D L2 L1 Sanity Checks L0 Graphics DX SoC Drivers Kernel Mode Driver Resource Manager Memory Manager KMD RM NVMEM Test & Metrics DB Target OS Power Manager NVPEP Linux Win RT Android Emulation Tests External Stimulus Into AXI bus Arch. MODS Test Infrastructure External Register Access Sim Front Test Gen3 Regression Automation AXI Commands To/from DUT Interrupts from DUT Test Configuration Source: CDNLive 2014 Hybrid

29 Performance Results Boot OSes, run real world applications and benchmarks Linux kernel boot Android Palladium only = 45 mins Hybrid = 2 mins Palladium only = Hours* Hybrid = mins Windows Palladium only = Days* Hybrid = mins Source: CDNLive 2014

30 SW Validation Results Eliminated reliance on other pre-silicon platforms SW problems found prior to Silicon return SW race conditions Memory management bugs Code completeness After silicon return Contributed to smoother bring-up SW Ready to demo product at SOL Less bugs resulted in focused effort to tune for power and perf Source: CDNLive 2014

31 Summary There is a huge opportunity to optimize development at the hardware/software interface Lower layers of software - up to the OS and base apps - need to be part of verification prior to chip tape out The market of users is constantly changing Software developers are increasing distance, and when not then they need more accuracy, driving needs in verification re-use and hybrid engine combinations Cadence Design Systems, Inc. All rights reserved.

32 So what does this mean for EDA? The future is already here it's just not very evenly distributed 32 "The Science in Science Fiction" on Talk of the Nation, NPR (30 November 1999, Timecode 11:55), William Gibson Cadence Design Systems, Inc. All rights reserved.

Embedded HW/SW Co-Development

Embedded HW/SW Co-Development It May be Driven by the Hardware Stupid! Frank Schirrmeister EDPS 2013 Monterey April 18th SPMI USB 2.0 SLIMbus RFFE LPDDR 2 LPDDR 3 emmc 4.5 UFS SD 3.0 SD 4.0 UFS Bare Metal