Extending HyperTransport Technology to 8.0 Gb/s in 32-nm SOI-CMOS Processors

Transcription

1 Extending HyperTransport Technology to 8.0 Gb/s in 32-nm SOI-CMOS Processors Bruce Doyle, Alvin Loke, Sanjeev Maheshwari, Charles Wang, Dennis Fischette, Jeffrey Cooper, Sanjeev Aggarwal, Tin Tin Wee, Chad Lackey, Harishkumar Kedarnath, Michael Oshima, Gerry Talbot & Emerson Fang Advanced Micro Devices, Inc.

2 Motivation High demand for multi-socket processor systems from explosive growth in server market Cores per die increasing faster than I/O capability Server performance increasingly limited by I/O bandwidth between sockets I/O technology shifts (e.g., PCIe-3) revolutionary in architecture & design, introduces product risk Evolutionary enhancements to existing I/O design can improve server system performance without revolutionary shifts 2

3 Evolution of AMD Server Processors Shanghai 45nm 4 cores & 4 HT I/O Magny Cours 45nm 6 cores & 4 HT I/O Orochi 32nm 8 cores & 4 HT I/O GOAL: 6.4Gb/s8.0Gb/s through modest improvements with jitter, return loss & constant power +25% I/O aggregate BW up to +8% system performance!! 3

4 Motivation Outline HyperTransport Overview Extending HT to 8Gb/s Forwarded Clock Jitter Filtering Wideband Digital Clean-Up PLL Power & Performance Optimization Silicon Results Conclusion 4

5 Motivation Outline HyperTransport Overview Extending HT to 8Gb/s Forwarded Clock Jitter Filtering Wideband Digital Clean-Up PLL Power & Performance Optimization Silicon Results Conclusion 5

6 Processor-to-Processor Link 6 Embedded NorthBridge (NB) Embedded NorthBridge (NB)

7 HT Link Characteristics Source synchronous Forward half-rate clock for RX data retiming Common-mode jitter rejection, low latency NRZ PAM-2 signaling 2.4 to 6.4Gb/s per lane 2 sublinks of 1 CLK lane + 9 data lanes DLL-based CDR 7

8 Motivation Outline HyperTransport Overview Extending HT to 8Gb/s Forwarded Clock Jitter Filtering Wideband Digital Clean-Up PLL Power & Performance Optimization Silicon Results Conclusion 8

9 Jitter in Forwarded Clock Links TX Data In TJ tx Data Lane D Q Data Out RX DATA CLK Forwarded Clock Lane 9

10 Jitter in Forwarded Clock Links TX Data In TJ tx c Data Lane TJ tx ( c + rx) rx D Q Data Out RX DATA CLK cdr c Forwarded Clock Lane rx dis TJ tx ( c + rx + dis + cdr ) 10

11 Clock & Data Phase Relationship data t 2 f t A sin(2 f t) c m m hase, P data t t? clock clock Time, t t t data 11

12 Sampling Jitter vs. Delay Mismatch Jitter Transfer r (db) J sample 2 sin( f m ) 10 = Jitter Modulation Frequency, f m (MHz) 12

13 Sampling Jitter vs. Delay Mismatch Jitter Transfer r (db) J sample = 160ps 2 sin( f ) m jitter amplification Jitter Modulation Frequency, f m (MHz) 13

14 Sampling Jitter vs. Delay Mismatch Jitter Transfer r (db) J sample =50ns 5.0ns 2 sin( f ) m jitter amplification Jitter Modulation Frequency, f m (MHz) 14

15 Desired Jitter Filtering Behavior f m 1 6 f m 1 6 data t Ph hase, clock t 2 f no sampling jitter c doubling of sampling jitter Time, t Time, t 15

16 Desired Jitter Filtering Behavior f m 1 6 f m 1 6 data t Ph hase, clock t 2 f no sampling jitter c sampling jitter transfer bounded to unity Time, t Time, t 16

17 Jitter Filtering Example ( 2ns) Jitter Transf fer (db) without jitter filtering 6dB peaks at 250 & 750MHz with jitter filtering Jitter Modulation Frequency, f m (MHz) 17

18 Motivation Outline HyperTransport Overview Extending HT to 8Gb/s Forwarded Clock Jitter Filtering Wideband Digital Clean-Up PLL Power & Performance Optimization Silicon Results Conclusion 18

19 HT I/O with Clean-Up PLL Embedded NorthBridge (NB) Embedded NorthBridge (NB) Clean- Up PLL Clean- Up PLL 19

20 Wideband Digital Clean-Up PLL Local REFCLK N Integral Correction To DLLs 14 Received Forwarded d Clock Early/Late Phase Comparator early2 early1 late1 late2 ±f bb1 ±f bb2 Proportional Correction Adjustable bandwidth for jitter shaping (200MHz default) Variable bang-bang rate (f bb1 to f bb1 +f bb2 ) Coarse frequency calibration to local REFCLK for PVT Low loop latency 20

21 Motivation Outline HyperTransport Overview Extending HT to 8Gb/s Forwarded Clock Jitter Filtering Wideband Digital Clean-Up PLL Power & Performance Optimization Silicon Results Conclusion 21

22 TX Output Driver 45nm Hybrid Mode 32nm Voltage Mode Power 20% Return loss & DCD 22

23 RX 4:1 Deserializer 45nm 32nm Power 35%, latency 23

24 RX Front End AC coupling to reduce CLK DCD 1-bit speculative (loop-unrolled) DFE 24

25 Motivation Outline HyperTransport Overview Extending HT to 8Gb/s Forwarded Clock Jitter Filtering Wideband Digital Clean-Up PLL Power & Performance Optimization Silicon Results Conclusion 25

26 Measurement Setup Embedded d NorthBr ridge (NB) ) HT I/O configured in NB loopback mode Test overage of full I/O subsystem 26

27 Measured TX Eye 8Gb/s PRBS-15 27

28 RX Eye with Jitter Modulation inject 0.4UI pp sinusoidal id jitter 28

29 Impact of Clean-Up PLL Mea asured BER clean-up PLL 1500 disabled 1000 enabled Jitter Modulation Frequency (MHz) 0.4UI pp jitter amplitude Clean-up PLL removes >300MHz jitter 29

30 Measured Power Consumption SOI-CMOS Data Rate Technology (Gb/s) HT I/O Energy Power Power Efficiency (W) (pj/bit) 45nm % nm % % higher data rate with only 5% more power 30

31 Conclusion Achieved higher processor link bandwidth through evolutionary enhancements in I/O design 25% boost in lane data rate Sampling jitter reduction with clean-up PLL Near constant power consumption for socket compatibility Improves server system performance with minimal product risk 31

32 감사합니다 32