Génération de tests basés sur les modèles pour des systèmes sur puce avec cohérence de caches
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1 Génération de tests basés sur les modèles pour des systèmes sur puce avec cohérence de s Massimo Zendri & Abderahman Kriouile STMicroelectronics DCG / IP dev / FVS
2 Model based test generation for coherent Systems On Chips Massimo Zendri & Abderahman Kriouile STMicroelectronics DCG / IP dev / FVS
3 Where you find us 3 Our MEMS & Sensors are augmenting the consumer experience Our digital consumer products are powering the augmented digital lifestyle Our automotive products are making driving safer, greener and more entertaining Our Microcontrollers are everywhere making everything smarter and more secure Our smart power products are allowing our mobile products to operate longer and making more of our energy resources
4 Towards the Home Cloud 4 Medium Screen Clients Small Screen Clients Home Cloud Home Automation Clients Broadcast Set-Top Box Over-The-Top Services Big Screens Personal Clients On the Move Operator Managed Network & Services Home gateway Connected Client & Server
5 Heterogeneous System-on-Chip (SoC) 5 Need for System-Level Cache Coherency ARM proposed ACE specification: standard for system level coherency
6 Simulation-Based Testing 6 CPU with CPU with video decoder without Cache Coherent Interconnect (CCI) Verilog/VHDL A. KRIOUILE, W. SERWE Using Formal Model to Improve Verification of Cache-Coherent SoC
7 Simulation-Based Testing 7 Interface-level CPU with CPU with video decoder without Monitor Monitor Monitor Assertions: CPU behavior Constraints: CCI behavior Expressed as SystemVerilog assertions or PSL properties Cache Coherent Interconnect (CCI) Verilog/VHDL Formal blocks Non-formal blocks A. KRIOUILE, W. SERWE Using Formal Model to Improve Verification of Cache-Coherent SoC
8 Model Checking 8 (without running any test) Assertions Monitor Monitor Monitor (CCI Constraints) Assertion i Constraints Cache Coherent Interconnect (CCI) Verilog/VHDL Applying restrictions for more exploration Limitation due to state-space explosion problem
9 HW Model Based Test Generator 9
10 Need for System-Level Verification 10 System-level CPU with CPU with GPU without Monitor W (L, D 1 ) W (L, D 1 ) 1 ) Monitor Monitor W (L, D 2 ) Cache Coherent Interconnect (CCI) Verilog/VHDL W (L, D 2 )
11 Formal Model of an ACE-based SoC 11 ACE master 1 (big) Line_1 Line_2 ACE master 2 (LITTLE) Line_1 Line_2 ACE-Lite master (GPU) AR R AW W B AC CR CD AR R AW W B AC CR CD AR R AW W B ACE port 1 ACE port 2 ACE-Lite port CCI (-coherent interconnect) AXI port AR R AW W B AXI slave (non--coherent NoC/memory) Interface transfers modeled by rendezvous 3400 lines of LNT code derived from ACE specification Parametric: #masters, forbidden ACE transactions, [Kriouile-Serwe-13] Formal Analysis of the ACE Specification for Cache Coherent Systems-on-Chip, FMICS, LNCS 8187, 2013
12 CADP: OCIS (Open/Cæsar Interactive Simulator) 12 language-independent tree-like scenarios save/load scenarios source code access dynamic recompile
13 Generation of System-Level Test Cases 13 function CIC formal model restricted model interesting configurations system properties model checker counterexamples test generation [Tretmans-92] [Jard-Jeron-05] IVK abstract test cases test purposes coverage-directed solver concrete RTL tests
14 IVK (Interconnect Verification Kit): Automated Interconnect Testbench Generation 14 design Framework setup HDL wrapping AXI AXI AXI T3 Master agent Master agent Master agent Initiator agent DUT ICN Scoreboard Interconnect ICN TDL T3 AXI AHB APB T1 Target agent Slave agent Slave agent Slave agent Target agent tests checks coverage Inputs Architectural description (TDL) either generated by interconnect designers GUI or through Excel flow Outputs Full Verification Environment, including sequences and coverage models
15 Several Kinds of Derived Tests generated CTGs (Complete Test Graphs) > 296 simple system-level tests for each correct initial state with two masters possibly sharing a memory line, initiate all permitted transitions check correct behavior of the Cache Coherent Interconnect (e.g., generation of corresponding snoops) 10 sequence tests to recreate counter-examples concurrency between transactions conditioned by response of the Cache Coherent Interconnect
16 Results IVK tests generated Many problems identified on the verification environment (VIP components) System level assertions to check system behavior 100% coverage of system level assertions Reproduction of 1 suspected architectural issue Used on 2 currently developed products (codenamed Orly3 and Barcelona)
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