Specification and Validation for Heterogeneous MP-SoCs
|
|
- Alan Bailey
- 5 years ago
- Views:
Transcription
1 Specification and Validation for Heterogeneous MP-SoCs Gabriela Nicolescu Ecole Polytechnique de Montréal Tel : (514) ext 5434 Fax: (514) gabriela.nicolescu@polymtl.ca
2 Heterogeneous SoC MEMS RISC Hw Components Config. Proc. Optical components Electro- Biological Components Communication Optical interconnect interconnect Paradigm shift SoCs are drivers for several technologies integration Applications automotive, communications, medical, defense 2
3 New technologies for heterogeneous SoC 3D System In Package Integration Specific components are fabricated on individual wafers and then integrated onto a single chip- scaled package Benefits Increased performance Increased integration density Reduced power consumption Wireless communication schemes Based on Capacitive coupling Based on Inductive coupling New system-level trade-off Source : Balinga, Banerjee 3
4 Outlook for the design of heterogeneous SoC Access to physical prototyping for multi- technology SoCs is a major challenge Significant cost Harder to influence standard processes Modeling and simulation becomes a necessary alternative in design space exploration for these systems Few existing approaches More research needed 4
5 Heterogeneous SoC Specification & Validation Optical Control Mechanical Extensions of existing tools/languages Homogeneous environment Classical HDLs + AMS concepts + new features for sim scheduler VHDL-AMS, Verilog- AMS, SystemC-AMS No powerful libraries 5
6 Heterogeneous SoC Specification & Validation Optical -1e-005-8e-006-6e-006-4e-006-2e e e-006 2e-006 4e-006-6e-006 6e-006-8e-006 8e-006 1e-005-1e-005 "chatoyant/wf4.txt" 1e-005 8e-006 6e-006 4e-006 2e-006 Control Electromechanical MoC Interfaces Heterogeneous Models of Computation (MoC) Single formalism for representing different models Deep conceptual understanding Ptolemy [Lee], Rugby [Jantsch] 6
7 Optical Heterogeneous SoC Specification & Validation Control Mechanical Heterogeneous execution models Multiple environments Taking into account implementation aspects Application specific efficient libraries LEOM [O Connors[ Connors] Pittsburgh [Levitan[ Levitan] Global execution models TIMA [Jerraya & Kriaa] Ecole Polytech Montreal Interfaces for Execution Models Adaptation 7
8 e-006 "chatoyant/w f4.txt" -4e-006-2e-006 1e-005 6e-006 8e-006 Key Features for Next Specification & Validation Tools Homogeneous environment facilitating cooperation between different teams Enabling easy specification, automatic generation for simulation interfaces Taking into account implementation choices Exploiting powerful existing tools (Simulink( Simulink,, SystemC, ) Based on a single well defined formalism for domain interaction Control Optical -1e-005-8e-006-6e-006-4e-006-2e e-0064e-0066e-0068e-0061e-005-1e-005-8e e-006 4e-006 Mechanical 8
9 Heterogeneity example - Continuous vs. Discret - Control t Discrete Model Mechanical t Continuous Model Simulation Step Synchronization State Event 9
10 Challenges for Accurate Global Execution Detection of state events generated by the continuous simulator Detection of the next event of the discrete simulator (scheduled event) Detection of the end of the discrete simulation cycle and the time step sending 10
11 Generic Architecture for Continuous/Discrete Simulation Discrete model Discrete simulator Continuous model Continuous simulator Détection d'événements Détection fin du cycle et Synchronization layer Synchronization Détection d'événements layer Cosimulation envoi du temps Changement de contexte interface Communication layer Communication layer Cosimulation bus 11
12 Generic Architecture for Continuous/Discrete Simulation Discrete State events detection End of discrete sim. cycle detection Context switch Communication layer Continuous Indication of state events and time sending Events detection Context switch Communication layer Cosimulation interface Cosimulation bus 12
13 First results - Continuous/Discrete simulation - SystemC/Simulink accurate simulation Easy integration, generic library elements Systemc Simulink 13
14 Performances analysis Inter-Simulators Communication overhead 20% of the total simulation time Overhead caused by the Simulink integration step adjustment max. 5% of total simulation time SystemC Synchronization overhead max. 0.2% of the total simulation time 14
15 Conclusions SoC drivers for multi-technology integration New CAD tools for design exploration are required Global specification and validation are important challenges First prototype for electro-mechanical systems Continuous/discrete integration Simulink and SystemC integration 15
Methodology for Efficient Design of Continuous/Discrete Co-Simulation Tool
Methodology for Efficient Design of Continuous/Discrete Co-Simulation Tool, H. Boucheneb, L. Gheorghe, F. Bouchimma Ecole Polytechnique de Montréal Tel : (514) 340 4711 ext 5434 Fax: (514) 340 3240 Email
More informationA Formalization of Global Simulation Models for Continuous/Discrete Systems
A Formalization of Global Simulation Models for Continuous/Discrete Systems L. Gheorghe, F. Bouchhima, G. Nicolescu, H. Boucheneb Ecole Polytechnique Montréal luiza.gheorghe@polymtl.ca Keywords: Co-Simulation,
More informationHardware/Software Co-design
Hardware/Software Co-design Zebo Peng, Department of Computer and Information Science (IDA) Linköping University Course page: http://www.ida.liu.se/~petel/codesign/ 1 of 52 Lecture 1/2: Outline : an Introduction
More informationIntegrated Workflow to Implement Embedded Software and FPGA Designs on the Xilinx Zynq Platform Puneet Kumar Senior Team Lead - SPC
Integrated Workflow to Implement Embedded Software and FPGA Designs on the Xilinx Zynq Platform Puneet Kumar Senior Team Lead - SPC 2012 The MathWorks, Inc. 1 Agenda Integrated Hardware / Software Top
More informationApplication of Multi-domain and Multi-language Cosimulation to an Optical MEM Switch Design
Application of Multi-domain and Multi-language Cosimulation to an Optical MEM Switch Design Abstract This paper presents the applicability of a cosimulation methodology based on an object-oriented simulation
More informationMATLAB/Simulink 기반의프로그래머블 SoC 설계및검증
MATLAB/Simulink 기반의프로그래머블 SoC 설계및검증 이웅재부장 Application Engineering Group 2014 The MathWorks, Inc. 1 Agenda Introduction ZYNQ Design Process Model-Based Design Workflow Prototyping and Verification Processor
More informationModeling and Simulation of System-on. Platorms. Politecnico di Milano. Donatella Sciuto. Piazza Leonardo da Vinci 32, 20131, Milano
Modeling and Simulation of System-on on-chip Platorms Donatella Sciuto 10/01/2007 Politecnico di Milano Dipartimento di Elettronica e Informazione Piazza Leonardo da Vinci 32, 20131, Milano Key SoC Market
More informationCodesign Framework. Parts of this lecture are borrowed from lectures of Johan Lilius of TUCS and ASV/LL of UC Berkeley available in their web.
Codesign Framework Parts of this lecture are borrowed from lectures of Johan Lilius of TUCS and ASV/LL of UC Berkeley available in their web. Embedded Processor Types General Purpose Expensive, requires
More informationHardware Software Codesign of Embedded Systems
Hardware Software Codesign of Embedded Systems Rabi Mahapatra Texas A&M University Today s topics Course Organization Introduction to HS-CODES Codesign Motivation Some Issues on Codesign of Embedded System
More informationOutline. SLD challenges Platform Based Design (PBD) Leveraging state of the art CAD Metropolis. Case study: Wireless Sensor Network
By Alberto Puggelli Outline SLD challenges Platform Based Design (PBD) Case study: Wireless Sensor Network Leveraging state of the art CAD Metropolis Case study: JPEG Encoder SLD Challenge Establish a
More informationHardware-Software Co-Design and Prototyping on SoC FPGAs Puneet Kumar Prateek Sikka Application Engineering Team
Hardware-Software Co-Design and Prototyping on SoC FPGAs Puneet Kumar Prateek Sikka Application Engineering Team 2015 The MathWorks, Inc. 1 Agenda Integrated Hardware / Software Top down Workflow for SoC
More informationLong Term Trends for Embedded System Design
Long Term Trends for Embedded System Design Ahmed Amine JERRAYA Laboratoire TIMA, 46 Avenue Félix Viallet, 38031 Grenoble CEDEX, France Email: Ahmed.Jerraya@imag.fr Abstract. An embedded system is an application
More informationA VARIETY OF ICS ARE POSSIBLE DESIGNING FPGAS & ASICS. APPLICATIONS MAY USE STANDARD ICs or FPGAs/ASICs FAB FOUNDRIES COST BILLIONS
architecture behavior of control is if left_paddle then n_state
More informationSystem-on-Chip. 4l1 Springer. Embedded Software Design and Programming of Multiprocessor. Simulink and SystemC. Case Studies
Katalin Popovici Frederic Rousseau Ahmed A. Jerraya Marilyn Wolf Embedded Software Design and Programming of Multiprocessor System-on-Chip Simulink and SystemC Case Studies 4l1 Springer Contents 1 Embedded
More informationCOMPLEX EMBEDDED SYSTEMS
COMPLEX EMBEDDED SYSTEMS Embedded System Design and Architectures Summer Semester 2012 System and Software Engineering Prof. Dr.-Ing. Armin Zimmermann Contents System Design Phases Architecture of Embedded
More informationTKT-1527 Digital System Design Issues Tero Arpinen. Introduction to SoC modeling and Models of Computation
TKT-1527 Digital System Design Issues Tero Arpinen Introduction to SoC modeling and Models of Computation 1 Reference material A. Jantsch and I. Sander, Models of computation and languages for embedded
More informationHeterogeneous systems co-simulation: a model-driven approach based on SysML State Machines and Simulink
Heterogeneous systems co-simulation: a model-driven approach based on SysML State Machines and Simulink Massimo Bombino 1 Matthew Hause 2 Patrizia Scandurra 3 1 Atego, Peschiera Borromeo (MI), Italy -
More informationHigh-Level Simulations of On-Chip Networks
High-Level Simulations of On-Chip Networks Claas Cornelius, Frank Sill, Dirk Timmermann 9th EUROMICRO Conference on Digital System Design (DSD) - Architectures, Methods and Tools - University of Rostock
More informationISSN Vol.04,Issue.01, January-2016, Pages:
WWW.IJITECH.ORG ISSN 2321-8665 Vol.04,Issue.01, January-2016, Pages:0077-0082 Implementation of Data Encoding and Decoding Techniques for Energy Consumption Reduction in NoC GORANTLA CHAITHANYA 1, VENKATA
More informationParag Choudhary Engineering Architect
Parag Choudhary Engineering Architect Agenda Overview of Design Trends & Designer Challenges PCB Virtual Prototyping in PSpice Simulator extensions for Models and Abstraction levels Examples of a coding
More informationCosimulation of ITRON-Based Embedded Software with SystemC
Cosimulation of ITRON-Based Embedded Software with SystemC Shin-ichiro Chikada, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada Graduate School of Information Science, Nagoya University Information Technology
More informationSystem Design and Methodology/ Embedded Systems Design (Modeling and Design of Embedded Systems)
Design&Methodologies Fö 1&2-1 Design&Methodologies Fö 1&2-2 Course Information Design and Methodology/ Embedded s Design (Modeling and Design of Embedded s) TDTS07/TDDI08 Web page: http://www.ida.liu.se/~tdts07
More informationHardware Software Codesign of Embedded System
Hardware Software Codesign of Embedded System CPSC489-501 Rabi Mahapatra Mahapatra - Texas A&M - Fall 00 1 Today s topics Course Organization Introduction to HS-CODES Codesign Motivation Some Issues on
More informationMaking the Most of your MATLAB Models to Improve Verification
Making the Most of your MATLAB Models to Improve Verification Verification Futures 2016 Graham Reith Industry Manager: Communications, Electronics & Semiconductors Graham.Reith@mathworks.co.uk 2015 The
More informationArchitecture choices. Functional specifications. expensive loop (in time and cost) Hardware and Software partitioning. Hardware synthesis
Introduction of co-simulation in the design cycle of the real- control for electrical systems R.RUELLAND, J.C.HAPIOT, G.GATEAU Laboratoire d'electrotechnique et d'electronique Industrielle Unité Mixte
More informationEarly Performance-Cost Estimation of Application-Specific Data Path Pipelining
Early Performance-Cost Estimation of Application-Specific Data Path Pipelining Jelena Trajkovic Computer Science Department École Polytechnique de Montréal, Canada Email: jelena.trajkovic@polymtl.ca Daniel
More informationHardware Description Languages. Introduction to VHDL
Hardware Description Languages Introduction to VHDL 1 What does VHDL stand for? VHSIC (= Very High Speed Integrated Circuit) Hardware Description Language 2 Others HDL VHDL IEEE Std 1076-1993 Verilog IEEE
More informationSystem Level Design with IBM PowerPC Models
September 2005 System Level Design with IBM PowerPC Models A view of system level design SLE-m3 The System-Level Challenges Verification escapes cost design success There is a 45% chance of committing
More informationDISTRIBUTED CO-SIMULATION TOOL. F.Hessel, P.Le Marrec, C.A.Valderrama, M.Romdhani, A.A.Jerraya
1 MCI MULTILANGUAGE DISTRIBUTED CO-SIMULATION TOOL F.Hessel, P.Le Marrec, C.A.Valderrama, M.Romdhani, A.A.Jerraya System-Level Synthesis Group TIMA Laboratory Grenoble, France Abstract Nowadays the design
More informationfakultät für informatik informatik 12 technische universität dortmund Data flow models Peter Marwedel TU Dortmund, Informatik /10/08
12 Data flow models Peter Marwedel TU Dortmund, Informatik 12 2009/10/08 Graphics: Alexandra Nolte, Gesine Marwedel, 2003 Models of computation considered in this course Communication/ local computations
More informationDesign Verification Lecture 01
M. Hsiao 1 Design Verification Lecture 01 Course Title: Verification of Digital Systems Professor: Michael Hsiao (355 Durham) Prerequisites: Digital Logic Design, C/C++ Programming, Data Structures, Computer
More informationCosimulation II. Cosimulation Approaches
Cosimulation II Cosimulation Approaches How to cosimulate? How to simulate hardware components of a mixed hardware-software system within a unified environment? This includes simulation of the hardware
More informationCosimulation II. How to cosimulate?
Cosimulation II Cosimulation Approaches Mahapatra-Texas A&M-Fall 00 1 How to cosimulate? How to simulate hardware components of a mixed hardware-software system within a unified environment? This includes
More informationDesign and Verification of FPGA Applications
Design and Verification of FPGA Applications Giuseppe Ridinò Paola Vallauri MathWorks giuseppe.ridino@mathworks.it paola.vallauri@mathworks.it Torino, 19 Maggio 2016, INAF 2016 The MathWorks, Inc. 1 Agenda
More informationEEL 5722C Field-Programmable Gate Array Design
EEL 5722C Field-Programmable Gate Array Design Lecture 19: Hardware-Software Co-Simulation* Prof. Mingjie Lin * Rabi Mahapatra, CpSc489 1 How to cosimulate? How to simulate hardware components of a mixed
More informationModelling and Simulation Made Easy with Simulink Tiffany Liang Application Engineer MathWorks
Modelling and Simulation Made Easy with Simulink Tiffany Liang Application Engineer MathWorks 2015 The MathWorks, Inc. 1 What will you learn in this presentation? For those who are not familiar with Simulink
More informationHardware Design and Simulation for Verification
Hardware Design and Simulation for Verification by N. Bombieri, F. Fummi, and G. Pravadelli Universit`a di Verona, Italy (in M. Bernardo and A. Cimatti Eds., Formal Methods for Hardware Verification, Lecture
More informationfakultät für informatik informatik 12 technische universität dortmund Modeling levels Peter Marwedel TU Dortmund, Informatik /11/07
12 Peter Marwedel TU Dortmund, Informatik 12 2009/11/07 Graphics: Alexandra Nolte, Gesine Marwedel, 2003 Modeling levels Levels of hardware modeling Possible set of levels (others exist) System level Algorithmic
More informationSystem on Chip (SoC) Design
System on Chip (SoC) Design Moore s Law and Technology Scaling the performance of an IC, including the number components on it, doubles every 18-24 months with the same chip price... - Gordon Moore - 1960
More informationComparison of models. Peter Marwedel Informatik 12, TU Dortmund, Germany 2010/11/07. technische universität dortmund
12 Comparison of models Peter Marwedel Informatik 12, TU Dortmund, Germany Graphics: Alexandra Nolte, Gesine Marwedel, 2003 These slides use Microsoft clip arts. Microsoft copyright restrictions apply.
More informationThe Use Of Virtual Platforms In MP-SoC Design. Eshel Haritan, VP Engineering CoWare Inc. MPSoC 2006
The Use Of Virtual Platforms In MP-SoC Design Eshel Haritan, VP Engineering CoWare Inc. MPSoC 2006 1 MPSoC Is MP SoC design happening? Why? Consumer Electronics Complexity Cost of ASIC Increased SW Content
More informationCo-Design of Many-Accelerator Heterogeneous Systems Exploiting Virtual Platforms. SAMOS XIV July 14-17,
Co-Design of Many-Accelerator Heterogeneous Systems Exploiting Virtual Platforms SAMOS XIV July 14-17, 2014 1 Outline Introduction + Motivation Design requirements for many-accelerator SoCs Design problems
More informationSystem level modelling with open source tools
System level modelling with open source tools Mikkel Koefoed Jakobsen (mkoe@imm.dtu.dk) Jan Madsen (jan@imm.dtu.dk) Seyed Hosein Attarzadeh Niaki (shan2@kth.se) Ingo Sander (ingo@kth.se) Jan Hansen (jan@real-ear.com)
More informationA Unified HW/SW Interface Model to Remove Discontinuities between HW and SW Design
A Unified HW/SW Interface Model to Remove Discontinuities between HW and SW Design Ahmed Amine JERRAYA EPFL November 2005 TIMA Laboratory 46 Avenue Felix Viallet 38031 Grenoble CEDEX, France Email: Ahmed.Jerraya@imag.fr
More informationSDL. Jian-Jia Chen (slides are based on Peter Marwedel) TU Dortmund, Informatik 年 10 月 18 日. technische universität dortmund
12 SDL Jian-Jia Chen (slides are based on Peter Marwedel) TU Dortmund, Informatik 12 2017 年 10 月 18 日 Springer, 2010 These slides use Microsoft clip arts. Microsoft copyright restrictions apply. Models
More informationNetwork-on-Chip Architecture
Multiple Processor Systems(CMPE-655) Network-on-Chip Architecture Performance aspect and Firefly network architecture By Siva Shankar Chandrasekaran and SreeGowri Shankar Agenda (Enhancing performance)
More informationRTOS-Centric Hardware/Software Cosimulator for Embedded System Design
RTOS-Centric Hardware/Software Cosimulator for Embedded System Design Shinya Honda Takayuki Wakabayashi Hiroyuki Tomiyama Hiroaki Takada Department of Information and Computer Science Toyohashi University
More informationHardware Description Languages & System Description Languages Properties
Hardware Description Languages & System Description Languages Properties There is a need for executable specification language that is capable of capturing the functionality of the system in a machine-readable
More informationTIMA Lab. Research Reports
ISSN 1292-862 TIMA Lab. Research Reports TIMA Laboratory, 46 avenue Félix Viallet, 38000 Grenoble France Application-Specific Multiprocessor Systems-on-Chip Ahmed Amine Jerraya, Amer Baghdadi, Wander Cesário,
More informationAbbas El Gamal. Joint work with: Mingjie Lin, Yi-Chang Lu, Simon Wong Work partially supported by DARPA 3D-IC program. Stanford University
Abbas El Gamal Joint work with: Mingjie Lin, Yi-Chang Lu, Simon Wong Work partially supported by DARPA 3D-IC program Stanford University Chip stacking Vertical interconnect density < 20/mm Wafer Stacking
More informationIntegration-aware Modeling, Simulation and Design Techniques for Smart Electronic Systems
Scuola di Dottorato Ph.D. in Control and Computer Engineering XXVII cycle Integration-aware Modeling, Simulation and Design Techniques for Smart Electronic Systems Alessandro Sassone Advisors: Prof. Enrico
More informationSingle Chip Heterogeneous Multiprocessor Design
Single Chip Heterogeneous Multiprocessor Design JoAnn M. Paul July 7, 2004 Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh, PA 15213 The Cell Phone, Circa 2010 Cell
More information[Sub Track 1-3] FPGA/ASIC 을타겟으로한알고리즘의효율적인생성방법및신기능소개
[Sub Track 1-3] FPGA/ASIC 을타겟으로한알고리즘의효율적인생성방법및신기능소개 정승혁과장 Senior Application Engineer MathWorks Korea 2015 The MathWorks, Inc. 1 Outline When FPGA, ASIC, or System-on-Chip (SoC) hardware is needed Hardware
More informationHardware/Software Partitioning for SoCs. EECE Advanced Topics in VLSI Design Spring 2009 Brad Quinton
Hardware/Software Partitioning for SoCs EECE 579 - Advanced Topics in VLSI Design Spring 2009 Brad Quinton Goals of this Lecture Automatic hardware/software partitioning is big topic... In this lecture,
More informationFSMs & message passing: SDL
12 FSMs & message passing: SDL Peter Marwedel TU Dortmund, Informatik 12 Springer, 2010 2012 年 10 月 30 日 These slides use Microsoft clip arts. Microsoft copyright restrictions apply. Models of computation
More informationThe SOCks Design Platform. Johannes Grad
The SOCks Design Platform Johannes Grad System-on-Chip (SoC) Design Combines all elements of a computer onto a single chip Microprocessor Memory Address- and Databus Periphery Application specific logic
More informationEEM870 Embedded System and Experiment Lecture 4: SoC Design Flow and Tools
EEM870 Embedded System and Experiment Lecture 4: SoC Design Flow and Tools Wen-Yen Lin, Ph.D. Department of Electrical Engineering Chang Gung University Email: wylin@mail.cgu.edu.tw March 2013 Agenda Introduction
More informationChapter 10 Objectives
Chapter 10 Topics in Embedded Systems Chapter 10 Objectives Understand the ways in which embedded systems differ from general purpose systems. Be able to describe the processes and practices of embedded
More informationHardware Description Languages & System Description Languages Properties
Hardware Description Languages & System Description Languages Properties There is a need for executable specification language that is capable of capturing the functionality of the system in a machine-readable
More informationA Heterogeneous and Distributed Co-Simulation Environment
XVII SIM - South Symposium on Microelectronics 1 A Heterogeneous and Distributed Co-Simulation Environment Alexandre Amory, Leandro Oliveira, Fernando Moraes {amory, laugusto, moraes}@inf.pucrs.br Abstract
More informationA Generic RTOS Model for Real-time Systems Simulation with SystemC
A Generic RTOS Model for Real-time Systems Simulation with SystemC R. Le Moigne, O. Pasquier, J-P. Calvez Polytech, University of Nantes, France rocco.lemoigne@polytech.univ-nantes.fr Abstract The main
More informationHardware, Software and Mechanical Cosimulation for Automotive Applications
, and Mechanical Cosimulation for Automotive Applications P. Le Marrec, C. A. Valderrama, F. Hessel, A. A. Jerraya System Level Synthesis Group, TIMA Laboratory, INPG, Grenoble M. Attia, O. Cayrol PSA
More informationAccelerating FPGA/ASIC Design and Verification
Accelerating FPGA/ASIC Design and Verification Tabrez Khan Senior Application Engineer Vidya Viswanathan Application Engineer 2015 The MathWorks, Inc. 1 Agenda Challeges with Traditional Implementation
More informationCourse Outcome of M.E (ECE)
Course Outcome of M.E (ECE) PEC108/109: EMBEDDED SYSTEMS DESIGN 1. Recognize the Embedded system and its programming, Embedded Systems on a Chip (SoC) and the use of VLSI designed circuits. 2. Identify
More informationHardware and Software Co-Design for Motor Control Applications
Hardware and Software Co-Design for Motor Control Applications Jonas Rutström Application Engineering 2015 The MathWorks, Inc. 1 Masterclass vs. Presentation? 2 What s a SoC? 3 What s a SoC? When we refer
More informationHVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips
on introducing a new design paradigm HVSoCs: A Framework for Rapid Prototyping of 3-D Hybrid Virtual System-on-Chips D. Diamantopoulos, K. Siozios, E. Sotiriou-Xanthopoulos, G. Economakos and D. Soudris
More informationIntroduction to System-on-Chip
Introduction to System-on-Chip COE838: Systems-on-Chip Design http://www.ee.ryerson.ca/~courses/coe838/ Dr. Gul N. Khan http://www.ee.ryerson.ca/~gnkhan Electrical and Computer Engineering Ryerson University
More informationHardware, Software and Mechanical Cosimulation for Automotive Applications
Hardware, Software and Mechanical Cosimulation for Automotive Applications P. Le Marrec, C.A. Valderrama, F. Hessel, A.A. Jerraya TIMA Laboratory 46 Avenue Felix Viallet 38031 Grenoble France fphilippe.lemarrec,
More informationA 1-GHz Configurable Processor Core MeP-h1
A 1-GHz Configurable Processor Core MeP-h1 Takashi Miyamori, Takanori Tamai, and Masato Uchiyama SoC Research & Development Center, TOSHIBA Corporation Outline Background Pipeline Structure Bus Interface
More informationIntroduction. Definition. What is an embedded system? What are embedded systems? Challenges in embedded computing system design. Design methodologies.
Introduction What are embedded systems? Challenges in embedded computing system design. Design methodologies. What is an embedded system? Communication Avionics Automobile Consumer Electronics Office Equipment
More informationHardware Modelling. Design Flow Overview. ECS Group, TU Wien
Hardware Modelling Design Flow Overview ECS Group, TU Wien 1 Outline Difference: Hardware vs. Software Design Flow Steps Specification Realisation Verification FPGA Design Flow 2 Hardware vs. Software:
More informationTIMA Lab. Research Reports
ISSN 1292-862 TIMA Lab. Research Reports TIMA Laboratory, 46 avenue Félix Viallet, 38000 Grenoble France Session 1.2 - Hop Topics for SoC Design Asynchronous System Design Prof. Marc RENAUDIN TIMA, Grenoble,
More informationECE 1160/2160 Embedded Systems Design. Midterm Review. Wei Gao. ECE 1160/2160 Embedded Systems Design
ECE 1160/2160 Embedded Systems Design Midterm Review Wei Gao ECE 1160/2160 Embedded Systems Design 1 Midterm Exam When: next Monday (10/16) 4:30-5:45pm Where: Benedum G26 15% of your final grade What about:
More informationNoC Round Table / ESA Sep Asynchronous Three Dimensional Networks on. on Chip. Abbas Sheibanyrad
NoC Round Table / ESA Sep. 2009 Asynchronous Three Dimensional Networks on on Chip Frédéric ric PétrotP Outline Three Dimensional Integration Clock Distribution and GALS Paradigm Contribution of the Third
More informationNavigating the RTL to System Continuum
Navigating the RTL to System Continuum Calypto Design Systems, Inc. www.calypto.com Copyright 2005 Calypto Design Systems, Inc. - 1 - The rapidly evolving semiconductor industry has always relied on innovation
More informationMixed Signal Verification Transistor to SoC
Mixed Signal Verification Transistor to SoC Martin Vlach Chief Technologist AMS July 2014 Agenda AMS Verification Landscape Verification vs. Design Issues in AMS Verification Modeling Summary 2 AMS VERIFICATION
More informationAn Inter-core Communication Enabled Multi-core Simulator Based on SimpleScalar
An Inter-core Communication Enabled Multi-core Simulator Based on SimpleScalar Rongrong Zhong, Yongxin Zhu, Weiwei Chen, Mingliang Lin Shanghai Jiao Tong University {zhongrongrong, zhuyongxin, chenweiwei,
More informationChallenges. Shift to Reuse Strategy Higher Level of Abstractions Software!!!
Challenges Shift to Reuse Strategy Higher Level of Abstractions Software!!! 1 PERCENT OF TRANSISTORS WITHIN EMBEDDED IP (EXCLUDES MEMORY) 100 Random Logic Transistors Transistors (%) Transistors Within
More informationInterconnect Delay Aware RTL Verilog Bus Architecture Generation for an SoC
Interconnect Delay Aware RTL Verilog Bus Architecture Generation for an SoC Kyeong Ryu, Alexandru Talpasanu, Vincent Mooney and Jeffrey Davis School of Electrical and Computer Engineering Georgia Institute
More informationA Framework for the Design of Mixed-Signal Systems with Polymorphic Signals
A Framework for the Design of Mixed-Signal Systems with Polymorphic Signals Rüdiger Schroll *1) Wilhelm Heupke *1) Klaus Waldschmidt *1) Christoph Grimm *2) *1) Technische Informatik *2) Institut für Mikroelektronische
More informationFPGA based Design of Low Power Reconfigurable Router for Network on Chip (NoC)
FPGA based Design of Low Power Reconfigurable Router for Network on Chip (NoC) D.Udhayasheela, pg student [Communication system],dept.ofece,,as-salam engineering and technology, N.MageshwariAssistant Professor
More informationA Reconfigurable Crossbar Switch with Adaptive Bandwidth Control for Networks-on
A Reconfigurable Crossbar Switch with Adaptive Bandwidth Control for Networks-on on-chip Donghyun Kim, Kangmin Lee, Se-joong Lee and Hoi-Jun Yoo Semiconductor System Laboratory, Dept. of EECS, Korea Advanced
More informationDesign and Verification of FPGA and ASIC Applications Graham Reith MathWorks
Design and Verification of FPGA and ASIC Applications Graham Reith MathWorks 2014 The MathWorks, Inc. 1 Agenda -Based Design for FPGA and ASIC Generating HDL Code from MATLAB and Simulink For prototyping
More informationExploration of Cache Coherent CPU- FPGA Heterogeneous System
Exploration of Cache Coherent CPU- FPGA Heterogeneous System Wei Zhang Department of Electronic and Computer Engineering Hong Kong University of Science and Technology 1 Outline ointroduction to FPGA-based
More informationA SystemC HDL Cosimulation Framework
A SystemC HDL Cosimulation Framework Christian Bernard, CEA/LETI Nicolas Tribié, CEA/LETI Marcello Coppolla, ST/AST A systemc HDL cosimulation framework 1 Agenda Motivatio Cosimulation usages Framework
More informationVHDL-BASED SIMULATION ENVIRONMENT FOR PROTEO NOC
VHDL-BASED SIMULATION ENVIRONMENT FOR PROTEO NOC David Sigüenza-Tortosa, IDCS-Tampere University of Technology, Finland, siguenzd@cc.tut.fi Jari Nurmi, IDCS-Tampere University of Technology, Finland, jari.nurmi@tut.fi
More informationPart 2: Principles for a System-Level Design Methodology
Part 2: Principles for a System-Level Design Methodology Separation of Concerns: Function versus Architecture Platform-based Design 1 Design Effort vs. System Design Value Function Level of Abstraction
More informationA framework for automatic generation of audio processing applications on a dual-core system
A framework for automatic generation of audio processing applications on a dual-core system Etienne Cornu, Tina Soltani and Julie Johnson etienne_cornu@amis.com, tina_soltani@amis.com, julie_johnson@amis.com
More informationCOE 561 Digital System Design & Synthesis Introduction
1 COE 561 Digital System Design & Synthesis Introduction Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Outline Course Topics Microelectronics Design
More informationSoC Design for the New Millennium Daniel D. Gajski
SoC Design for the New Millennium Daniel D. Gajski Center for Embedded Computer Systems University of California, Irvine www.cecs.uci.edu/~gajski Outline System gap Design flow Model algebra System environment
More informationCo-Simulation of Functional SystemC TLM Models with Power/Thermal Solvers
Author manuscript, published in "Virtual Prototyping of Parallel and Embedded Systems (VIPES), Boston : United States (2013)" Co-Simulation of Functional SystemC TLM Models with Power/Thermal Solvers Tayeb
More informationCycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs Jürgen Schnerr 1, Oliver Bringmann 1, and Wolfgang Rosenstiel 1,2 1 FZI Forschungszentrum Informatik Haid-und-Neu-Str.
More informationFlexRay The Hardware View
A White Paper Presented by IPextreme FlexRay The Hardware View Stefan Schmechtig / Jens Kjelsbak February 2006 FlexRay is an upcoming networking standard being established to raise the data rate, reliability,
More informationIntro to High Level Design with SystemC
Intro to High Level Design with SystemC Aim To introduce SystemC, and its associated Design Methodology Date 26th March 2001 Presented By Alan Fitch Designer Challenges Design complexity System on Chip
More informationEECS Dept., University of California at Berkeley. Berkeley Wireless Research Center Tel: (510)
A V Heterogeneous Reconfigurable Processor IC for Baseband Wireless Applications Hui Zhang, Vandana Prabhu, Varghese George, Marlene Wan, Martin Benes, Arthur Abnous, and Jan M. Rabaey EECS Dept., University
More informationTHE EUROPEAN DESIGN AND TEST CONFERENCE 1995 Paris,France 6-9 March 1995
THE EUROPEAN DESIGN AND TEST CONFERENCE 1995 Paris,France 6-9 March 1995 A UNIFIED MODEL FOR CO-SIMULATION AND CO-SYNTHESIS OF MIXED HARDWARE/SOFTWARE SYSTEMS Authors: C. A. Valderrama, A. Changuel, P.V.
More informationSpecifications and Modeling
12 Specifications and Modeling Peter Marwedel TU Dortmund, Informatik 12 Springer, 2010 2012 年 10 月 17 日 These slides use Microsoft clip arts. Microsoft copyright restrictions apply. Hypothetical design
More informationApplications, Processing and Integration Options for High Dielectric Constant Multi-Layer Thin-Film Barium Strontium Titanate (BST) Capacitors
Applications, Processing and Integration Options for High Dielectric Constant Multi-Layer Thin-Film Barium Strontium Titanate (BST) Capacitors Agenda Introduction What is BST? Unique Characteristics of
More informationSimulation, prototyping and verification of standards-based wireless communications
Simulation, prototyping and verification of standards-based wireless communications Colin McGuire, Neil MacEwen 2015 The MathWorks, Inc. 1 Real Time LTE Cell Scanner with MATLAB and Simulink 2 Real time
More informationBuilding Whole Systems: an Overview
1 (29) Building Whole Systems: an Overview In this lecture: System specification, design, and synthesis Hardware/software co-design Work tips Design challenges and trade-offs 2 (29) Ideal flow (Informal)
More information