CS 4120 Hardware Description Languages and Synthesis Homework 6: Introduction to Cadence Silicon Ensemble

Transcription

1 CS 4120 Hardware Description Languages and Synthesis Homework 6: Introduction to Cadence Silicon Ensemble 0. Introduction In this homework, you will be introduced to a Place and Route tool called Silicon Ensemble This tool can create a final layout from a schematic or a HDL file. All parts/gates used in the design must be in a pre-defined library that is developed to work with Silicon Ensemble. This tool can accept various constraints such as timing and area. The tool will then try to meet the constraints that are given to it. In this homework the basics of place and route will be covered 1. Silicon Ensemble Setup 1.1 The first thing that you need to do is make another directory for all of your Silicon Ensemble designs. Go to your home directory and type the following to make a new directory: mkdir silicone 1.2 After making the directory you will need to copy some files into the directory, so that you can do this homework. Copy the following files into your silicone directory. tsmc25_4lm-cic.lef copy from /theda21_1/lib25spdm/cic_cbdk25_v1/core/lef/tsmc25_4lm-cic.lef tsmc25.v copy from /theda21_1/lib25spdm/cic_cbdk25_v1/core/verilog/tsmc25.v HW6.v Download from the course website..sysnopsys_dc.setup copy from /usr/local/myscript/synopsys_dc.setup Setup your environment Execute following command: source /usr/local/myscript/cadtool.cshrc Copyright 1999, Charlie Boecker Permission to duplicate and distribute this document is granted for sole educational purpose without any commercial advantage, provided this copyright message is accompanied in all the duplicates distributed. All other rights reserved. All Cadence s tools referred are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks belong to their respective owners.

2 2. Preparing the Verilog Code Now, open HW6.v. This file is the synthesis result of the structural style 4-bit multiplier we once created in homework 2.Note that the design consists of only the basic cells defined in TSMC25.v and the library file TSMC25.db used by design_analyzer. We will do the placement and routing for HW6.v now. 3. Importing Verilog and LEF Files into Silicon Ensemble 3.1 To start Silicon Ensemble you need to type the following in your silicone directory. sesi m=48 & This should bring up a Welcome window to Silicon Ensemble, which will go away after a while and then Silicon Ensemble will start up after about 30 seconds or so. 3.2 Once Silicon Ensemble is up, acquaint yourself with the different menus at the top, the quick buttons on the lower-left, the select/view options in the upper-left, and the application output at the bottom of the window. The application output will give you feedback about what is going on similar to the CIW in Cadence. 3.3 Choose Edit Environment. Find INPUT.LEF.DEF.NAMEMAP variable and set it to be TRUE. 3.4 The first step is getting the design into Silicon Ensemble. To do this choose File Import LEF. The Import LEF window will pop up. There should be only one choice in this window tsmc25_4lmcic.lef. Double click it. There should be a bunch of output, but after it is complete there should be no errors or warnings. If there are errors, contact your TA. You now have the library information imported into Silicon Ensemble. 3.5 The next step is to get the connectivity information into Silicon Ensemble. To do this, choose File Import Verilog. The Import Verilog window will pop up. Remember that we need two verilog files one for the library and one for the design. In the Verilog Source Files field enter the following tsmc25.v HW6.v.Here,tsmc25.v is the library file and HW6.v is the design file. In the Verilog Top Module field fill in the following mul_4bit. The rest of the form should be ok, so click on OK. After it is complete, you shouldn t have any errors. Now everything that is needed is in Silicon Ensemble.

3 4. Initializing Floorplan / Placing IOs 4.1 The cells that were in the schematic should be in Silicon Ensemble now. Fit the design to the window by pressing the icon in the middle of all of the arrows on the left. After you do this, you will not see anything. The reason is because Silicon Ensemble doesn t know where to put the cells yet. 4.2 Now you can initialize the floorplan by choosing Floorplan Initialize Floorplan. An Initialize Floorplan window will pop up. There are a lot of fields in the window. To find out what the different fields in the form are click on the Help button in the lower-right corner of the window. You will probably want to know what each of the fields is for. Set the form so that the fields are filled in like the following: Left/Right 40 microns Top/Bottom 40 microns Row Util. 70% Row Spacing 2 tracks Block Halo per side 20 microns Also, make sure that the Aspect Ratio option is selected in the Die Size Constraint and the Aspect Ratio is 1.0. The Flip Every Other Row and Abut Rows options should also be on. You also need to set some variables, so that Silicon Ensemble will be able to place and route our circuit correctly. Click on the Variables button in the lower-right hand corner. An Environment Variables window will open. You can use Help to find more about this.for the time being, the default setting are ok. After making sure that everything is correct click on OK. You should see red rows appear in your design. Your cells will be placed inside these rows later. 4.3 Now that the floorplan is initialized, the I/O Pins need to be placed. This is done by choosing Place IOs. A Place IO window will open. For now, just choose the random option for the placement of the pins. 5. Planning Power / Placing Cells / Compacting Floorplan 5.1 After the IOs are placed, the power routing scheme needs to be developed. To plan the power lines choose Route Plan Power. A Plan Power toolbox will open. There should also be a yellow box enclosing the three rows in the middle. If you can not see this, click the redraw icon. This is the path that the tool plans to route the power lines. You can change this by deleting/adding power paths. For this design, just leave the default power paths.

4 5.2 To make the power paths click on the Add Rings button. A PP Add Rings window will open. In the window fill in the form so that the following fields are set to the values given below: Preferred Dir Horizontal Metal1 Preferred Dir Vertical Metal2 Core Ring Width (Horizontal) 10.8 microns Core Ring Width (Vertical) 10.8 microns Core Ring space(from core, Horizontal) 2.16 microns Core Ring space(from core, Vertical) 2.16 microns Block Ring Width (Horizontal) 0 Block Ring Width (Vertical) 0 You should try to understand what each of the field represents. Again click on Help to find out about the commands and the fields/options associated with it. After, the values are entered click on OK. You should see a couple of blue and red rings encircle the rows. You are done planning the power, so click on Close in the Plan Power toolbox. 5.3 After the power routing is planned, the cells need to be placed inside the rows. Choose Place Cells. A Place Cells window will open. There are many options to choose from. For now, we will just use the Pin Placement option, which just makes sure that the circuit is logically connected right and doesn t place any emphasis on the delay of the cell. Click on Help to learn about the options that are available for the placement of cells. After you are done reading about the different options, close the Help window and click OK in the Place Cells window. You should be able to see the cells that are placed in the rows after this is done. If you are not able to see them make sure that they are visible in your Object Selection palette in the upper-left corner. In fact, you should probably make sure everything is visible. This will let you see everything that is happening in your design. 5.4 The next thing to do is to compact the design, so that some of the space can be removed and the design can be reduced in size. Choose Floorplan Compact Floorplan (Vsize). A Compact Floorplan (Vsize) window opens. In the window click Variables. An Environment Variables window will open. In the window search for the VSIZE.ITERATIONS variable and set it to 2. This is the number of iterations that you want the tool to make when compacting your floorplan. Search for the VSIZE.UPDATE.CONGESTION.MAP variable and set it to true. This tells the tool to update the congestion map, which you or the tool can use to decide on how to route or change the routing of the design. After both of these variables are set, click OK in the Environment Variables window. Then

5 click OK in the Compact Floorplan (Vsize) window. You should see your design change size. Your design is now ready to be routed. Before routing save your design by choosing File Save As. A Save As window will open. In the window everything should be ok, except change the Design Name field to mul4bit_vsize and click OK. The homework mentioned the congestion map above. The congestion map is a map that describes how hard the design is to route in a certain location. Depending on the color of the line that the congestion map draws the congestion could be high red or low blue. To display only the congestion map, you can change the display options by clicking the Display Options icon on the left by the Redraw icon. A Display Options window will appear. In the window turn off everything except the congestion map, remember what was set though, so you can restore it. After turning off all the displays except the congestion map, click on OK. Now you should see the congestion map (may not be present because of such a small design). This is a representation of how tough it will be to route the design. Most of the lines should be either blue or green, which means the router should have no problem. After done looking at the congestion map, restore the display options to its original state. 6. Routing the Design 6.1 Now your design may be smaller than it was before. Depending on how tough the design is to route, it may even get bigger. The cells in the design are not going to move from now on, so we can route the power lines to the cells. Choose Route Connect Ring and Connect Ring toolbox appears. You should see vdd! and gnd! in the Nets field. Disable block option.in the Follow Pins Pin Width field, fill in Click on OK. You should see the vdd! and gnd! pins connected to the vdd! and gnd! rings that are enclosing the cells. 6.2 The design is now connected to vdd! and gnd!. The next step is to route the cells together, so that they are logically the same as the schematic. Choose Route Global Route. A Global Route window will open. All the defaults in the window should be ok for this design. Again, if you want to know what all the options are for, click on Help and it will tell you. Click on OK. The output window will tell you what is going on. This step just does an initial routing of the cell. It tries to balance the congestion through the cell, so it doesn t run into a net that isn t routable. 6.3 Next choose Route Final Route. A Final Route window will open. Make sure that the Auto Search and Repair option and the All option are selected. Again, if you want to know more about final route, click the Help button. After selecting the options above, click on OK. The design should be connected now. You may not be able to see that the design is routed. If you want to zoom in click

6 on the magnification button in the lower left region of the window and make a box around the region you want to see. Save your design under the name of mul4bit_routed. 7. Print out the result Snapshot your place&route result into a.jpg file. Tips Press Print Scrn Sysrq key on your keyboard, then execute mspaint program and paste the snapshot on it. Save the snapshot into a bmp file and zip the file. PS. help message ) silicon ensemble! #" $% sesi h & ' ( The homework is due by noon, 5/1/2003. Please compress your snapshot file to zip file. Name the file as YourStudentID_hw6.zip, and it to tacs4120@nthucad.cs.nthu.edu.tw.