POWERLINK - Use Cases
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1 POWELINK - Use Cases POWELINK Use Cases in open, POWELINK compatible networks POWELINK with FPGA and Soft-CPU This case is the most common use case, it allows for an excellent POWELINK Performance and supports all outstanding POWELINK features. In this scenario a Hub-IP Core ensures low latency and low jitter in the line-structure of the network. A special component PE²MAC (POWELINK Enhanced Ethernet MAC) provides a Autoreply functionality, which basically answers Poll-equest from the MN almost instantly with the corresponding Poll-esponse. This results in an overall excellent performance and specially low jitter. In a Soft-CPU in the same FPGA the POWELINK Protocol is being managed and the customer s application is running. As a further improvement a DP-AM can be employed so the customer s sensible application runs in a additional, external CPU and the Soft-CPU only manages the POWELINK Protocol. This approach enables the customer to run his complex, sensible and often already existing design almost unchanged while the POWELINK objects are accessed as an external memory, that s located as DP-AM in the FPGA. (with PUDIn Support) POWELINK CN, ANSI-C Source Code Driver for MCU (NIOS or Microblaze) For POWELINK CN Protcolo Stack, ANSI-C Source Code POWELINK DesignTool Tool for generating fast and costeffective POWELINK applications (Controlled Nodes). POWELINK-Hub IP-Core POWELINK HUB IP - Core for XILINX or Altera FPGA, VHDL Source Code. The EPL Hub is optimized for low latency. POWELINK MAC (PE²MAC) POWELINK Enhanced Ethernet MAC IP-Core, VHDL Source Code für Xilinx or Altera FPGAs. The MAC offers extremely fast Poll esponses operating POWELINK.
2 POWELINK - Use Cases POWELINK with FPGA and external MCU This use case allows to combine the advantages of high speed / low jitter connectivity of the FPGA Ethernet access solution with the performance and the perherial components of a silicon MCU. Existing or price effective silicon MCUs with Flash/AM and the proper peripherials on-board are often good enough for reasonable POWELINK performance. They add less money and components to the BOM than the external SD-AM and serial Flash for the Soft-CPU would add. Depending on the Software-Design and the System-Load Cycle Times down to 1ms can be realised. POWELINK CN, ANSI-C Source Code Driver for MCU (STM32, Luminary, ) For POWELINK CN Protcolo Stack, ANSI-C Source Code POWELINK DesignTool Tool for generating fast and costeffective POWELINK applications (Controlled Nodes). POWELINK-Hub IP-Core POWELINK HUB IP - Core for XILINX or Altera FPGA, VHDL Source Code. The EPL Hub is optimized for low latency. POWELINK MAC (PE²MAC) POWELINK Enhanced Ethernet MAC IP-Core, VHDL Source Code für Xilinx or Altera FPGAs. The MAC offers extremely fast Poll esponses operating POWELINK.
3 POWELINK - Use Cases POWELINK with FPGA and external Linux-CPU Instead of the MCU a powerfull CPU (e.g. Arm9, i.mx) can be employed. Normally running POWELINK on Linux Systems would limit cycle time and possible jitter to values that are not acceptable for industrial applications. Combining the Linux CPU with the FPGA enables the Linux CPU at least theoretical to manage all possible cycle times and low jitter. The bottleneck is now the protocol stack that would need to run completely in the Kernel Space in Kernel-Mode to comply to POWELINK s speed requirements. Bringing large protocol libraries into the Kernel-Mode increases risks and reduces overall stability of the Linux system. Therefore port has created a Kernel-Mode POWELINK Kernel Mode Interface that runs in the Kernel Space while ports POWELINK Library runs in the User-Mode. This separation enables Linux for the industrial grade cycle times and jitter AND maintains the Linux concept of a fast Kernel-Mode Interface and a dedicated User-Mode application. POWELINK CN, ANSI-C Source Code Driver for CPU (GPL Kernel Mode Interface) For POWELINK CN Protcolo Stack, ANSI-C Source Code POWELINK DesignTool Tool for generating fast and costeffective POWELINK applications (Controlled Nodes). POWELINK-Hub IP-Core POWELINK HUB IP - Core for XILINX or Altera FPGA, VHDL Source Code. The EPL Hub is optimized for low latency. POWELINK MAC (PE²MAC) POWELINK Enhanced Ethernet MAC IP-Core, VHDL Source Code für Xilinx or Altera FPGAs. The MAC offers extremely fast Poll esponses operating POWELINK.
4 POWELINK - Use Cases POWELINK with Linux SoC A special use-case of the Linux System is the SoC (e.g. ZYNQ) Here the FPGA and a powerful Linux CPU are combined on a single chip. Here as well the advantages of the Kernel-Mode Interface and the User Mode operated POWELINK protocol stack are combined. Linux becomes enabled for the industrial grade cycle times and jitter AND Linux concept of a fast Kernel-Mode Interface and a dedicated User-Mode application is maintained. POWELINK CN, ANSI-C Source Code Driver for ZYNQ (GPL Kernel Mode Interface) For POWELINK CN Protcolo Stack, ANSI-C Source Code POWELINK DesignTool Tool for generating fast and costeffective POWELINK applications (Controlled Nodes). POWELINK-Hub IP-Core POWELINK HUB IP - Core for ZYNQ, VHDL Source Code. The EPL Hub is optimized POWELINK MAC (PE²MAC) POWELINK Enhanced Ethernet MAC IP-Core, VHDL Source Code für ZYNQ FPGAs. The MAC offers extremely fast Poll esponses operating POWELINK.
5 POWELINK - Use Cases POWELINK with TI s Sitara AM335x Port s POWELINK Protocol Library supports POWELINK on TI s versatile platform Sitara. The on-chip periphrials ICSS (Industrial Communication Sub System) with the parts PU (Programmanle eal Time Units) deliver an outstanding support for the POWELINK specific support in ()programmable) hardware. Besides POWELINK other Ethernet based fieldbusses are supported as well. Currently TI s eal Time OS Sys/BIOS is supported, Linux Support is under construction. POWELINK CN, ANSI-C Source Code Driver for Sitara (AM335x) For POWELINK CN Protcolo Stack, ANSI-C Source Code POWELINK DesignTool Tool for generating fast and costeffective POWELINK applications (Controlled Nodes).
6 POWELINK - Use Cases The following Use Cases are only suitable for applications with limited POWELINK requirements. Significant limitations in Cycle Time, Jitter and Latency apply. POWELINK with epeater-mode Switch Controller and external CPU This approach combines the price effective silicon MCUs with Flash/AM and the proper peripherials on-board with a Silicon Switch controller for provinding line structure. Some Switch controller manufacturer provide a feature calle epeater Mode, which provides lowlatency and low jitter troughout the network. This approach providing Line Structure comes with the lowest BOM cost, however shorther cycle times than 1ms are not possible. POWELINK CN, ANSI-C Source Code Driver for MCU (STM32, Luminary, ) For POWELINK CN Protcolo Stack, ANSI-C Source Code POWELINK DesignTool Tool for generating fast and costeffective POWELINK applications (Controlled Nodes). POWELINK with CPU in Star Structure This use case describes the lowest cost BOM approach utilizing the start structure topology. The POWELINK is employed on the same MCU as the application is running. This makes sense for cost sensitive applications with only medium performance requirements. A cycle time down to 1ms is possible however this depends on the software architecture. POWELINK CN, ANSI-C Source Code Driver for MCU (STM32, Luminary, ) For POWELINK CN Protcolo Stack, ANSI-C Source Code POWELINK DesignTool Tool for generating fast and costeffective POWELINK applications (Controlled Nodes).
7 POWELINK - Use Cases POWELINK available components and Tools by port = Library + Driver The POWELINK for Controlled Nodes (CNs) by port provides POWELINK functionality for devices. The consists from the POWELINK Library and the POWELINK Driver. While the Library is hardware independent, the Driver connects the Library to the specific hardware and optional to the OS. This way the Library can be used on almost any hardware platform without porting it to the new hardware platform. Only the Driver needs to be created with significantly less effort. The POWELINK can be used with Operating Systems (OS) and without running on plain hardware. Several hardware platforms are currently supported: ST9, STM32, Luminary, Am335x, NIOS and MicroBlaze. The Kernel-Mode Linux Driver for port s POWELINK enables Linux POWELINK applications for the high POWELINK performance of the Kernel-Mode solution but maintains the integrity of the system with the Library running in User-Mode. While the MCU platforms (STM32, Luminary) are able to provide cost effective, low ressource POWELINK connectivity, the FPGA solutions enables Embedded Systems for the maximum POWELINK performance. Advantages/USPs - FPGAs supported as well as MCUs and Linux Systems - Suitable for Embedded Systems with no or any OS - Suitable for high performance Linux applications o Kernel-Mode Driver o User-Mode Library - New platforms easy supported - DesignTool support - Delivery in Source Code POWELINK MAC (PE²MAC) Port s POWELINK Enhanced Ethernet MAC (PE²MAC) is a VHDL written IP-Core for Altera and Xilinx FPGAs. The Core of the PE²MAC is a set of Compare/Capture egisters that can trigger on the Poll-equest message, sent by the Managing Node (MN). Upon reception of the Poll-equest message the PE²MAC automatically responds in hardware with the preconfigured Poll-esponse message. This functionaltity enables the CN for cycle times down to 200μs and for an exceptional low jitter over the complete network. The PE²MAC operates best with port s POWELINK Hub and port s POWELINK. POWELINK Hub The POWELINK Hub by port is a Class 2 epeating Hub wit 3 MII-ports for use in POWELINk networks. It only introduces below 360ns delay (including delay by the PHYs) and less than 40ns Jitter. The POWELINK Hub integrates seamless with the PE²MAC Missing Driver or missing Feature Port is available for creating new driver or missing features.
8 POWELINK - Use Cases DesignTool Port s POWELINK DesignTool configures the Library, the Driver, the Objects and creates the XDD-File. Port s POWELINK DesignTool generates the fabric to combine User-Application, Protocol-Stack and the XDD-File to be a POW- ELINK CN-Device. The SW-Engineer configures using this GUI-Tool port s POWELINK, creates the POWELINK-objects and creates his own variables-definitions. Upon pressing a button the tool creates the fabric, consisting from various Header-Files and from the XDD-File. Further a reasonable documentation is created. The DesignTool saves development time, reduces design cycles and improves the quality of the product creation process. Get in touch: Port GmbH egensburger Strasse 7b Halle (Saale) GEMANY Phone: Fax: Web: service@port.de
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