ASDeX-driven Analog Circuit Verification

Transcription

1 -driven Analog Circuit Verification, Lars Hedrich Sebastian Steinhorst Department of Computer Science Goethe University Frankfurt am Main, Germany TUM CREATE Singapore Workshop Frontiers in Analog CAD, Berkeley, Feb. 14 th -15 th 2013

2 Outline Introduction and AXEI -driven Work-Flow Conclusion

3 Introduction Introduction Motivation: Aim: - Specification for analog circuits mostly written in text Complex description misunderstanding - Verification methodologies Difficult to understand without additional documentation Rarely implemented by end users - IP-XACT for digital circuits [IEEE SA ] - integrated successfully into validation and synthesis workflow - Integration of -format into analog verification workflow Include all relevant information - An interface from to target tools ASL & assertion based model checking [1] Other verification methodologies 3

4 Introduction Assertion-based Verification 4

5 Introduction -driven Design Flows AXEI & Templates DUV s specification in specification testbench function task 5

6 Introduction -driven Design Flows AXEI & Templates DUV s specification in specification testbench function task ASL 6

7 and AXEI Concept for Code Generation using AXEI Input: - file set - Code templates Template 7

8 and AXEI Concept for Code Generation using AXEI Input: - file set - Code templates Engine Interface: - Python - Parser - Generator Template AXEI Generator 8

9 and AXEI Concept for Code Generation using AXEI Input: - file set - Code templates Engine Interface: - Python - Parser - Generator Output: - Target code for design tools - New values of circuit s properties in - Documentation Template AXEI Generator Target Code PERL ASL VHDL- AMS 9

10 and AXEI Overview of Structure : Analog Specification Description in XML Formalization through XML-Schema-Definition (XSD) Contents: All relevant parameters of specification Ports with characteristics Properties of analog circuits Operating parameters & environmental conditions Information about measurement, testbench and simulation 10

11 and AXEI Overview of Structure : Analog Specification Description in XML Formalization through XML-Schema-Definition (XSD) Contents: All relevant parameters of specification Ports with characteristics Properties of analog circuits Operating parameters & environmental conditions Information about measurement, testbench and simulation 11

12 and AXEI Mapping Sub-Blocks in the Task Block Task 12

13 and AXEI Mapping Sub-Blocks in the Task Block Task Z = plog X Y Z = plog U U

14 and AXEI Mapping Sub-Blocks in the Task Block Task Z = plog X Y 20 Z = plog U U

15 and AXEI Mapping Sub-Blocks in the Task Block Task TB-Library TB component connects to port A and port B Specification Definition: Port input Port output Z = plog X Y 20 Z = plog U U 1 2 A = input B = output 15

16 ASDex-driven work-flow Examples: Generation of Testbench Code Template AXEI Generator Target Code PERL VHDL- AMS inn inp ASL 16

17 ASDex-driven work-flow Examples: Generation of Testbench Code <Specification> <ports> <port><name>in1</> <port><name>output</> <Testbench> <component> <name>uin</> <nature>v</> <dc_supply> <p_net>inp</> <n_net>0</> <Task-tb_port_mapping> <tb_port_mapping> <port_name>output</> <te_net_name>uout</> <tb_port_mapping> <port_name>in1</> <tb_net_name>inp</> Template AXEI Generator Target Code PERL ASL VHDL- AMS inn inp 17

18 ASDex-driven work-flow Examples: Generation of Testbench Code <Specification> <ports> <port><name>in1</> <port><name>output</> <Testbench> <component> <name>uin</> <nature>v</> <dc_supply> <p_net>inp</> <n_net>0</> AXEI Generator Template (Mako) Mapping: % for spec_port in ports.port: % if spec_port.get_name( ) == mapp.port_name: % spec_port.set_name(mapp.tb_port_name) Generation: % ${cp.nature} (instanz(ref_name, Template `${cp.name} ), net${dc_supply.p_net}, ${dc_supply.n_net}, ${cp_par.name}=${cp_par.value}); <Task-tb_port_mapping> <tb_port_mapping> <port_name>output</> <te_net_name>uout</> <tb_port_mapping> <port_name>in1</> <tb_net_name>inp</> spv (instanz(ref_name, `Uin ), netinp, 0, p1=1.5); SPICE like netlist file inn inp 18

19 ASDex-driven work-flow Examples: Generation of Function Code Template AXEI Generator Target Code PERL ASL VHDL- AMS 19

20 ASDex-driven work-flow Examples: Generation of Function Code <Function><name>slew-rate</> <object_name>in</> <object_name>out</> <variable_name>low</> <variable_default><value>0.2</> <divide/> <apply><minus/> <apply><fn><ci>max</></> <ci>out</></> <apply><fn><ci>min</></> <ci>out</></></> <apply><fn><ci>risetime</></> Template AXEI Generator <Ref_function><ref_name>slew-rate</> <func_mapping> <object_in_function>in</> <tb_net>inp</> <func_mapping> <object_in_function>out</> <tb_component>output</> <parameter_override> <variable_name>low</> <value>0.1</> Target Code PERL ASL VHDL- AMS 20

21 ASDex-driven work-flow Examples: Generation of Function Code <Function><name>slew-rate</> <object_name>in</> <object_name>out</> <variable_name>low</> <variable_default><value>0.2</> <divide/> <apply><minus/> <apply><fn><ci>max</></> <ci>out</></> <apply><fn><ci>min</></> <ci>out</></></> <apply><fn><ci>risetime</></> Template (Mako) % for child in function.iter(): %% %% Build the equation %% Replace the object name %% Override the variable value %% Transform to the target code function Template %% AXEI Generator <Ref_function><ref_name>slew-rate</> <func_mapping> <object_in_function>in</> <tb_net>inp</> <func_mapping> <object_in_function>out</> <tb_component>output</> <parameter_override> <variable_name>low</> <value>0.1</> ΔOUT / risetime Function ASL(macro) file numvar %intern_output_min, ; on steady assign(%intern_output_min,min) value(out)[-inf,inf]; on steady assign(%intern_output_max,max) value(out)[-inf,inf]; 21

22 ASDex-driven work-flow Verification Run 22

23 ASDex-driven work-flow Verification Run GUI Automatic Automatic Automatic Automatic Automatic Automatic 23

24 ASDex-driven work-flow Verification Run 180nm Technology Specification description in Format Testbench & Function Generation Properties Assertion Simulation Model Checking Evaluation Documentation Generation GUI Automatic Automatic Automatic Automatic Automatic Automatic 24

25 Conclusion Conclusion An -driven verification framework All necessary methods provided by AXEI Case study An higher degree of automation and formalization in verification process Better usability for end users 25

26 Thank you for your attention! Home Page: Workshop Frontiers in Analog CAD, Berkeley, Feb. 14 th -15 th 2013

27 Signal Transition (1) 27

28 Signal Transition (2) 28

29 and AXEI Description in Function Block Formulas described in MathML format Name of the function List of the objects to be calculated Function List of the variables, which are defined in the function Variable s name Default value of the variable Path for a pre-defined function description in mathml mathml description block Needed for property parameters calculation, e.g. in a function library of the model checking work flow [1]. 29

30 and AXEI Description in Function Block Formulas described in MathML format Function 20 Z = plog X Y Objects Variable Needed for property parameters calculation, e.g. in a function library of the model checking work flow [1]. 30

31 Topology Synthesis from Examples: Generation of Ocean Scripts <Function> <object_name>x</> <object_name>y</> <variable_name>low</> <variable_default><value>0.1</> <mrow> <mi>psrr</> <mo>=</> <mn>20</> <mi>log</> <mo>(</> <mrow> <mi>x</> <mo>(</> <mi>freq</> <mo>)</> </> <mo>/</> <mrow> <mi>y</> <mo>(</> <mi>freq</> <mo>)</> </> <mo>)</> </> <Ref_function> <func_mapping> <object_in_function>x</> <tb_component>vcc</> <func_mapping> <object_in_function>y</> <tb_component>vos</> <parameter_override> <variable_name>freq</> <value>10</> Template (Mako) % for child in function.iter(): %% %% Build the equation %% Replace the object name %% Override the variable value %% Transform to the target code function Template %% AXEI Generator PSRR = 20log(Vcc(freq=10)/Vos(freq=10)) Ocean Script {(db20(value(mag(getdata("/vcc"?result "xf-xf")) 10)) - db20(value(mag(getdata("/vos"?result "xf-xf")) 10)))} 31

32 Conclusion Comparison Manual design flaw avoided Time saved, through the fully automatic framework 32

33 Conclusion Comparison asdex::specio::class docs doc_output asdex_output Manual design flaw avoided Time saved, through the fully automatic framework 33

34 Conclusion Comparison Manual design flaw avoided Time saved, through the fully automatic framework 34

35 Conclusion Comparison asdex::specio::class docs doc_output asdex_output Manual design flaw avoided Time saved, through the fully automatic framework 35

36 Conclusion Comparison Manual design flaw avoided Time saved, through the fully automatic framework 36

37 Conclusion Comparison Manual design flaw avoided Time saved, through the fully automatic framework 37