Analog Verification Concepts: Industrial Deployment Case Studies

Transcription

1 Analog Verification Concepts: Industrial Deployment Case Studies Frontiers in Analog CAD (FAC 2014) July, 9-10, 2014, Grenoble, France Peter Rotter, Infineon Technologies AG

2 Agenda Analog Verification - Context/Components/Coordination (R)evolution of Industrial Verification Ecosystem Analog Verification Planning & Sign-Off Requirements on Verification Software & Integration Case Study 1: Safe Operating Area Checks Case Study 2: Analog Model Validation Summary & Final Thoughts Page 2

3 Agenda Analog Verification - Context/Components/Coordination (R)evolution of Industrial Verification Ecosystem Analog Verification Planning & Sign-Off Requirements on Verification Software & Integration Case Study 1: Safe Operating Area Checks Case Study 2: Analog Model Validation Summary & Final Thoughts Page 3

4 Mixed-Signal Sign-Off and Regression Overview Product Requirements Over-All Verification Plan Verification Manager T T XML T Tracability Target Datasheet T Design Specs Open Access Design Data Mixed-Signal Regression Runner T Analog Regression Runner ADE-L Model Validation Layout Checks Layout Extraction Plotting ADE-XL T T T T I check & run check & run check & run check & run Interactive Setup & Modular Rerun I I I I I I I check & run check & run Analog Autom. Workflow: Task Sequence Page 4

5 Analog Verification - Context/Components/Coordination T DEV T IF Techfile Design Manual Dev. Handbook Sign-Off Guidelines Product Requ mts Product Spec Design Group PDK Design Flow Design Package Design Flow Compl nce Guidelines Setup Design Step 1 Design Step 2 Design Step Design Step N Consis ncy Guidelines Automation Data 1 Data 2 Data Data N Page 5

6 Agenda Analog Verification - Context/Components/Coordination (R)evolution of Industrial Verification Ecosystem Analog Verification Planning & Sign-Off Requirements on Verification Software & Integration Case Study 1: Safe Operating Area Checks Case Study 2: Analog Model Validation Summary & Final Thoughts Page 6

7 Trends in Analog Design Technology Rules increasing number and complexity for small technology nodes technology variants for specific purposes (automotive/industrial) CMOS Transistor Model Complexity increasing number of parameters (BSIM4, PSP, HiSIM-HV several hundred param s) Technology variations increasing for small technology nodes statistical methods required Regression Tooling increasing number and complexity of solutions Safety Requirements formal proofs of compliance required General (IEC-61508) Safety Integrity Level (SIL) Classification Automotive (ISO 26262) Aviation (DO-178/254) Railway (CENELEC 50126/128/129) Page 7

8 Two Worlds collide creative intuitive implicit holistic interactive Analog Design systematic formalized explicit detailed automated Management Page 8

9 (R)evolution of Industrial Verification Ecosystem Analog Verification creative intuitive implicit holistic interactive Analog Design Handshake systematic formalized explicit detailed automated Analog Verification Engineer Industrialized Work Split Page 9

10 Digital vs. Analog Verification Management Digital Mixed-Signal Analog ADE-XL Digital Reg. AMS Designer emanager NCSIM Verification Manager SystemC Questa Analog Reg. Spectre Ultrasim Mixed-Signal Reg. Titan Nanosim XA ADMS VCS-XA Page 10

11 Overall Verification Crossing Design Domains Digital Regression Requirement Engineering Analog Regression Functional Verification Mixed-Signal Spice Analog Regression Spice Mixed-Signal Vertical Verification Domain-Crossing Horizontal Verification Domain-Crossing Additional effort and complexity for design groups and CAD support Page 11

12 Some Open Issues Design Flow Automation support for transfer of Guidelines/Specifications to Design Steps Setup Interface for automation support of Design Group specific Guidelines Sign-Off Status Reporting General Examples for Manual Design Steps: Product Requirement to Block Level Specification break-down Process Analog Block-level Verification Definition & Setup Examples for Implicit Requirements: Check for design critical aspects not covered by technology models Implicit design constraints imposed by technology (topology selection) Analog Design is a complex problem requiring to cover an immense number of currently non-formalized aspects. Key for Successful Design: Designer Intuition Hence: Water-proof formalization via guidelines questionable! Page 12

13 Agenda Analog Verification - Context/Components/Coordination (R)evolution of Industrial Verification Ecosystem Analog Verification Planning & Sign-Off Requirements on Verification Software & Integration Case Study 1: Safe Operating Area Checks Case Study 2: Analog Model Validation Summary & Final Thoughts Page 13

14 Analog Verification - Integration Objectives Systematic Analog Sign-off Guidelines tooling for hierarchical requirement break-down, verification planning and execution completeness ensured via proper coverage measures setup support via pre-defined templates (Analog Verification IP) Formalized overview status reports hierarchical status feed-back proof of safety requirements compliance Explicit measurements & checkers specification ranges result evaluation Detailed break-down in list of individual tasks with dedicated objectives Automated capture existing interactive setups and push to automation (unified) regression runner for all verification domains specification checks automated generation of documentation Page 14

15 Analog Sign-Off Motivation Status Quo Systematic approach to ensure Analog Sign-Off Compliance generally requested Complete supply chain for tool, technology and library data provision considered Overall Goals Systematic, formalized approach to list, specify (short work instructions) and document Analog Sign-Off related Design Steps including Setups Ensure Analog Sign-Off compliant Design System provision Account for Technology Specific Flavors Deployment Guidelines should be used for a systematic planning and execution of all defined steps and thus help to ensure Analog Sign-Off compliance for all Analog-/Mixed-Signal Design for internal use Copyright Infineon Technologies AG All rights reserved. Page 15

16 Generic Scheme for Sign-Off Task Definition Concise scheme for descriptions of Analog Sign-Off Tasks: Sign-Off Task unique keyword Category ordering scheme Scope/Objective concise definition of purpose Application Model scenarios for check deployment Method/Tooling description of tool chain Result Evaluation guideline for result assessment Page 16

17 AMS Verification Planning & Sign-Off Product Requ mts Product Spec AMS Verification Planning Analog Mixed-Signal Digital Model Spec Model Verification Analog Reg. Mixed-Sig Reg. Voltage Drop Digital Reg. vmanager AMS Verification Sign-Off Page 17

18 Reliability Planning & Sign-Off Product Requ mts Product Spec Static Tasks Dynamic Tasks Reliability Planning Analog Mixed-Signal Digital Device Block Interface Metallization REL Model Spec REL Model Verif. SOAC Aging Sim. Static ERC Floating Gate REL DRC Curr. Density Dynamic ERC ESD Reliability Sign-Off Page 18

19 Agenda Analog Verification - Context/Components/Coordination (R)evolution of Industrial Verification Ecosystem Analog Verification Planning & Sign-Off Requirements on Verification Software & Integration Case Study 1: Safe Operating Area Checks Case Study 2: Analog Model Validation Summary & Final Thoughts Page 19

20 Basic Automation Concepts Setup Design Step 1 Design Step 2 Design Step Design Step N Interactive Execution Data Step 1 Data Step 2 Data Step Data Step N Task Module 1 Task Module 2 Task Module Task Module N Work Flow Definition Automation Platform Page 20

21 Analog Automation Workflow in Action Set Up Set Up Set Up Set Up Set Up Schematic Layout Layout Netlist Schematic Schematic Checks Log-File Layout Verification Log-File Layout Extraction Log-File Parasitic Reduction Log-File Analog Regression Log-File Plot Tool Log-File Task control Pass ok Automation Engine Out of date checking Workflow: Task Sequence Status Report Page 21

22 Mixed-Signal Sign-Off and Regression Strategy Pick-up Approach avoid additional setup effort as much as possible capture existing interactive setups and push to automation identify and build up stand-alone base applications (Analog Regression Runner, Model Validation) Modularity Task Modules as generic building blocks Task Sequences provided as pre-defined sets for common use cases Flexibility selection of individual Task Modules local modification/definition of Task Sequences address small sequence of tasks with highest automation benefit Transparency native and stand-alone application usage should not be blocked out strong focus on error checking and debugging Page 22

23 Agenda Analog Verification - Context/Components/Coordination (R)evolution of Industrial Verification Ecosystem Analog Verification Planning & Sign-Off Requirements on Verification Software & Integration Case Study 1: Safe Operating Area Checks Case Study 2: Analog Model Validation Summary & Final Thoughts Page 23

24 Reliability Planning & Sign-Off Product Requ mts Product Spec Static Tasks Dynamic Tasks Reliability Planning Analog Mixed-Signal Digital Device Block Interface Metallization REL Model Spec FOCUS SOAC Aging Sim. Dynamic ERC Static ERC Floating Gate ESD REL DRC Curr. Density REL Model Verif. Reliability Sign-Off Page 24

25 Electrical Device Stress I DS Electrical Device Stress during Operation t Operating Modes Important! Page 25

26 Safe Operating Area Checks (SOAC) Introduction For semiconductor devices the Safe Operating Area is defined as the voltage and current conditions over which the device can be expected to operate without self-damage. Checks can be defined for Spice transistor level simulations using tool specific features (assertions, special checks). The allowed voltage/current ranges are dynamically monitored during simulation runtime and warning/error messages are issued in case of violations. SOAC setups are technology dependent and need to be defined and provided with each Technology Package. SOAC can be costly with respect to memory consumption, runtime and license usage. Therefore the usage needs to be transparent and controllable by the designer. A unified interface and used model concept for all supported tools is very desirable. Page 26

27 SOAC Analog Sign-Off Definition Check Scope Device stress disaster check Application Model Use standard test scenarios for specification verification over temperature, process corner, supply modes, Functional tests for power on/off, sleep, wake-up, Note: Stress-scenario definition via stimulus important for check coverage Method/Tooling Include simulator specific Save Operating Area Checks (SOAC) files provided in Technology Package Run Spice simulation (Spectre, Titan, Fastmos, Mixed-Signal) Result Evaluation Check all messages in violation files via Cadence ADE browser or text based in log file (Message Type: Warning) Page 27

28 SOAC Context/Components/Coordination REL Design Manual Dev. Handbook T IF Techfile Guidelines Designer PDK Design Flow Design Package Design Flow Setup Warning Design Warning Warning Automation Warning Warning Page 28

29 SOAC Design Flow: Overview & Open Issues Primary Use Model Spice Level Tools (Manual) Spice: Spectre, Titan (IFX) FastSpice: XA, Nanosim, Ultrasim Mixed-Signal: AdvanceMS, AMS Designer Problems: non-standardized check definition: tool/vendor specific concepts check scenario definitions with reasonable coverage large number of dummy errors Secondary Use Model Regression Tooling (Automation) IFX Analog Regression Runner, ADE-XL IFX Mixed-Signal Regression Runner IFX Digital Regression Runner, vmanager Problems: non-standardized activation and result provision transparent result propagation: documentation/summary report missing waiver concept missing Design Flow Support Design Package interface defined Setup support for default SOAC settings where possible Unique result evaluation script (IFX) for all tools supporting primary use model Page 29

30 SOAC Open Issues: Focus Topic Usability Problem issue with large number of dummy errors Possible Solution Scenarios define checks with improved selectivity: simple technology rules need to be extended provide filtering/post-processing/sorting using some kind of severity criteria (e.g. duration factor: see next slide) enhance tool functionality by more efficient assessment features (back-annotation, violations overlay to waveforms, waiving methodologies) Page 30

31 SOAC Overshoot Suppression via duration I DS default t I DS t d > t s t d < t s Suppressed duration = t s t Page 31

32 Case Study 1: Safe Operating Area Checks Deployment Issues: CAD Setup: Non-standardized SOAC check definition, activation and especially result provision leads to high effort for overall integration Vertical Verification Domain-Crossing: Effort for check integration to regression environments Horizontal Verification Domain-Crossing: Analog Verification / Reliability Checks require different application scenarios; improved check selectivity requires cross-domain cooperation Implicit/Explicit: Converting design know-how to check scenarios with reasonable coverage based on use modes specified at verification planning Interactive/Automation: Automatic result evaluation in case of dummy errors impossible; waiving concepts currently missing Page 32

33 Agenda Analog Verification - Context/Components/Coordination (R)evolution of Industrial Verification Ecosystem Analog Verification Planning & Sign-Off Requirements on Verification Software & Integration Case Study 1: Safe Operating Area Checks Case Study 2: Analog Model Validation Summary & Final Thoughts Page 33

34 AMS Verification Planning & Sign-Off Product Requ mts Product Spec AMS Verification Planning Analog Mixed-Signal Digital FOCUS Model Spec Model Verification Analog Reg. Mixed-Sig Reg. Voltage Drop Digital Reg. vmanager AMS Verification Sign-Off Page 34

35 Analog Models Specification, Features & Verification Analog Model Specification o o o o interface definitions: list of terminals and power supply connections list of functional features list of limitations due to abstractions validity/application ranges Analog Model Features o o o o analog behavioral model real-value models, i.e. data types: analog_t, analog_t_vector UPF-support (IEEE.UPF VHDL-package application), get_supply for sink-power-connects, set_supply for supply sources (i.e. voltage regulator model) or equivalent (System-)Verilog library capability validity-/out-of-range checks and reporting (top-level requirement) Test Bench Features Two modes: o o behavioral mode without out-of-range stimulus for model consistency verification (this talk) behavioral mode incl. out-of-range stimulus for model feature verification Page 35

36 Model Consistency Concept General Overview Flow-Chart (Detailed) Input Description File : Analog Designer Input Requirement Functional Description Specification (min/max) Stimuli (VHDL+UPF) Analog Model (VHDL+UPF) Checker (VHDL+UPF) Test-Bench: (System)-Verilog: HW HW ßà FW TB: Verilog ßà Schematic VHDL-Codes: Im / Export Stimuli (VHDL+UPF) Config A: Analog Model (VHDL+UPF) Checker (VHDL+UPF) Regression (WOTAN) Pass/Fail Stimuli (VHDL+UPF) Analog Schematic (Transistor) Checker (VHDL) Pass/Fail Config B: Mixed-Signal-Simulation:.) Cadence Model Validater (amsdmv).) Same Test-Bench schematic.) 2 different config views Automatic Comparison Waveform Plot Pass/Fail Pass/Fail manually Page 36

37 Analog Model Development and Analog-centric Verification Flow-Chart (Detailed) Input Description File : Analog Designer HDL-driven Modeling For model development Digital test bench applied Input Requirement Functional Description Specification (min/max) Stimuli (VHDL+UPF) Analog Model (VHDL+UPF) Checker (VHDL+UPF) Test-Bench: (System)-Verilog: HW HW ßà FW TB: Verilog ßà Schematic VHDL-Codes: Im / Export Stimuli (VHDL+UPF) Config A: Stimuli (VHDL+UPF) Config B: Analog Model (VHDL+UPF) Analog Schematic (Transistor) Checker (VHDL+UPF) Checker (VHDL) Regression (WOTAN) Pass/Fail Pass/Fail Model Consistency Check Mixed signal simulation with two configurations (DUT as HDL-model/Spiceschematics) Test bench applied Result compare tool applied Regression (for multiple models) Mixed-Signal-Simulation:.) Cadence Model Validater (amsdmv).) Same Test-Bench schematic.) 2 different config views Automatic Comparison Waveform Plot Pass/Fail Pass/Fail manually Page 37

38 Waveform Comparison General Approaches Simulator internal - on-the-fly Measurements with specification limits Assertions (block-level self-checking) Vector files with expected outputs (VEC, EVCD format) Simulator external - post-processing Specifications (Analog Regression Runner, ADE-XL) Vector-valued Measurements (series of time points) Waveform (result data points) post-processing Signal Types DC, AC, TRAN, HB, Noise analog, digital Focus: time-domain (transient) simulations with varying time steps Page 38

39 Transient Comparison Algorithm Basic Ideas Boundaries via Scalar Values Curve Length Boundaries via Signals Tube Model Test Waveform Reference Waveform Tolerance Boundaries dy, dt Page 39

40 Automation of Analog Simulation and Waveform Compare Flow Cadence Solution amsdmv Page 40

41 Digital-centric Model Verification CAD Framework for Digital-centric Model Verification UVM (Standard Universal Verification Methodology) as basis IFX analog verification extensions A-UVM Design and Verification Conference, DVCON 2014 Automated Comparison of Analog Behavior in a UVM Environment, Sebastian Simon, Alexander E. Rath, Volkan Esen, and Wolfgang Ecker, Infineon Technologies AG A-UVM Features Analog transactions Constrained-random analog stimulus Monitoring of analog behavior Basic checks for comparing analog transactions Page 41

42 Automation of Digital Simulation and Waveform Compare Flow UVM Example Page 42

43 Digital Comparison Algorithm Basic Idea Metric: Earth Mover s Distance Approach to measure the distance between two distributions Visualization: transportation of soil from one pile to another = Work += distance x amount: A = i= 1 j= 1 Find minimum flow which equalizes distributions à optimization problem has to be solved n n d ij f ij Page 43

44 Automation of Digital Simulation and Waveform Compare Flow Integration Concept I Generic monitors extract analog transactions = feature vectors Extraction types: sampling, FOURIER, sine, ramp, jump Similarity analysis implemented with SystemVerilog DPI-C Page 44

45 Automation of Digital Simulation and Waveform Compare Flow Integration Concept II Analyzing one pair of transactions results in exactly one value s EM for the Earth Mover s Distance Range: 0 s EM 1 (where 1 implies a full match) Basic idea for regression: defining a lower bound for s EM Once s EM falls below this bound, the regression test fails and the regarding transactions can be examined Page 45

46 Analog-centric vs. Digital-centric Comparison of Model Verification Features Features Analog-centric Digital-centric Test Bench Compare Setup Debugging Regression Documentation schematic result data access manual stimulus generation load conditions waveform pre- and post-processing A/D, D/A conversion GUI based tolerance definitions messages in log file analog waveform viewer: automatic signal pair selection violation area reports and marker (visualization of tolerance boundaries) amsdmv Analog Regression Runner (each in Analog Automation Env.) automated via Regression detailed reporting of violations A-UVM (driver, monitor, score board) constrained random stimulus generation reuse from digital functional verification extraction type (sampling, Fourier, ) extraction parameter (sampling rates) lower bound for metric messages in log file digital waveform viewer: manual signal pair selection digital signal check via SimVision UVM in Digital Regression Runner vmanager automated via UVM/Regression Page 46

47 Analog-centric vs. Digital-centric Comparison of Use Models Flow-Chart (Detailed) Input Description File : Analog Designer Input Requirement Functional Description Specification (min/max) Efforts for Digital-centric Model Verification: Full reuse potential of existing digital test bench No transfer to full-custom Design Flow required No additional analog test bench setup (digital test bench reuse and substitution of HDL by Spiceschematics for mixed-signal configuration) Support for UPF enabled by default in HDL-driven approach Stimuli (VHDL+UPF) Analog Model (VHDL+UPF) Checker (VHDL+UPF) Test-Bench: (System)-Verilog: HW HW ßà FW TB: Verilog ßà Schematic VHDL-Codes: Im / Export Stimuli (VHDL+UPF) Config A: Stimuli (VHDL+UPF) Config B: Analog Model (VHDL+UPF) Analog Schematic (Transistor) Mixed-Signal-Simulation:.) Cadence Model Validater (amsdmv).) Same Test-Bench schematic.) 2 different config views Checker (VHDL+UPF) Checker (VHDL) Automatic Comparison Waveform Plot Regression (WOTAN) Pass/Fail Pass/Fail Pass/Fail Pass/Fail manually Efforts for Analog-centric Model Verification: Requires semi-custom to full-custom Design Flow transfer of all HDL-elements Requires to setup a second simulation in analog environment (analog test bench schematics) No UPF support (manual and expert-level effort required for UPF-enabling) Page 47

48 Case Study 2: Analog Model Validation Deployment Issues: Vertical Verification Domain-Crossing: Integration of model validation into different regression environments lead to different use models Horizontal Verification Domain-Crossing: Analog-centric / Digital-centric Model Verification requires different domain know-how Implicit/Explicit: Converting design block know-how to model specification and check scenarios with reasonable coverage based on validity/application ranges specified in verification planning Interactive/Automation: Validation acceptance criteria need to be defined explicitly; additional effort for out-of-range checks Page 48

49 Agenda Analog Verification - Context/Components/Coordination (R)evolution of Industrial Verification Ecosystem Analog Verification Planning & Sign-Off Requirements on Verification Software & Integration Case Study 1: Safe Operating Area Checks Case Study 2: Analog Model Validation Summary & Final Thoughts Page 49

50 Summary & Final Thoughts Analog Verification Coverage definitions/measures currently missing design/topology/check specific Formalization binary good/bad decisions not compliant with analog designer reasoning trade-offs and margins usually not covered (but: compare Worst-case Distance Measure for Yield Estimation) converting implicit to explicit knowledge often tricky (compare topology recognition for automatic constraint setup in tool Wicked, MunEDA) Page 50

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