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1 From layout to chips CircuitsMulti-Projets MPW Services Center for ICs, Photonics & MEMS Prototyping & Low Volume Production mycmp.fr Grenoble - France
2 From layout to chips STMicroelectronics Standard Technology offers at CMP in 2018 Deep Sub-Micron, SOI and SiGe Processes
3 From layout to chips STMicroelectronics Technology offers at CMP: CMP Process Portfolio from ST 160nm CMOS: SOIBCD8s in nm CMOS : BCD8SP 130nm SiGe : BICMOS9MW & HCMOS9GP 130nm SOI: H9SOI-FEM 130nm HV-CMOS: HCMOS9A 65nm CMOS: CMOS065LPGP 55nm SiGe: BICMOS055 28nm FDSOI: 28FDSOI 3
4 From layout to chips Deep Sub-micro 160nm: SOIBCD8s 160nm SOIBCD8s: Bipolar-CMOS-DMOS Smart Power on SOI: 160nm Mixed Analog / Digital Bipolar-CMOS-DMOS 4LM on SOI Gate length: 180nm (drawn). 4 Cu metal layers, AlCu Thick Power M4. Operating voltages: 3.3V baseline, 1.8V optional : Digital & Analog. Medium Voltage Module Power MOS: 6V 40V. High Voltage Module MOS : 70V 200V. Dielectric Isolation on SOI. Analog + Digital + Power & HV on one chip. High Voltage to drive external loads. Analog block to interface «external world» to the digital systems. Digital Core for signal processing. Memories SPRAM/ DPRAM / ROM available. 1 MPW run organised in 2018: 22 sd February. Turnaround: 18 weeks to 24 weeks. Current supported version of Design Kits : 2.1 Applications: Automotive Sensor Interface ICs, 3D Ultrasound, MEMS & micro-mirror driver.
5 From layout to chips Deep Sub-micro 160nm: BCD8SP 160nm BCD8SP: Bipolar-CMOS-DMOS Smart Power: 160nm Mixed Analog / Digital Bipolar-CMOS-DMOS 4LM. Gate length: 180nm (drawn). 4 Cu metal layers, Thick Power M4, M4 Al optional. Operating voltages: 1.8V - 5V : Digital & Analog. Power devices : 10V - 18V - 27V - 42V - 60V. Dual gate oxide process : 1.8V CMOS, 5V CMOS. Analog + Digital + Power & HV on one chip. High power transistor. Low power digital and analog device. Memories SPRAM/ DPRAM / ROM available free of charge on request. Standard cells librairies : Analog/digital, IO, Power devices. 3 MPW runs organised in 2018: 28 th February, 24 th April and 2 sd October. Turnaround: 18 weeks to 24 weeks Current supported version of Design Kits : 2.4. Applications: Power Management systems, DC-DC converter, Motor drivers, Printer.
6 From layout to chips Deep Sub-micro 130nm: H9-SOI-FEM 130nm H9-SOI-FEM: Front-End Module: 130nm mixed A/D/RF CMOS SLP/M4TC ( Thick Copper Metal Stack). Gate length: 130nm (drawn). Ultra-thick Cu top metal, 4 Cu metal layers. Body contacted CMOS. High Linearity MIM capacitor (2fF/mm 2 ). 5.0V NLDMOS & PLDMOS. Standard cell libraries : IO cells, ESD kit. Floating body CMOS 5.0V NLDMOS. 200mm SOI wafers with high resistive (HR) substrate and Trap Rich SOI. 3 MPW runs organised in 2018 : 21 st March, 7 th June and 29 th October. Turnaround: 16 weeks to 18 weeks. Current supported version of the design kits: Applications: Radio receiver/transceiver, Cellular, Wifi, Automative keyless systems.
7 From layout to chips Deep Sub-micro 130nm: H9GP / B9 130nm HCMOS9GP CMOS and BiCMOS9MW SiGe: General Purpose: 130nm mixed A/D/RF CMOS SLP/6LM (triple Well) HCMOS9GP. BICMOS9MW technology is using 130nm HCMOS9GP as base process. Power supply : 1.2V for core and 2.5V for IO. 6 Cu Metal layers, thick top metal layer. SiGe-C bipolar transistor (ft around 230GHz) in BiCMOS9MW. MIM capacitors. High performance and Medium voltage NPN bipolar transistor. Memories SPRAM/ DPRAM / ROM available free of charge on request. Lead-time for memory generation: 1 to 2 weeks. Standard cells librairies. Tutorial in development to ease the migration. 3 MPW runs organised in 2018: 14 th February, 15 th May and 14 th November. Turnaround: 16 weeks to 18 weeks. Current supporter version of the Desing kits: 2.9b in BiCMOS9MW. Current supporter version of the Design kits: 9.2 (RF option available) in HCMOS9GP. Applications: General purpose Analog/Digital/ RF applications and Millimeter-Wave applications (frequencies up to 77GHz for automotive radars), WLAN, Optical communications.
8 From layout to chips 130nm: HCMOS9A + NVM offer. 130nm HCMOS9A HV-CMOS: Addon NVM with CEA-LETI Based on HCMOS9A 130nm mixed A/D/RF technology of STMicroelectronics, and with cooperation of CEA-LETI. CMP opens a new service for Non Volatile Memory integration in Q4, Standard cells Librairies : Core cells, PR, Analog and digital IO and NVM addon. LETI NVM design kit available in February/March MPW run organised in 2018: Q Turnaround: 24 weeks to 30 weeks (dataprep/front end ST and post-process CEA-LETI). Current supported version of the design kits: Applications: For all applications requiring non-volatile memory.
9 From layout to chips Deep Sub-micro 130nm: HCMOS9A 130nm HCMOS9A HV-CMOS: Mixed Digital / Analog / Energy Management: 130nm mixed A/D/RF CMOS SLP/4LM (triple Well). Gate length: 130nm (drawn). 4 Cu metal layers, Thick M4. Low k inter-level dielectric. Cross section view - Bipolar HV transistor Power Management. Operating voltages: 1V2 GO1, 4V8 for GO2, 20V for HV with DGO option. Specific Devices: N&P 20V Drift MOS with 85A gate oxide, MIM 5fF capacitor. Memories SPRAM / ROM available free of charge on request. Standard cells Librairies : Core cells, PR, Analog and digital IO. 1 MPW run organised in 2018: 2 sd November. Turnaround: 16 weeks to 18 weeks. Current supported version of the design kits: Applications: Implantable devices, Robots/drones, Energy harvesting applications, Sensors wireless, Connected devices/internet of thing, Autonomous systems.
10 From layout to chips Deep Sub-micro 65nm: CMOS65LPGP 65nm CMOS65LPGP CMOS: Low Power General Purpose: 65nm mixed A/D/RF CMOS SLP/7LM (triple Well). Gate length: 65nm (drawn). 7 Cu metal layers. Dual gate oxide (1V for core and 2.5V for IO). Various Power supplies: 2.5V, 1.8V, 1.2V, 1V. MIM and Fringe MOM capacitors. Analog / RF capabilities. Multiple Vt transistor offering. High Density of integration: 800kgates/mm². Memories SPRAM/ DPRAM / ROM available free of charge on request. Standard cells librairies. RF kit available on request and subject to restriction. 3 MPW runs organised in 2018: 21 th March, 7 th June and 29 th October. Turnaround: 22 weeks to 26 weeks. Current supported version of the design kits: 5.4. Applications: General purpose, Analog/RF capabilities.
11 From layout to chips Deep Sub-micro 55nm: BiCMOS055 55nm BiCMOS055 SiGe: Low Power: 55nm mixed A/D/RF CMOS SLP/8LM (triple Well). Gate length: 55nm (drawn). 8 Cu metal layers, Ultra-thick Cu top metal. Low Power and General purpose MOS transistor. Dual gate oxide (1V for core, 2.5V for IO). MIM and Fringe MOM capacitors. Bipolar SiGe-C NPN transistors with Ft=320GHz. High density of integration : up to 970kgates/mm². Analog / RF capabilities. Various power supplies : 2.5V, 1.2V, 1V. Millimiter-wave inductor. 3 MPW runs organised in 2018: 26 st March, 7 th June and 29 th October. Turnaround: 28 weeks to 36 weeks. Current supported version of the design kits : 2.6 Applications: Optical, Wireless and High-Performance Analog 11 Applications.
12 From layout to chips Deep Sub-micro 28nm: FDSOI28 28nm FDSOI: Fully depleted Silicon On Insulator: 28nm mixed A/D/RF CMOS SLP/8LM (triple Well). Gate length: 28nm (drawn). 8 Cu metal layers (6 thin + 2 thick Cu top metal). Body biasing. Triple well Fully depleted SOI devices. IO supply voltage: 1.8 V using the IO oxide. Ultra low k inter-level dielectric. Low leakage (High density) SRAMS. Analog / RF capabilities. MIM and Fringe MOM capacitors. Standard cell libraires (more than 3Mgates/mm²). 2 MPW runs organised in 2018: 16 th April, 5 th November. Turnaround: 24 weeks to 32 weeks. Current supported version of the design kits : 2.9. Applications: Low power and high performance applications
13 From layout to chips STMicroelectronics Libraries Standard Cells libraries included in STMicroelectronics Design kits: The content of librairies depends on each technology : CORE cells Libraries: CORE: General purpose core libraries. CORX: Complementary core libraries (complex gates). CLOCK: Buffer cells for clock tree synthesis. PR: Place and route filler cells. DP: Datapath leaf cells libraries. HD: High density core libraries. IO cells Libraries: 1.8V, 2.5V, 3.3V IO pads: 80µ, 65µ, 60µ, 50µ 40µ and 30µ IO pads : Digital and Analog. Staggered IO pads. Flip-Chip pads. Level Shifters, and compensation cells. ESD.
14 From layout to chips STMicroelectronics IP blocks RAMS and ROM block available through STMicroelectronics generators: Technology SPREG SPRAM DPREG DPRAM ROM MPSRAM BCD8SP Yes Yes Yes HCMOS9GP Yes Yes Yes Yes BICMOS9MW Flow for a request of block (1 or 2 weeks): Send to CMP type, number of words and number of bits. Receive results of Cut explorer. Send names of selected cuts. Yes HCMOS9A Yes Yes CMOS65LP Yes Yes Yes Yes Yes CMOS65GP Yes Yes CMOS28FDSOI Yes Yes Yes Yes Yes Generation at STMicroelectronics, data preparation at CMP (reduced layouts). Delivery of blocks. Data include layout, models for simulation, files for P&R.
15 From layout to chips STMicroelectronics Design-kits Supported CAD Tools by STMicroelectronics Design kits:
16 From layout to chips Submission cycle for CMP users Reservation for MPW run one month before the CMP deadline is mandatory : Design transfer Wafers shipment Users - Research Laboratories - Education & Universities - Companies, Sartup - Data checking (DRC) - Help for corrections (Report) - Data preparation (Sealring/Tiling) - Supports Foundry 2 to 3 weeks Report for corrections Transfer validated designs 12 to 28 weeks Depending on technologies The global turnaround includes the data checking, verifications, supports and final data preparation done at CMP
17 . From layout to chips Data preparation for CMP users The circuits must be sent at CMP by FTP : You must send your circuit without sealring and without tiling. You must run DRCs on the gds2 file before sending it. DRC must be clean except low densities outside exclusion area. DRC is free of fatal error Sealring generation Dummies generation - Replacement of ST standard cells - Addition of the sealring - Verification of ST standard cells used - Addition of logos - Data checking + DRC - Addition of fondry cells - Help for corrections (Report) - Move to origin - Supports - Verification of generated dummies - Final DRC - Verification of densities - Report to the user if necessary - Preparation of final database - Shipment to ST
18 From layout to chips Thank you!
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