Lecture 11: PI/T parallel I/O, part I

Transcription

1 Lecture 11: PI/T parallel I/O, part I Geeral descriptio of the parallel I/O fuctio Bufferi Hadshaki Iput ad Output trasfers Timi Diarams Reister model of the Port Geeral Cotrol Reister (PGCR) Port Service Request Reister (PSSR) Port {A,B,C} Data Directio Reister (PxDDR) Port Iterrupt Vector Reister (PIVR) Port {A,B,C} Data Reister (PxDR) Port {A,B} Alterate Data Reister (PxADR) Port Status Reister (PSR) Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 1

2 Parallel I/O eeral descriptio The parallel fuctio has three ports Two idepedet 8-bit ports ( ad B) A third dual-fuctio port C Ports A ad B be ca be used as I/O ports with various hadshaki ad bufferi capabilities i four differet modes Mode 0: Uidirectioal 8-bit Mode 1: Uidirectioal 16-bit Mode 2: Bidirectioal 8-bit Mode 3: Bidirectioal 16-bit Port C ca be used as a simple 8-bit port without hadshaki or double-bufferi a iterrupt iterface to the timer a iterrupt iterface to parallel I/O a support iterface for DMA operatio Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 2

3 Double bufferi ad latches iitial iput latches fial iput latches The PI/T data is double-buffered The PI/T is able to receive a ew iput while stori the previous iput Data ca be trasferred at almost the maximum rate at which the ca read the PI/T, without iformatio bei lost iput output 1 byte D-latch A up-arrow represets a 0-to-1, or positiveede, trasitio A dow-arrow represets a 1-to-0, or eative-ede, trasitio Data is latched o Q oly duri a positiveede trasitio of the clock Data iput Clock iput D Q output D CLK Q x 0,1, No chae Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 3

4 Hadshaki Hadshaki Permits data trasfers to be iterlocked with a exteral activity, so that data is moved at a rate i keepi with the peripheral s capacity D 0 Iterlocked meas that the ext actio caot o ahead util the curret actio has bee completed Iput port Data i A I/O trasfer usi hadshaki is also called a closed-loop data trasfer D 7 A iput port is iformed of the arrival of ew data throuh a iput strobe Iput strobe (load ew data) A output port aouces the availability of ew data throuh a output strobe D 0 I the PI/T parallel iterface, hadshaki is achieved by meas of four hadshake sials H1 ad for port A Output port Data out H3 ad H4 for port B D 7 Output strobe (ew data available) Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 4

5 Iterlocked hadshake iput mode Let s assume a data trasfer throuh Port A. The PI/T has two data trasfer cotrol lies: a ede-sesitive iput H1 ad a output The PI/T idicates the peripheral that it is ready to accept ew data by asserti its output The peripheral forces a active trasitio o the PI/T s H1 iput, iformi the PI/T that data is ow available o its data iput port Asserti H1 sets a status bit withi the PI/T ad eerates a iterrupt request to the if the PI/T is prorammed to do so The PI/T eates its output to iform the peripheral that the data has bee received At the same time, the peripheral is idicati that it is o loer i a positio to receive ew data The peripheral eates H1 to iform the PI/T that it has ackowleded the data trasfer The PI/T asserts to idicate that it is oce more ready to receive data from the peripheral At this stae, the system is i the same state as i the first step of this sequece, ad a ew cycle may commece Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 5

6 Iterlocked hadshake output mode The loads data ito the PI/T s output reister, causi the output to be asserted after a delay of two clock cycles The assertio of idicates to the peripheral that the data is available The peripheral asserts H1 to idicate that it has read the data The assertio of H1 causes the PI/T to eate idicati that it has ackowleded the peripheral s receipt of data The peripheral eates H1 to iform the PI/T that it is oce more ready for data The loads ew data ito the PI/T output reister, ad is asserted aai to idicate a data-ready state Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 6

7 Coordiatio of double bufferi ad hadshaki duri iput The timi diaram depicts two cosecutive iputs cycles usi doublebuffered iput I the first cycle, is eated after H1 has bee asserted, ad asserted automatically after approximately four clock cycles is asserted this secod time because the iput has bee trasferred from the PI/T s iitial iput latches to its fial iput latches, ad the iitial iput latches are oce more ready to accept data However, o the secod iput cycle, remais iactive hih because both iput buffers are full. The output re-asserts itself oly whe the reads from the PI/T ad empties the fial iput latches Data from peripheral valid valid H1iput (Active-low) idicates peripheral has data output (Active-low) idicates PI/T is ready for data is automatically asserted after 4 cycles sice the PI/T is ready to receive more data due to double-bufferi reads data asserted oly after a read to data reister, as both iput buffers are full Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 7

8 Coordiatio of double bufferi ad hadshaki duri output The timi diaram depicts two cosecutive output cycles usi doublebuffered output Iitially both the PI/T s output buffers are empty Whe data is first loaded ito the PI/T by the, the data is trasferred to the IC s output termials ad is asserted Whe the ext write to the PI/T s data reister is made, the data is ot immediately trasferred to the output buffer, ad therefore the PI/T is i a busy state ad caot accept ew data. Oly whe H1 is asserted by the peripheral does the PI/T trasfer its latest data to the output reister. Now the PI/T may oce more accept data from the As i the case of iput trasfers, the kows whe the PI/T is ready for data by examii the state of the H1 fla bit: H1S Data to peripheral Active-low H1 iput idicates peripheral has read data Active-low output idicates PI/T has data for peripheral writes to PI/T s data reister writes to PI/T s data reister (secod time) Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 8

9 Reister model of the Offset R0 $01 Port Mode Cotrol H34 Eable H12 Eable H4 Sese H3 Sese Sese H1 Sese Port Geeral Cotrol Reister R1 $03 SVCRQ Select Iterrupt PFS Port Iterrupt Priority Cotrol Port Service Request Reister R2 $05 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port A Data Directio Reister R3 $07 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port B Data Directio Reister R4 $09 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port C Data Directio Reister R5 $0B Iterrupt Vector Number Iterrupt Source Port Iterrupt Vector Reister R6 $0D Port A Sub-mode Cotrol It. Eable H1 SVRQ H1 Status Ctrl Port A Cotrol Reister R7 $0F Port B Sub-mode H4 Cotrol H4 It. Eable H3 SVRQ H3 Status Ctrl Port B Cotrol Reister R8 $11 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port A Data Reister R9 $13 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port B Data Reister R10 $15 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port A Alterate Reister R11 $17 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port B Alterate Reister R12 $19 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port C Data Reister R13 $1B H4 Level H3 Level Level H1 Level H4S H3S S H1S Port Status Reister $1D (ull) $1F (ull) R14 $21 TOUT/TIACK* Cotrol ZD Cotrol Clock Cotrol Timer Eable Timer Cotrol Reister R15 $23 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer Iterrupt Vector Reister $25 (ull) R16 $27 Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Couter Preload Reister Hih R17 $29 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Couter Preload Reister Middle R18 $2B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Couter Preload Reister Low $2D (ull) R19 $2F Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 Bit 16 Cout Reister Hih R20 $31 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Cout Reister Middle R21 $33 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Cout Reister Low R22 $35 ZDS Timer Status Reister $37 (ull) $39 (ull) $3B (ull) $3D (ull) $3F (ull) Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 9

10 Brief overview of parallel I/O reisters Port Geeral Cotrol Reister (PGCR) Selectio of I/O modes (0, 1, 2 ad 3) ad hadshaki sials (H1,, H3 ad H4) Port Service Request Reister (PSSR) Selectio of Port C fuctios: DMA requests, IRQ/IACK sials ad hadshaki sial priority Port {A,B,C} Data Directio Reister (PxDDR) Selectio of idividual port bits as iputs or outputs Port Iterrupt Vector Reister (PIVR) Storae of vector umber for vectored iterrupts Port {A,B} Cotrol Reister (PxCR) Selectio of port sub-modes ad hadshake sials operatio Port {A,B,C} Data Reister (PxDR) Cotets of the I/O ports Port {A,B} Alterate Data Reister (PxADR) Istataeous loic levels of the I/O pis of the port Port Status Reister (PSR) Status iformatio of the hadshake sials Next lecture Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 10

11 Port Geeral Cotrol Reister PGCR7-PGCR6 Select the operati mode of the PI/T PGCR5-PGCR4 Eables the hadshake pairs H3-H4 ad H1-. These bits have to be set before we ca make use of the cotrol iputs ad outputs. Doi this avoids spurious operatio of the hadshake lies before the PI/T has bee fully cofiured PGCR3-PCGR0 Determie the sese of the four hadshake lies. These cotrol lies ca be prorammed to be active-low or active-hih Bit PGCR7 PGCR6 PGCR5 PGCR4 PGCR3 PGCR2 PGCR1 PGCR0 H4 H3 H1 Fuctio Port mode cotrol H34 eable H12 eable sese Sese Sese Sese PGCR7 PGCR6 Port mode cotrol 0 0 Mode Mode Mode Mode 3 PGCR5 H3, H4 cotrol 0 H34 disable 1 H34 eable PGCR4 H1, cotrol 0 H12 disable 1 H12 eable Sese PGCR3-0 (Assertio Level) 0 LOW 1 HIGH Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 11

12 Port Service Request Reister PSSR6-PSSR5 (service request) Determies whether the PI/T eerates a iterrupt or a DMA request PSSR4-PSSR3 (operatio select) Determies whether two of the dual-fuctio pis belo to port C or perform specialpurpose fuctios PSSR2-PSSR0 (iterrupt-priority cotrol) Bit PSRR7 PSRR6 PSRR5 PSRR4 PSRR3 PSRR2 PSRR1 PSRR0 SRVRQ Fuctio Iterrupt cotrol Port iterrupt priority (DMA cotrol) PSRR6 PSRR5 Iterrupt pi fuctio 0 PC4/DMAREQ* = PC4 DMA ot used 1 0 PC4/DMAREQ* = DMAREQ* Associated with double-buffered trasfers cotrolled by H1 H1 does ot cause iterrups i this mode 1 1 PC4/DMAREQ* = DMAREQ* Associated with double-buffered trasfers cotrolled by H3 H3 does ot cause iterrups i this mode PSRR4 PSRR3 Iterrupt pi fuctio 0 0 PC5/PIRQ* = PC5 No iterrupt support PC6/PIACK* = PC6 No iterrupt support 0 1 PC5/PIRQ* = PIRQ* Autovectored iterrupt supported PC6/PIACK* = PC6 Autovectored iterrupt supported 1 0 PC5/PIRQ* = PC5 PC6/PIACK* = PIACK* 1 1 PC5/PIRQ* = PIRQ* Vectored iterrupt supported PC6/PIACK* = PIACK* Vectored iterrupt supported PSRR2 PSRR1 PSRR0 Order of priority iterrupt Hiuest Lowest H1S S H3S H4S S H1S H3S H4S H1S S H4S H3S S H1S H4S H3S H3S H4S H1S S H3S H4S S H1S H4S H3S H1S S H4S H3S S H1S Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 12

13 Port Data Directio Reisters Port Data Directio Reisters: PADDR,PBDDR ad PCDDR Select the directio ad bufferi characteristics of each of the appropriate port pis A loical ONE makes the correspodi pi act as a OUTPUT A loical ZERO makes the correspodi pi act as a INPUT Port C behaves i the same fashio ad determies whether each dual-fuctio chose for port C operatio is a iput or a output Bit PADDR7 PADDR6 PADDR5 PADDR4 PADDR3 PADDR2 PADDR1 PADDR0 Fuctio Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit PBDDR7 PBDDR6 PBDDR5 PBDDR4 PBDDR3 PBDDR2 PBDDR1 PBDDR0 Fuctio Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit PCDDR7 PCDDR6 PCDDR5 PCDDR4 PCDDR3 PCDDR2 PCDDR1 PCDDR0 Fuctio Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 13

14 Port Iterrupt Vector Reister Whe the parallel port sectio executes a vectored iterrupt, it supplies the with oe of four possible iterrupt vector umbers Each of these umbers is associated with a specific iterrupt cause The upper-order six bits must be supplied by the prorammer The two least-siificat bits are determied by the iterrupt source This arraemet has bee implemeted to avoid the eed for four separate vector umber reisters Bit PIVR7 PIVR6 PIVR5 PIVR4 PIVR3 PIVR2 PIVR1 PIVR0 Fuctio Iterrupt vector umber User defied value Seleted automatically PIVR1 PIVR0 Iterrupt source 0 0 H H3 1 1 H4 Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 14

15 Port Alterate/Data Reisters Port Data Reisters: PADR, PBDR ad PCDR PADR ad PBDR are holdi reisters betwee the side of the PI/T ad its I/O pis ad iteral buffer reisters PCDR is a holdi reister for movi data to ad from port C or its alterate-fuctio pis. The exact ature of a iformatio trasfer depeds o the type of cycle bei executed (read or write) ad o the way i which port C is cofiured Port Alterate Reisters: PAAR ad PBAR Provide aother way of readi the state of ports A ad B. These reisters are READ-ONLY ad their cotets reflect the istataeous loic levels at the I/O pis. These reisters bypass the selected operati modes of ports A ad B: if you wat to kow the state of port A ad B you just read from PAAR or PBAR Port C fuctio Operatio PCDDR = 0 PCDDR = 1 (iput) (output) Read Read output Read pi PCDR reister Write Output reister Output reister PCDR buffer disabled buffer disabled Alterate fuctio PCDDR = 0 PCDDR = 1 (iput) (output) Read pi Read output reister Write to output Write to output reister reister Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 15

16 Port Status Reister PSR7-PSR4 These bits show the istataeous level at the respective hadshake pis, ad are idepedet of hadshake pis sese bits i the PGCR PSR3-PSR0 These bits are the hadshake status bits: H4S-H1S They are set or cleared as specified by the appropriate operati mode For example, if H1 is cofiured as active-low (by cleari bit 0 of the PGCR), a electrically low level at the H1 pi will set PSR0 to 1 to idicate that the status bit HS1 has bee set Bit PSR7 PSR6 PSR5 PSR4 PSR3 PSR2 PSR1 PSR0 Fuctio H4 level H3 level level H1 level H4S H3S S H1S Microprocessor-based System Desi Ricardo Gutierrez-Osua Wriht State Uiversity 16