Lecture 2: MC68000 interrupt in C language

Transcription

1 Lecture 2: MC68000 iterrupt i C lauae Problem defiitio Vectored iterrupts The vector table Itroductio to the PI/T Basic PI/T operatio C lauae solutio Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

2 Problem Setup the PI/T to read data from Port A ad copy to Port B every 5 secods Port A should be prorammed for o-latched iput Port B should be prorammed for sile-buffered output Timer should be setup to iterrupt the MC68000 every 5 secods MC68000 PI/T Read Write Port A Port B Sesor data Motor commad Timer Iterrupt (5 s.) Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

3 Vectored iterrupts Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

4 Vectored iterrupts The provides two iterrupt schemes Vectored: iteded for moder 16-bit peripherals Auto-vectored: iteded for older 8-bit peripherals There are seve levels of iterrupts available The sequece of operatios duri a vectored iterrupt request is the followi A peripheral requires attetio by asserti its iterrupt request output (IRQ*) The priority ecoder produces a 3-bit code with the hihest IRQ* lie active ad passes it to the o the IPL0*-IPL3* iputs The compares the level of the iterrupt with the iterrupt mask fla (I 2 I 1 I 0 ) i the SR. If the requested iput is reater tha (I 2 I 1 I 0 ), the iterrupt is serviced, otherwise it is iored If the decides to service the iterrupt: The code 111 is placed o (FC 2 FC 1 FC 0 ) to iform the system that a iterrupt is about to be serviced The priority of the iterrupt is placed o (A 3 A 2 A 1 ) (FC 2 FC 1 FC 0 ) ad (A 3 A 2 A 1 ) are passed to a iterrupt ackowlede decoder which asserts oe of the seve IACK* lies The asserted IACK* lie iforms the iterrupti device that it is about to be serviced The peripheral whose iterrupt level matches the asserted IACK* will kow that it is oi to be serviced The peripheral the writes the IVEC vector oto the data bus (D 7 D 0 ) ad asserts the DTACK* lie (DTACK stads for Data Trasfer Ackowlede) the active DTACK* termiates the IACK cycle ad the will execute the iterrupt hadler poited by the vector fetched from (D 7 D 0 ) Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

5 The vector table Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

6 Itroductio to the The PI/T (Parallel Iterface/Timer) is a eeral-purpose peripheral Its primary fuctio is a parallel iterface Its secodary fuctio is a prorammable timer The PARALLEL INTERFACE provides 4 modes with various hadshaki ad bufferi capabilities Uidirectioal 8-bit Uidirectioal 16-bit Bidirectioal 8-bit Bidirectioal 16-bit The PROGRAMMABLE TIMER provides a variety of OS services Periodic iterrupt eeratio Square wave eeratio Iterrupt after timeout Elapsed time measuremet System watchdo Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

7 PI/T simplified iterface with the MC68000 Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

8 PI/T simplified iterface with the MC68000 A address decoder places the PI/T at a ive locatio withi the address space of the processor O the SBC68K, the PI/T base address is $FE8000 The is prorammed ad used by readi ad writi data to the correct memory-mapped locatios (reisters) The cotais 23 iteral reisters, which are are selected by the state of 5 reister-select iputs (RS 1 -RS 5 ) coected to the address bus (A 1 -A 5 ) Notice that ALL the reisters are located at ODD memory locatios Oly 9 of the 23 reisters are used for the prorammable timer fuctio Data to the iteral reisters is trasferred throuh the data bus (D 0 -D 7 ) There are three iteral ports Port A ad Port B are used for parallel iterface Port C is shared by timer ad parallel iterface Hadshaki is accomplished throuh lies H 1 -H 4 Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

9 PI/T timer reisters Timer Cotrol Reister (TCR) Determies the operatio modes of the timer Timer Iterrupt Vector Reister (TIVR) Stores the iterrupt vector umber Couter Preload Reister (CPR) A 24-bit couter with the desired (by the prorammer) umber of couts measured i ticks Couter Reister (CNTR) A 24-bit couter dow-couter that is automatically decremeted with every tick Timer Status Reister (TSR) Determies the status of the timer Oly Bit #0 (Zero Detect Status or ZDS) is used I order to clear the ZDS bit after a zero-detect YOU MUST WRITE A 1 to it (YES, the ZDS bit is cleared by writi a ONE to it) Reister ad Memoic Acc. Offset Timer Cotrol Reister TCR R/W $21 Timer Iterrupt Vector Reister TIVR R/W $23 Couter Preload Reister Hih CPRH R/W $27 Couter Preload Reister Middle CPRM R/W $29 Couter Preload Reister Low CPRL R/W $31 Couter Reister Hih CNTRH R $2F Couter Reister Middle CNTRM R $31 Couter Reister Low CNTRL R $33 Timer Status Reister TSR R/W $35 Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

10 Timer Cotrol Reister Timer Eable (TCR0) Turs the timer ON ad OFF. The timer is disabled whe the bit is cleared; it is eabled whe set To start the timer, place a 1 i TCR0 To stop the timer, place a 0 i TCR0 Clock Cotrol (TCR1-2) The PI/T timer permits differet clock pulse operatios. Whe the field is 00, every 32 CPU clock cycles become 1 timer tick. Couter Load (TCR4) After completi its coutdow, the tick couter is either reset from the Couter Preload Reister (CPR) or it rolls over to $FFFFFF Writi a 0 o TCR4 causes a reload from the CPR Writi a 1 o TCR4 causes a roll-over to $FFFFFF. Actio o Zero Detect (TCR5-7) The timer ca select from a series of actios whe the tick couter reaches 0. Mode TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 1 1 X 1 0 X 00 or 1X X 0 X 00 or 1X X 1 1 X 00 or 1X X 1 X X 1 X 0 X X 1 1 X T OUT /TIACK* cotrol Mode 1: Real-time clock Mode 2: Square wave eerator Mode 3: Iterrupt after timeout ZD cotrol Not Clock cotrol used Mode 4: Elapsed time measuremet Mode 5: Pulse couter Mode 6: Period measuremet Timer eable Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

11 Clock cotrol (TCR2-TCR1) The couter ca be decremeted from three differet sials T IN, the exteral clock iput The output of a 5-bit prescaler drive by CLK ad eabled by T IN CLK, the system clock (prescaled) The 5-bit prescaler allows us to divide the couter frequecy by 32 The SBC68K clock rus at 8MHz ( secods per cout), so 1 secod will require 250,000 CLK ticks (mode 00) TCR 2 TCR 1 Clock Cotrol Example 0 0 PC 2 /T IN is a port C fuctio. The couter clock is prescaled by 32, thus the couter clock is CLK/32. The timer eable bit determies whether the timer is i the ru or halt state. CLK Prescaler PC 2 /T IN is a timer iput. The prescaler is decremeted o the falli ede CLK Prescaler of CLK ad the couter is decremeted whe the prescaler rolls over 0 1 from $00 to $1F (31 10 ) Timer is i the ru state whe BOTH timer eable bit ad TIN are asserted. TIN PC 2 /T IN is a timer iput ad is prescaled by 32. The prescaler is decremeted followi the risi trasitio of TIN after bei 1 0 sychroized with the iteral clock. The 24-bit couter is decremeted TIN Prescaler whe the prescaler rolls over from $00 to $1F. The timer eable bit determies whether the timer is i the ru or halt state. PC 2 /T IN is a timer iput ad prescali is ot used. The 24-bit couter is 1 1 decremeted followi the risi ede of the sial at the T IN pi after TIN bei sychroized with the iteral clock. The timer eable bit determies whether the timer is i the ru or halt state. Couter Couter Couter Couter Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

12 T OUT /TIACK* cotrol (TCR7-TCR5) Bits 7-5 of the Timer Cotrol Reister cotrol the way the PI/T timer behaves o a zerodetect (ZDS=1) Whether iterrupts are supported (vectored, auto-vectored or oe) How does the PC3/T OUT output pi behave How is the PC7/TIACK* iput pi iterpreted Timer respose TCR 7 TCR 6 TCR 5 (simplified) 0 0 X Use timer pis for the operatio of I/O port C Tole a square wave 0 1 X with each expiratio of the timer No vectored iterrupt eerated o a cout of 0 Geerate a vectored iterrupt o a cout of 0 No autovectored iterrupt eerated o a cout of 0 Geerate a autovectored iterrupt o a cout of 0 Timer respose (detailed) PC3/T OUT ad PC7/TIACK* are port C fuctios PC3/T OUT is a timer fuctio. I the ru state T OUT provides a square wave which is toled o each zero-detect. The T OUT pi is hih i the halt state. PC7/TIACK* is a port C fuctio. PC3/T OUT is a timer fuctio. I the ru or halt state T OUT is used as a timer request output. Timer iterrupt is disabled, the pi is always three-stated. PC7/TIACK* is a port C fuctio. Sice iterrupt requests are eated, PI/T produces o respose to a asserted TIACK*. PC3/T OUT is a timer fuctio ad is used as a timer iterrupt request output. The timer iterrupt is eabled ad T OUT is low (IRQ* asserted) wheever the ZDS bit is set. PC7/TIACK* is used to detect the IACK cycle. This combiatio operates i the vectored-iterrupt mode. PC3/T OUT is a timer fuctio. I the ru or halt state it is used as a timer iterrupt request output. The timer iterrupt is disabled ad the pi always three-stated. PC7/TIACK* is a port C fuctio. PC3/T OUT is a timer fuctio ad is used as a timer iterrupt request output. The timer iterrupt is eabled ad T OUT is low wheever the ZDS bit is set. PC7/TIACK* is a port C fuctio. This combiatio operates i a autovectored iterrupt mode. Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

13 Parallel I/O eeral descriptio The parallel fuctio has three ports Two idepedet 8-bit ports ( ad B) A third dual-fuctio port C Ports A ad B be ca be used as I/O ports with various hadshaki ad bufferi capabilities i four differet modes Mode 0: Uidirectioal 8-bit Mode 1: Uidirectioal 16-bit Mode 2: Bidirectioal 8-bit Mode 3: Bidirectioal 16-bit Port C ca be used as a simple 8-bit port without hadshaki or double-bufferi a iterrupt iterface to the timer a iterrupt iterface to parallel I/O a support iterface for DMA operatio Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

14 Brief overview of parallel I/O reisters Port Geeral Cotrol Reister (PGCR) Selectio of I/O modes (0, 1, 2 ad 3) ad hadshaki sials (H1, H2, H3 ad H4) Port Service Request Reister (PSSR) Selectio of Port C fuctios: DMA requests, IRQ/IACK sials ad hadshaki sial priority Port {A,B,C} Data Directio Reister (PxDDR) Selectio of idividual port bits as iputs or outputs Port Iterrupt Vector Reister (PIVR) Storae of vector umber for vectored iterrupts Port {A,B} Cotrol Reister (PxCR) Selectio of port sub-modes ad hadshake sials operatio Port {A,B,C} Data Reister (PxDR) Cotets of the I/O ports Port {A,B} Alterate Data Reister (PxADR) Istataeous loic levels of the I/O pis of the port Port Status Reister (PSR) Status iformatio of the hadshake sials Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

15 The PI/T s modes of operatio Mode 0 (1D/8bit) Mode 1 (1D/16bit) Mode 2 (2D/8bit) Mode 3 (2D/16bit) Sub-mode 00 MC68230 A(B) [8] H1(H3) H2(H4) Sub-mode X0 MC68230 H1 H2 A+B [16] H3 H4 MC68230 A [8] B [8] H1 H2 H3 H4 Output Xfers Iput Xfers MC68230 A+B [16] H1 H2 H3 H4 Output Xfers Iput Xfers Sub-mode 01 MC68230 A(B) [8] H1(H3) H2(H4) Sub-mode X1 MC68230 H1 H2 A+B [16] H3 H4 LEGEND Uidirectioal Double-buffered Sub-mode 1X MC68230 A(B) [8] H1(H3) H2(H4) NPd* Bidirectioal Sile-buffered No-latched *NPd: This is the ONLY mode that is Not Pi-defiable Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

16 Port Geeral Cotrol Reister PGCR7-PGCR6 Select the operati mode of the PI/T PGCR5-PGCR4 Eables the hadshake pairs H3-H4 ad H1-H2. These bits have to be set before we ca make use of the cotrol iputs ad outputs. Doi this avoids spurious operatio of the hadshake lies before the PI/T has bee fully cofiured PGCR3-PCGR0 Determie the sese of the four hadshake lies. These cotrol lies ca be prorammed to be active-low or active-hih Bit PGCR7 PGCR6 PGCR5 PGCR4 PGCR3 PGCR2 PGCR1 PGCR0 H4 H3 H2 H1 Fuctio Port mode cotrol H34 eable H12 eable sese Sese Sese Sese PGCR7 PGCR6 Port mode cotrol 0 0 Mode Mode Mode Mode 3 PGCR5 H3, H4 cotrol 0 H34 disable 1 H34 eable PGCR4 H1, H2 cotrol 0 H12 disable 1 H12 eable Sese PGCR3-0 (Assertio Level) 0 LOW 1 HIGH Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

17 Port Data Directio Reisters Port Data Directio Reisters: PADDR,PBDDR ad PCDDR Select the directio ad bufferi characteristics of each of the appropriate port pis A loical ONE makes the correspodi pi act as a OUTPUT A loical ZERO makes the correspodi pi act as a INPUT Port C behaves i the same fashio ad determies whether each dual-fuctio chose for port C operatio is a iput or a output Bit PADDR7 PADDR6 PADDR5 PADDR4 PADDR3 PADDR2 PADDR1 PADDR0 Fuctio Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit PBDDR7 PBDDR6 PBDDR5 PBDDR4 PBDDR3 PBDDR2 PBDDR1 PBDDR0 Fuctio Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit PCDDR7 PCDDR6 PCDDR5 PCDDR4 PCDDR3 PCDDR2 PCDDR1 PCDDR0 Fuctio Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

18 Port Service Request Reister PSSR6-PSSR5 (service request) Determies whether the PI/T eerates a iterrupt or a DMA request PSSR4-PSSR3 (operatio select) Determies whether two of the dual-fuctio pis belo to port C or perform specialpurpose fuctios PSSR2-PSSR0 (iterrupt-priority cotrol) Bit PSRR7 PSRR6 PSRR5 PSRR4 PSRR3 PSRR2 PSRR1 PSRR0 SRVRQ Fuctio Iterrupt cotrol Port iterrupt priority (DMA cotrol) PSRR6 PSRR5 Iterrupt pi fuctio 0 PC4/DMAREQ* = PC4 DMA ot used 1 0 PC4/DMAREQ* = DMAREQ* Associated with double-buffered trasfers cotrolled by H1 H1 does ot cause iterrups i this mode 1 1 PC4/DMAREQ* = DMAREQ* Associated with double-buffered trasfers cotrolled by H3 H3 does ot cause iterrups i this mode PSRR4 PSRR3 Iterrupt pi fuctio 0 0 PC5/PIRQ* = PC5 No iterrupt support PC6/PIACK* = PC6 No iterrupt support 0 1 PC5/PIRQ* = PIRQ* Autovectored iterrupt supported PC6/PIACK* = PC6 Autovectored iterrupt supported 1 0 PC5/PIRQ* = PC5 PC6/PIACK* = PIACK* 1 1 PC5/PIRQ* = PIRQ* Vectored iterrupt supported PC6/PIACK* = PIACK* Vectored iterrupt supported PSRR2 PSRR1 PSRR0 Order of priority iterrupt Hiuest filowest H1S H2S H3S H4S H2S H1S H3S H4S H1S H2S H4S H3S H2S H1S H4S H3S H3S H4S H1S H2S H3S H4S H2S H1S H4S H3S H1S H2S H4S H3S H2S H1S Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

19 Mode 0, sub-mode 00 Data flow Double-buffered iput or Sile-buffered output Applicatios Normally used to receive data from devices such as A/D coverters Hadshaki Data is latched ito the iput reister by the asserted ede of H1 H2 behaves accordi to its prorammi fuctio defied below Port B behaves idetically (usi H3 ad H4) MC68230 A(B) [8] H1(H3) H2(H4) Bit PACR7 PACR6 PACR5 PACR4 PACR3 PACR2 PACR1 PACR0 0 0 H2 Cotrol H2 It. H1 Cotrol fi Sub-mode 00 PACR5 PACR4 PACR3 H2 Cotrol H2S 0 X X Iput pi: Ede-sesitive iput Set o asserted ede Output pi: eated Always clear Output pi: asserted Always clear Output pi: iterlocked iput hadshake Always clear Output pi: pulsed iput hadshake Always clear PACR2 H2 iterrupt 0 H2 iterrupt disabled 1 H2 iterrupt eabled PACR1 PACR0 H1 Cotrol 0 X H1 iterrupt ad DMA request disabled 1 X H1 iterrupt ad DMA request eabled X X H1S status set aytime data is available i the double-buffered iput path Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

20 Mode 0, sub-mode 01 Data flow Double-buffered output or No-latched iput Applicatios Normally used to sed data to devices such as D/A coverters or priters Tables are almost idetical to 0/00 except for PACR0 If PACR0=0, H1S is set whe port A is half-empty If PACR0=1, H1S is set whe port A is full-empty Port B cotrol is idetical (usi H3 ad H4, of course) MC68230 A(B) [8] H1(H3) H2(H4) Bit PACR7 PACR6 PACR5 PACR4 PACR3 PACR2 PACR1 PACR0 0 1 H2 Cotrol H2 It. H1 Cotrol fi Sub-mode 01 PACR5 PACR4 PACR3 H2 Cotrol H2S 0 X X Iput pi: Ede-sesitive iput Set o asserted ede Output pi: eated Always clear Output pi: asserted Always clear Output pi: iterlocked iput hadshake Always clear Output pi: pulsed iput hadshake Always clear PACR2 H2 iterrupt 0 H2 iterrupt disabled 1 H2 iterrupt eabled PACR1 PACR0 H1 Cotrol 0 X H1 iterrupt ad DMA request disabled 1 X H1 iterrupt ad DMA request eabled X 0 H1S status set if either iitial or fial output latches ca accept data ad cleared otherwise X 1 H1S status set if both iitial ad fial output latches are empty ad cleared otherwise Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity

21 Solutio /* Timer Reister Addresses */ #defie tmr ((usied char*) 0xFE8021) /* Timer Base Address */ #defie tcr (( usied char*) tmr) /* Timer Cotrol Re */ #defie tivr (( usied char*) tmr+2) /* Timer Iterrupt Vector Re */ #defie cprh (( usied char*) tmr+6) /* Preload Hi Re */ #defie cprm (( usied char*) tmr+8) /* Preload Mid Re */ #defie cprl (( usied char*) tmr+10) /* Preload Lo Re */ #defie crh (( usied char*) tmr+14) /* Couter Hi Re */ #defie crm (( usied char*) tmr+16) /* Couter Mid Re */ #defie crl (( usied char*) tmr+18) /* Couter Lo Re */ #defie tsr (( usied char*) tmr+20) /* Timer Status Re */ /* Parallel I/O Reister Addresses */ #defie PGCR ( usied char*)0xfe8001 /* PI/T Geeral Cotrol Re */ #defie PSRR ( usied char*)0xfe8003 /* PI/T Service Routie Re */ #defie PIVR ( usied char*)0xfe800b /* PI/T Iterrupt Vector Re */ #defie PSR ( usied char*)0xfe801b /* PI/T Status Re */ #defie PACR ( usied char*)0xfe800d /* PI/T Port A Cotrol Re */ #defie PADDR ( usied char*)0xfe8005 /* Port A Data Directio Re */ #defie PADR ( usied char*)0xfe8011 /* Port A Data Re */ #defie PBCR ( usied char*)0xfe800f /* Port B Cotrol Re */ #defie PBDDR ( usied char*)0xfe8007 /* Port B Data Directio Re */ #defie PBDR ( usied char*)0xfe8013 /* Port B Data Re */ void isr() { pritf("five secs has passed\"); *pbdr = *padr ; /* This is really the mai job of isr * It copies the cotet Port A data reister (our iput port) ad the places it to Port B (our output port)*/ mai () { lo *vtable; it cout= ; asm( move.w #$2400,SR"); asm( movea.l #$20000,SP); *PGCR = 0x0F; /* disable Port A & B */ *PADDR = 0x00; /* Set Port A as iput */ *PBDDR = 0xFF; /* set Port B as Output */ *PSRR = 0x00; /* set PI/T for o Iterrupts */ *PBCR = 0x00; /*0r 0x80*/ /* Set Port B Cotrol */ *PACR = 0x40; /*0r 0x80*/ /* Set Port A Cotrol */ /****Prepare CPU for a iterrupt processi**/ *tivr = 70; vtable = (lo *) (70*4); *vtable = isr; /****Set up timer cotrol reister*/ *tcr = 0xA0; /* Set Timer Mode */ *cprl = (usied char) cout; cout = cout >> 8; /* shift riht 8 bits */ *cprm = (usied char) cout; cout = cout >> 8; /* shift riht 8 bits */ *cprh = (usied char) cout; *tcr = 0xA1; /* Start timer */ } *tsr = 0x01; /* reset the ZDS bit */ asm(" rte"); while (1) { /* Create a ifiite loop which does othi*/ } } Desi of Computi Systems Ricardo Gutierrez-Osua Wriht State Uiversity