Lecture 12: PI/T parallel I/O, part II

Transcription

1 Lecture 12: PI/T parallel I/O, part II Terms ad defiitios PI/T modes of operatio Modes ad sub-modes A example i C lauae Microprocessor-based System Desi Wriht State Uiversity 1

2 Term ad symbol defiitios Pi-defiable Vs. No Pi-defiable Pi-defiable Used whe each pi i a port ca be idividually prorammed to act either as a iput lie or as a output lie. The directio of each pi is defied i the port s PxDDR Not pi-defiable Used whe ALL the bits i the port act as either iput lies or as output lies Latched Vs. No-latched Latched The value read by the CPU at the port reflects the state of the iput pi at the momet is was latched (i.e., whe the iput strobe was asserted) No-latched The value read by the CPU at the port reflects the state of the iput pi at the momet is is read (i.e., istataeous value) Uidirectioal Vs. Bidirectioal Uidirectioal (Modes 0 ad 1) The directio of data flow is determied by the PxDDR ad ca oly be modified by recofiuri this reister Bidirectioal (Modes 2 ad 3): Data ca flow i ay directio ad the cotets of the PxDDR are iored. Primary Data Directio The directio of the data trasfer that permits doublebufferi NPd* I/O port D 0 D 7 Iputs Outputs Iput strobe Uidirectioal Sile-buffered No-latched LEGEND Bidirectioal Pi-defiable Double-buffered *NPd: This is the ONLY mode that is Not Pi-defiable Microprocessor-based System Desi Wriht State Uiversity 2

3 The PI/T s modes of operatio PI/T operati modes PGCR cofi. 0 0 Mode 0 PGCR 0 1 Mode 1 PGCR 1 0 Mode 2 PGCR 1 1 Mode 3 PGCR Mode Uidirectioal 8-bit mode Uidirectioal 16-bit mode Bidirectioal 8-bit mode Bidirectioal 16-bit mode Data reister arraemet A B A B A B A B Submodes 00 Pi-defiable doublebuffered iput or silebuffered output 01 Pi-defiable doublebuffered output or o-latched iput X0 Pi-defiable doublebuffered iput or silebuffered output 01 Pi-defiable doublebuffered output or o-latched iput Port A is pi-defiable sile-buffered output or o-latched iput. Port B is double-buffered bidirectioal I/O Ports A ad B form a sile bidirectioal 16-bit port 1X Pi-defiable silebuffered output or o-latched iput Microprocessor-based System Desi Wriht State Uiversity 3

4 The PI/T s modes of operatio Mode 0 (1D/8bit) Mode 1 (1D/16bit) Mode 2 (2D/8bit) Mode 3 (2D/16bit) Sub-mode 00 A(B) [8] () () Sub-mode X0 A+B [16] A [8] B [8] Output Xfers Iput Xfers A+B [16] Output Xfers Iput Xfers Sub-mode 01 A(B) [8] () () Sub-mode X1 A+B [16] LEGEND Uidirectioal Double-buffered Sub-mode 1X A(B) [8] () () NPd* Bidirectioal Sile-buffered No-latched *NPd: This is the ONLY mode that is Not Pi-defiable Microprocessor-based System Desi Wriht State Uiversity 4

5 Mode 0, sub-mode 00 Data flow Double-buffered iput or Sile-buffered output Applicatios Normally used to receive data from devices such as A/D coverters Hadshaki Data is latched ito the iput reister by the asserted ede of behaves accordi to its prorammi fuctio defied below Port B behaves idetically (usi ad ) A(B) [8] () () Bit PACR7 PACR6 PACR5 PACR4 PACR3 PACR2 PACR1 PACR0 0 0 Cotrol It. Cotrol Sub-mode 00 PACR5 PACR4 PACR3 Cotrol S 0 X X Iput pi: Ede-sesitive iput Set o asserted ede Output pi: eated Always clear Output pi: asserted Always clear Output pi: iterlocked iput hadshake Always clear Output pi: pulsed iput hadshake Always clear PACR2 iterrupt 0 iterrupt disabled 1 iterrupt eabled PACR1 PACR0 Cotrol 0 X iterrupt ad DMA request disabled 1 X iterrupt ad DMA request eabled X X S status set aytime data is available i the double-buffered iput path Microprocessor-based System Desi Wriht State Uiversity 5

6 Mode 0, submode 00: example Cofiure the PI/T i mode 0, sub-mode 00 where Port A Bits 7 ad 6 of port A are used for output Bits 5 to 0 of port A are used for iput Pulsed hadshake is used i the primary directio Hadshake sials of Port A are active-hih Iterrupts are disabled PIT EQU $FE8001 ;PI/T base address o the SBC68K PGCR EQU $00 ;offset of PGCR PACR EQU $0C ;offset of PACG PADDR EQU $04 ;offset of PADDR PADR EQU $10 ;offset of PADR setup LEA PIT,A0 ;A0 poits to the PI/T s base address MOVE.B #% , PGCR(A0) ;setup PGCR for mode 0 operatio MOVE.B #% , PACG(A0) ;setup port A for submode 00 operatio * ;with pulsed output hadshake MOVE.B #% , PADDR(A0) ;setup bits 7,6 as outputs, 0 to 5 as iputs MOVE.B #% , PGCR(A0) ;eable 2 ad make, active-hih * ;ote that 2 is set to eable ad RTS sed MOVE.B D0,PADR(A0) ;write to port A to output bits 7 ad 6 RTS receive MOVE.B PADR(A0),D0 ;read from port A to iput bits 5 to 0 RTS Microprocessor-based System Desi Wriht State Uiversity 6

7 Mode 0, sub-mode 01 Data flow Double-buffered output or No-latched iput Applicatios Normally used to sed data to devices such as D/A coverters or priters Tables are almost idetical to 0/00 except for PACR0 If PACR0=0, S is set whe port A is half-empty If PACR0=1, S is set whe port A is full-empty Port B cotrol is idetical (usi ad, of course) A(B) [8] () () Bit PACR7 PACR6 PACR5 PACR4 PACR3 PACR2 PACR1 PACR0 0 1 Cotrol It. Cotrol Sub-mode 01 PACR5 PACR4 PACR3 Cotrol S 0 X X Iput pi: Ede-sesitive iput Set o asserted ede Output pi: eated Always clear Output pi: asserted Always clear Output pi: iterlocked iput hadshake Always clear Output pi: pulsed iput hadshake Always clear PACR2 iterrupt 0 iterrupt disabled 1 iterrupt eabled PACR1 PACR0 Cotrol 0 X iterrupt ad DMA request disabled 1 X iterrupt ad DMA request eabled X 0 S status set if either iitial or fial output latches ca accept data ad cleared otherwise X 1 S status set if both iitial ad fial output latches are empty ad cleared otherwise Microprocessor-based System Desi Wriht State Uiversity 7

8 Mode 0, sub-mode 1X Data flow Sile-buffered output or No-latched iput Applicatios A simple eeral-purpose bit I/O facility i which the various bits may be used idividually to perform iput or output as required cotrol is ede-sesitive ad plays NO ROLE i ay hadshaki may be prorammed as a ede-sesitive iput that sets bit S whe asserted Port B behaves idetically (usi ad ) A(B) [8] () () Bit PACR7 PACR6 PACR5 PACR4 PACR3 PACR2 PACR1 PACR0 1 X Cotrol It. Cotrol Sub-mode 1X PACR5 PACR4 PACR3 Cotrol S 0 X X Iput pi: Ede-sesitive iput Set o asserted ede 1 X 0 Output pi: eated Always clear 1 X 1 Output pi: asserted Always clear PACR2 iterrupt 0 iterrupt disabled 1 iterrupt eabled PACR1 PACR0 Cotrol 0 X iterrupt disabled 1 X iterrupt eabled X X is ede-sesitive iput: S status set by the asserted ede of Microprocessor-based System Desi Wriht State Uiversity 8

9 Mode 1, sub-mode X0 Data flow Double-buffered iput or Sile-buffered output Port A should cotai the Most Siificat Byte i the word The MOVEP.W PADR(A0),DO istructio will behave as follows: [DO(8:15)] [PADR(A0)] [DO(0:7)] [PBDR(A0)] The operatio of the port is cotrolled by PBCR ad (,) Port A Cotrol Reister used to provide additioal facilities with sials ad A+B [16] Bit PACR7 PACR6 PACR5 PACR4 PACR3 PACR2 PACR1 PACR0 0 0 Cotrol It. Cotrol Sub-mode XX PACR0-PACR5 behave exactly as i Mode 0, submode 1X Bit PBCR7 PBCR6 PBCR5 PBCR4 PBCR3 PBCR2 PBCR1 PBCR0 X 0 Cotrol It. Cotrol Sub-mode X0 PBCR5 PBCR4 PBCR3 Cotrol S 0 X X Iput pi: Ede-sesitive iput Set o asserted ede Output pi: eated Always clear Output pi: asserted Always clear Output pi: iterlocked iput hadshake Always clear Output pi: pulsed iput hadshake Always clear PBCR2 iterrupt 0 iterrupt disabled 1 iterrupt eabled PBCR1 PBCR0 Cotrol 0 X iterrupt ad DMA request disabled 1 X iterrupt ad DMA request eabled X X S status set if data preset i double-buffered iput path Microprocessor-based System Desi Wriht State Uiversity 9

10 Mode 1, sub-mode X1 Data flow Double-buffered output or No-latched iput Writi to the PI/T the MSB should be writte to Port A ad the LSB to port B IN THIS ORDER The operatio of the port is similar to Mode 1/X0 except for PBCR0 A+B [16] Bit PACR7 PACR6 PACR5 PACR4 PACR3 PACR2 PACR1 PACR0 0 0 Cotrol It. Cotrol Sub-mode XX PACR0-PACR5 behave exactly as i Mode 0, submode 1X Bit PBCR7 PBCR6 PBCR5 PBCR4 PBCR3 PBCR2 PBCR1 PBCR0 X 1 Cotrol It. Cotrol Sub-mode X1 PBCR5 PBCR4 PBCR3 Cotrol S 0 X X Iput pi: Ede-sesitive iput Set o asserted ede Output pi: eated Always clear Output pi: asserted Always clear Output pi: iterlocked iput hadshake Always clear Output pi: pulsed iput hadshake Always clear PBCR2 iterrupt 0 iterrupt disabled 1 iterrupt eabled PBCR1 PBCR0 Cotrol 0 X iterrupt ad DMA request disabled 1 X iterrupt ad DMA request eabled X 0 S status set wheever the iitial or fial output latches ca accept ew data ad cleared if both latches are full X 1 S status set whe BOTH the iitial or fial output latch are empty ad cleared if at least oe latch is full Microprocessor-based System Desi Wriht State Uiversity 10

11 Mode 2 Data flow Port A is uidirectioal (directio is determied by PADDR as usual) o-latched iput or sile-buffered output Port B is bidirectioal, double-buffered, o-pi addressable I/O (PBDDR is iored) All the hadshake sials are associated with Port B ad cotrol output trasfers Data writte by the CPU is passed to the peripheral whe the latter asserts ad cotrol iput trasfers Data latched o the asserted ede of A [8] B [8] Output Xfers Iput Xfers Bit PACR7 PACR6 PACR5 PACR4 PACR3 PACR2 PACR1 PACR0 X X mode Iterrupt Cotrol do t care PACR5 PACR4 PACR3 iterrupt S X X 0 Output pi: Iterlocked output hadshake Always cleared X X 1 Output pi: Pulsed output hadshake Always cleared PACR2 iterrupt 0 iterrupt disabled 1 iterrupt eabled PACR1 PACR0 Cotrol 0 X iterrupt ad DMA request disabled 1 X iterrupt ad DMA request eabled X 0 S status set if iitial or fial output latches ca accept data ad cleared otherwise X 1 S status set if both iitial ad fial output latches are empty ad cleared otherwise Bit PBCR7 PBCR6 PBCR5 PBCR4 PBCR3 PBCR2 PBCR1 PBCR0 X X mode Iterrupt Cotrol do t care PBCR5 PBCR4 PBCR3 iterrupt S X X 0 Output pi: Iterlocked output hadshake Always cleared X X 1 Output pi: Pulsed output hadshake Always cleared PBCR2 iterrupt 0 iterrupt disabled 1 iterrupt eabled PBCR1 PBCR0 Cotrol 0 X iterrupt ad DMA request disabled 1 X iterrupt ad DMA request eabled X X S status set if data is available i the double-buffered iput path Microprocessor-based System Desi Wriht State Uiversity 11

12 Mode 3 Data flow Both ports act like a 16-bit bidirectioal, double-buffered, o-pi addressable I/O port Applicatios Relatively hih speed data trasfers Keep i mid that the PI/T-CPU data bus is 8-bit wide so two R/W cycles are ecessary Hadshake sials are similar to Mode 2 ad cotrol output trasfers ad cotrol iput trasfers A+B [16] Output Xfers Iput Xfers Bit PACR7 PACR6 PACR5 PACR4 PACR3 PACR2 PACR1 PACR0 X X mode Iterrupt Cotrol do t care PACR5 PACR4 PACR3 iterrupt S X X 0 Output pi: Iterlocked output hadshake Always cleared X X 1 Output pi: Pulsed output hadshake Always cleared PACR2 iterrupt 0 iterrupt disabled 1 iterrupt eabled PACR1 PACR0 Cotrol 0 X iterrupt ad DMA request disabled 1 X iterrupt ad DMA request eabled X 0 S status set if iitial or fial output latches ca accept data ad cleared otherwise X 1 S status set if both iitial ad fial output latches are empty ad cleared otherwise Bit PBCR7 PBCR6 PBCR5 PBCR4 PBCR3 PBCR2 PBCR1 PBCR0 X X mode Iterrupt Cotrol do t care PBCR5 PBCR4 PBCR3 iterrupt S X X 0 Output pi: Iterlocked output hadshake Always cleared X X 1 Output pi: Pulsed output hadshake Always cleared PBCR2 iterrupt 0 iterrupt disabled 1 iterrupt eabled PBCR1 PBCR0 Cotrol 0 X iterrupt ad DMA request disabled 1 X iterrupt ad DMA request eabled X X S status set if data is available i the double-buffered iput path Microprocessor-based System Desi Wriht State Uiversity 12

13 A example i C lauae Write a C proram to Read data from Port A i a o-latched fashio Write the data from Port A to Port B i a sile-buffered fashio This procedure should be performed periodically every 5 secods USE TIMER INTERRUPTS!!! The vector umber is 70 (decimal) Microprocessor-based System Desi Wriht State Uiversity 13

14 Solutio /* Timer Reister Addresses */ #defie tmr ((usied char*) 0xFE8021) /* Timer Base Address */ #defie tcr (( usied char*) tmr) /* Timer Cotrol Re */ #defie tivr (( usied char*) tmr+?) /* Timer Iterrupt Vector Re */ #defie cprh (( usied char*) tmr+?) /* Preload Hi Re */ #defie cprm (( usied char*) tmr+?) /* Preload Mid Re */ #defie cprl (( usied char*) tmr+??) /* Preload Lo Re */ #defie crh (( usied char*) tmr+??) /* Couter Hi Re */ #defie crm (( usied char*) tmr+??) /* Couter Mid Re */ #defie crl (( usied char*) tmr+??) /* Couter Lo Re */ #defie tsr (( usied char*) tmr+??) /* Timer Status Re */ /* Parallel I/O Reister Addresses */ #defie PGCR ( usied char*)0xfe80?? /* PI/T Geeral Cotrol Re */ #defie PSRR ( usied char*)0xfe80?? /* PI/T Service Routie Re */ #defie PIVR ( usied char*)0xfe80?? /* PI/T Iterrupt Vector Re */ #defie PSR ( usied char*)0xfe80?? /* PI/T Status Re */ #defie PACR ( usied char*)0xfe80?? /* PI/T Port A Cotrol Re */ #defie PADDR ( usied char*)0xfe80?? /* Port A Data Directio Re */ #defie PADR ( usied char*)0xfe80?? /* Port A Data Re */ #defie PBCR ( usied char*)0xfe80?? /* Port B Cotrol Re */ #defie PBDDR ( usied char*)0xfe80?? /* Port B Data Directio Re */ #defie PBDR ( usied char*)0xfe80?? /* Port B Data Re */ void isr() { pritf("five secs has passed\"); *pbdr = *padr ; /* This is really the mai job of isr * It copies the cotet porta data resiter (our iput port) ad the places it to port B (our output port)*/ mai () { lo *vtable; it cout=?; asm( move.w #$2400,SR"); asm( movea.l #$20000,SP); *PGCR = 0x??; /* disable Port A & B */ *PADDR = 0x??; /* Set Port A as iput */ *PBDDR = 0x??; /* set Port B as Output */ *PSRR = 0x??; /* set PI/T for o Iterrupts */ *PBCR = 0x??; /*0r 0x??*/ /* Set Port B Cotrol */ *PACR = 0x??; /*0r 0x??*/ /* Set Port A Cotrol */ /****Prepare CPU for a iterrupt processi**/ *tivr =??; vtable = (lo *) (??*?); *vtable = isr; /****Set up timer cotrol reister*/ *tcr = 0x??; /* Set Timer Mode */ *cprl = (usied char) cout; cout = cout >> 8; /* shift riht 8 bits */ *cprm = (usied char) cout; cout = cout >> 8; /* shift riht 8 bits */ *cprh = (usied char) cout; *tcr = 0x??; /* Start timer */ } *tsr = 0x01; /* reset the ZDS bit */ asm(" rte"); while (1) { /* Create a ifiite loop which does othi*/ } } Microprocessor-based System Desi Wriht State Uiversity 14

15 Solutio /* Timer Reister Addresses */ #defie tmr ((usied char*) 0xFE8021) /* Timer Base Address */ #defie tcr (( usied char*) tmr) /* Timer Cotrol Re */ #defie tivr (( usied char*) tmr+2) /* Timer Iterrupt Vector Re */ #defie cprh (( usied char*) tmr+6) /* Preload Hi Re */ #defie cprm (( usied char*) tmr+8) /* Preload Mid Re */ #defie cprl (( usied char*) tmr+10) /* Preload Lo Re */ #defie crh (( usied char*) tmr+14) /* Couter Hi Re */ #defie crm (( usied char*) tmr+16) /* Couter Mid Re */ #defie crl (( usied char*) tmr+18) /* Couter Lo Re */ #defie tsr (( usied char*) tmr+20) /* Timer Status Re */ /* Parallel I/O Reister Addresses */ #defie PGCR ( usied char*)0xfe8001 /* PI/T Geeral Cotrol Re */ #defie PSRR ( usied char*)0xfe8003 /* PI/T Service Routie Re */ #defie PIVR ( usied char*)0xfe800b /* PI/T Iterrupt Vector Re */ #defie PSR ( usied char*)0xfe801b /* PI/T Status Re */ #defie PACR ( usied char*)0xfe800d /* PI/T Port A Cotrol Re */ #defie PADDR ( usied char*)0xfe8005 /* Port A Data Directio Re */ #defie PADR ( usied char*)0xfe8011 /* Port A Data Re */ #defie PBCR ( usied char*)0xfe800f /* Port B Cotrol Re */ #defie PBDDR ( usied char*)0xfe8007 /* Port B Data Directio Re */ #defie PBDR ( usied char*)0xfe8013 /* Port B Data Re */ void isr() { pritf("five secs has passed\"); *pbdr = *padr ; /* This is really the mai job of isr * It copies the cotet porta data resiter (our iput port) ad the places it to port B (our output port)*/ mai () { lo *vtable; it cout= ; asm( move.w #$2400,SR"); asm( movea.l #$20000,SP); *PGCR = 0x0F; /* disable Port A & B */ *PADDR = 0x00; /* Set Port A as iput */ *PBDDR = 0xFF; /* set Port B as Output */ *PSRR = 0x00; /* set PI/T for o Iterrupts */ *PBCR = 0x00; /*0r 0x80*/ /* Set Port B Cotrol */ *PACR = 0x40; /*0r 0x80*/ /* Set Port A Cotrol */ /****Prepare CPU for a iterrupt processi**/ *tivr = 70; vtable = (lo *) (70*4); *vtable = isr; /****Set up timer cotrol reister*/ *tcr = 0xA0; /* Set Timer Mode */ *cprl = (usied char) cout; cout = cout >> 8; /* shift riht 8 bits */ *cprm = (usied char) cout; cout = cout >> 8; /* shift riht 8 bits */ *cprh = (usied char) cout; *tcr = 0xA1; /* Start timer */ } *tsr = 0x01; /* reset the ZDS bit */ asm(" rte"); while (1) { /* Create a ifiite loop which does othi*/ } } Microprocessor-based System Desi Wriht State Uiversity 15