Computer Architecture. Microcomputer Architecture and Interfacing Colorado School of Mines Professor William Hoff

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1 Computer rchitecture Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff

Computer Hardware Orgaizatio Processor Performs all computatios; coordiates data trasfer Iput devices Sesors, keypads, etc Output devices Motors, LEDs, etc Memory

2 Computer Hardware Orgaizatio Processor Performs all computatios; coordiates data trasfer Iput devices Sesors, keypads, etc Output devices Motors, LEDs, etc Memory RM ad ROM From Huag, HCS/9S Itroductio to Software ad Hardware Iterfacig, 00 Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff

3 Processor (CPU) Cosists of rithmetic logic uit (LU) combiatioal circuit that performs arithmetic ad logic operatios Cotrol uit state machie that geerates cotrol sigals to cotrol the LU ad memory trasfers Registers These are storage locatios i the CPU Sometimes there is a special register called a accumulator that is used for most istructios Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff 3

4 Example LU This LU performs 4 differet operatios o two -bit iputs, ad LU Result Cout The operatio is determied by a two-bit opcode (geerated by the cotrol uit) opcode 00 DD 0 SU 0 ND OR Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff 4

5 Example LU Ci 0 draw with Microsoft Visio 00 = DD 0 = SU 0 = ND = OR 0 Ci X Y Sum dder Cout Resu lt Comparator 0 Cout Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff 5

6 Example DD Ci 0 00 = DD 0 = SU 0 = ND = OR 0 Ci X Y Sum dder Cout Resu lt Comparator 0 Cout Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff 6

7 Example DD ssume CIN= Ci 0 Comparator 0 0 Ci X Sum dder Y Cout = DD 0 = SU 0 = ND = OR Resu lt 0 Cout Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff 7

8 We wat -, or +(-) So we add to the egative of Recall that to egate a two s complemet umber, you ivert all the bits ad add 0 0 Example SU Ci 0 Comparator Ci X Y Sum dder Cout = DD 0 = SU 0 = ND = OR Result Cout Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff 8

9 Example SU Ci = DD 0 = SU 0 = ND = OR 0 ~ Ci X Y Sum dder Cout Resu lt Comparator 0 Cout Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff 9

10 Cotrol Uit The cotrol uit is a little state machie that geerates cotrol sigals for the LU ad memory The sequece of operatios is specified by machie code (the user s program) Clock Cotrol Uit Cotrol sigals Istructio register (IR) holds the fetched istructio Program couter (PC) holds the address of ext istructios IR Data bus PC ddress bus Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff 0

Memory I may computer architectures, IO devices are treated just like memory (this is called memorymapped IO) usses cosist of ddress bus Data bus

11 Memory I may computer architectures, IO devices are treated just like memory (this is called memorymapped IO) usses cosist of ddress bus Data bus Cotrol bus Data bus is bidirectioal (has tri-state drivers) Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff

12 Memory OE output eable WE write eable Memory is a set of registers decoder selects a sigle register, based o the address value The cotets of that register are writte to or read out to the data bus Coceptual model for a 64K memory ^6 = Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff

13 Memory read cycle CPU places address o address bus, ad asserts RD Memory retrieves cotets of that register, places o data bus Memory Timig Memory write cycle CPU places address o address bus, ad data byte oto data bus, the asserts WR Memory latches i value o data bus ito appropriate register WR RD WR RD ssumes the WR ad RD sigals are active low, ad data is latched o risig edge Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff 3

14 data or machie code Simple Program Locatio Cotets Istructio $000 $5 -- $00 $37 -- $000 $6 LD $000 $00 $0 $00 $00 $003 $ DD $00 $004 $0 $005 $0 $006 $43 DEC $007 $7 ST $00 $008 $0 $009 $0 ssembly laguage Meaig of istructios LD $000 (machie code $6,$0,$00) Load accumulator with the cotets of memory at locatio $000 DD $00 (machie code $,$0,$0) dd the cotets of memory at locatio $00 to accumulator DEC (machie code $43) Decremet by ST $00 (machie code $7,$0,$0) Store the value i to memory locatio $00 Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff 4

15 Sequece of Evets for LD Istructio (ssume that the program couter poits to address $000; the start of the LD istructio). The processor puts $000 oto the address bus. The memory respods by puttig $6 o the data bus. Locatio Cotets Istructio $000 $5 -- $000 $6 LD $000 $00 $0 $00 $00 $000 ddress bus CPU Memory... $6 Data bus Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff 5

16 Sequece of Evets for LD Istructio. The processor sees that $6 was fetched, which is the opcode for a LD istructio. It kows that it has to fetch two more bytes for this type of istructio. The processor puts $00 oto the address bus. The memory respods by puttig $0 o the data bus. $00 Locatio Cotets Istructio $000 $5 -- $000 $6 LD $000 $00 $0 $00 $00 ddress bus CPU Memory... $0 Data bus Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff 6

17 Sequece of Evets for LD Istructio 3. The processor puts $00 oto the address bus. The memory respods by puttig $00 o the data bus. Now the processor has fetched the etire istructio. Locatio Cotets Istructio $000 $5 -- $000 $6 LD $000 $00 $0 $00 $00 $00 ddress bus CPU Memory... $00 Data bus Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff 7

18 Sequece of Evets for LD Istructio 4. To execute the istructio, the processor puts $000 oto the address bus. The memory respods by puttig the cotets of $000, which is $5 o the data bus. This is loaded ito the processor s register. Locatio Cotets Istructio $000 $5 -- $000 $6 LD $000 $00 $0 $00 $00 $000 ddress bus CPU Memory... $5 Data bus Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff 8

19 Timig diagram for LD Clock ddress bus (6 bit) Data bus (8 bit) Note as this is ot a real CPU, timig diagram is coceptual oly Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff 9

20 Summary The CPU cosists of rithmetic/logic uit (LU) Cotrol uit Registers Memory (ad devices) are accessed through the address bus, data bus, ad cotrol bus t the lowest level, the CPU executes machie code (we ca better read it by writig it as assembly laguage ) Microcomputer rchitecture ad Iterfacig Colorado School of Mies Professor William Hoff 0

CSC 220: Computer Organization Unit 11 Basic Computer Organization and Design

CSC 220: Computer Organization Unit 11 Basic Computer Organization and Design College of Computer ad Iformatio Scieces Departmet of Computer Sciece CSC 220: Computer Orgaizatio Uit 11 Basic Computer Orgaizatio ad Desig 1 For the rest of the semester, we ll focus o computer architecture: