EMBEDDED MICROCONTROLLERS AND PROCESSOR DESIGN

Transcription

1 EMBEDDED MICROCONTROLLERS AND PROCESSOR DESIGN GREG OSBORN Prentice Hall Upper Saddle River, New Jersey Columbus, Ohio

2 CHAPTER 1 EMBEDDED PROCESSORS 1.0 Microcontrollers Microcontroller Markets DataPath Commercial Microcontrollers SoC Core Processors Relative SoC Unit Volumes Very-Large-Scale Integration (VLSI) Chip Design Tools Intellectual Property Instruction Set Architecture Return on Investment Semiconductor Technology Developments 7 CHAPTER 2 MICROCONTROLLER ARCHITECTURE 2.0 Computer on a Chip John von Neumann von Neumann Architecture Computer Architectures CISC and RISC Semiconductor Technology Small-Scale Integration Hardware Bus Intelligent Peripherals Standardized I/O Interfaces MSI and LSI Electronic Calculator Programmable Calculator Microprocessors Application-Oriented Processing Intel i Intel i Microprocessor Peripherals Microcomputer i8051 Microcontroller IX

3 X CONTENTS 2.9 RISC Introduction RISC Processors RISC Synergy RISC Marketing Fabless Semiconductor Company RISC as Intellectual Property RISC Technology Curve Embedded Controller IP CISC IP RISC IP Third-Party IP Application Specific Processors Summary 28 CHAPTER 3 EMBEDDED MICROCONTROLLER TECHNOLOGY 3.0 Integrated Circuits Moore's Law Microprocessor Performance Enabling Technologies Amdahl's Law Technology Convergence Design Abstraction Instruction Set Architectures Processor Family Tree RISC and CISC Processor Technology Performance Measurement Program Instructions Cost per Instruction Microcoded Instructions Memory Technology Locality Memory Hierarchy Cache Memory LI and L2 Cache Data Registers Instruction Queues Branch Instructions Memory Latency Cache Blocks Instruction Processing Symbolic Assembly Program Compilers Hard-Coded Instructions Program Design Program Code Size Creep CISC Instruction Set Unified Instruction Set Industry Standard Software Instruction Set Extensions RISC Instruction Set Architecture Microcode Micro Instruction Cycles Application Specific Instructions Single-Cycle Instructions 49

4 XI 3.9 Processor Logic Synchronous Logic Register Sets Orthogonal Registers Register Optimization Load/Store Data Operations Processor Functional Partitioning Instruction Pipelining Execution Units Pipeline Stages Pipeline Throughput Sequential Execution Branch Execution Five-Stage Pipeline Instruction Pipeline Stalls Branch Prediction Table Data Pipeline Stall Summary 56 CHAPTER 4 MICROCONTROLLER FUNCTIONS Device Functions Transistor Technology CMOS Transistor CMOS Power Consumption Packaging Operating Temperature Range Memory Technologies DRAM SRAM NVRWM EEPROM FLASH Technology ROM Hardware Features Configuration Word Oscillator Types Reset Standby Modes Low-Power Consumption Watchdog Timer In-Circuit Programming Data Input/Output Parallel I/O Tri-State Bit I/O Memory Mapped I/O Synchronous Serial Communication 70 CHAPTER 5 PROGRAM DESIGN Program Design Polling Program Program Flow Program Timing Sequential Tasks 74

5 XII CONTENTS Task Timing Multiple Sequential Tasks Interrupts Asynchronous Timing Interrupt Enable Machine State Latency Context Switch Interrupt Vector Nested Interrupts Critical Code Interrupt Service Routine Real-Time Operating System Event-Driven System Nucleus System Layering Risk 84 CHAPTER 6 HARDWARE/SOFTWARE DEBUG 6.0 Hardware/Software Debug COTS Controller Tools Embedded Controller Tools First Silicon Board-Level Probes Debug Process Steps Software Editor Compilation Program Build Simulator In-Circuit Emulation SoC Debug Strategies SoC Software Debug Core-Level Debug JTAG/EJTAG Specification 6.7 ARM SoC Debug MIPS SoC Debug EJTAG Functions CHAPTER 7 SERIAL DATA COMMUNICATIONS Serial Data Communication UART Asynchronous Mode Transmit/Receive Buffers SPI - Serial Peripheral Interface I 2 C - Inter-IC Bus How the I 2 C Bus Works I 2 C Bus Terminology Terminology for Bus Transfer CAN Controller Area Network LIN Local Interconnect Network I 2 S Inter-IC Sound I 2 S Serial Data I 2 S Word Select I 2 S Bus Timing 117

6 XIII 7.7 IrDA - Infrared Data Association IrDA Stack USB - Universal Peripheral Bus USB Topology USB Architecture USB Physical Connection USB Interface USB 2.0 Specification Bluetooth Bluetooth Architecture Bluetooth Frequency Bluetooth Network 125 CHAPTER 8 ANALOG TO DIGITAL CONVERSION Analog-to-Digital Conversion Analog-to-Digital Conversion Overview Transducers Low-Pass Filter Active Filter Sampling Shannon's Sampling Theorem What is an ADC? ADC Converter Resolution LSB and MSB Defined Quantization Quantization Error Offset Error Differential Nonlinearity Missing Codes SNR Signal-to-Noise Ratio Analog-to-Digital Conversion Algorithms Successive Approximation SAR ADC Architecture Flash ADC Integrating ADCs Single-Slope Architecture Dual-Slope Architecture Pipeline ADC Sigma-Delta Oversampling 150 CHAPTER 9 DIGITAL SIGNAL PROCESSING Digital Signal Processing What is a DSP? Filtering and Synthesis DSP Performance Analog Signal Conversion DSP Controller Architectures Analog Filters Filter Performance Measurements Time Domain Response Analog Low-Pass Filter Active Analog Filters Active Filter Comparison 163

7 XIV CONTENTS 9.4 Digital Filters Finite Input Response Filter FIR Filter Implementation Convolution Infinite Impulse Response Filter Signal Transformation Phasor Model Fourier Series Discrete Fourier Series Fourier Transform Discrete Fourier Transform Fast Fourier Transform FFT Implementation DFT "Butterfly" Table Addressing 176 CHAPTER 10 FUZZY LOGIC 10.0 Fuzzy Logic Fuzzy Logic Method Fuzzy Perception Fuzzy Logic Terminology Fuzzy Expert System The Inference Process Fuzzification Inference Composition Defuzzification Linguistic Variables Using Linguistic Variables Anatomy of a Fuzzy Rule Logically Combining Linguistic Variables 10.6 PID Controller Linguistic Time of Day Linguistic Comparisons Fuzzy Logic Application How Fuzzy Logic is Used The Rule Matrix Fuzzy Logic Implementation Membership Functions Input Degree of Membership Inferencing Defuzzification Fuzzy Centroid Algorithm Tuning and System Enhancement CHAPTER 11 8-BIT MICROCONTROLLERS General-Purpose Microcontrollers Microchip PIC 18F PIC18F4520 Harvard Architecture Instruction Pipeline Special Features Power Management Modes Oscillator Configuration 206

8 Reset Memory Organization Interrupt Structure Input/Output Ports Timer-Related Functions TimerModules Capture/Compare/PWM Functions Serial Communication Interface MSSP SPI I 2 C EUSART Analog-to-Digital Converter Analog Comparator Special Features of the CPU Instruction Set Electrical Characteristics Z1LOGZ8 Encore! XPF0830 Series ez8 CPU Description The Z8 Encore! CPU Architecture Fetch Unit Execution Unit Address Space Register File Program Memory Data Memory Peripherals Overview Reset Controller and Stop Mode Recovery Low-Power Modes General-Purpose Input/Output GPIO Architecture GPIO Alternate Functions GPIO Interrupts Interrupt Controller Master Interrupt Enable Interrupt Vectors and Priority Timers ONE-SHOT Mode CONTINUOUS Mode COMPARATOR COUNTER Mode PWM SINGLE OUTPUT Mode PWM DUAL OUTPUT Mode CAPTURE Mode CAPTURE RESTART Mode COMPARE Mode GATED Mode CAPTURE/COMPARE Mode Watchdog Timer Analog-to-Digital Converter ADC Operation ADC Timing Comparator 243 i Flash Memory Nonvolatile Data Storage On-Chip Debugger 244

9 XVI CONTENTS Oscillator Control Crystal Oscillator Internal Precision Oscillator ez8 CPU Instructions and Programming Program Stack 247 CHAPTER BIT MICROCONTROLLER bit Processor Overview Freescale SI2XD Processor Overview XGATE Overview XGATE Module XGATE RISC Core XGATE Programmer's Model XGATE Memory Map XGATE Semaphores XGATE Modes of Operation Clocking Clock and Reset Generator (CRG) Pierce Oscillator (XOSC) Analog-to-Digital Convenor (ATD) Enhanced Capture Timer (ЕСТ) Features Pulse-Width Modulator (PWM) Features Interintegrated Circuit (IIC) Features Scalable Controller Area Network (CAN) Features CAN System Serial Communication Interface (SCI) Features Functional Description Data Formats Receiver Transmitter Baud Rate Generator Serial Peripheral Interface (SPI) Features Functional Description Periodic Interrupt Timer (PIT) Features Voltage Regulator (VREG) Features Background Debug Module (BDM) Features Interrupt Module (XINT) Features Interrupt Nesting Mapping Memory Control (MMC) Features Debug (DBG) Features External Bus Interface (XEBI) Features 280

10 XVII Port Integration Module (PIM) Features Port Pin Functional Description Data Register Input Register Data Direction Register Kbyte EEPROM (EETX2K) Features Functional Description EEPROM Module Security Kbyte Flash Module (FTX512K4) Features Security (SEC) Features Modes of Operation Secured Microcontroller Texas Instruments MSP430 Family Low Power Design Flexible Clock System MSP430CPU Operating Modes FLL + Clock Module Flash Memory Controller Hardware Multiplier DMA Controller Digital I/O Watchdog Timer Timers A and В US ART USCI UARTMode SPIMode I 2 C Mode ADC 12 Function DAC Embedded Emulation Module Triggers 307 CHAPTER 13 INTELLECTUAL PROPERTY SoC CORES SoC Overview SoC Design Challenges Configurable Processors SoC Integration Extensible Processors Extensible Processors as RTL Alternatives Explicit Control Scheme The MIPS32 4K Processor Core Family Key Features of the 4KE Family Execution Unit Multiply/Divide Unit (MDU) Memory Manage Unit (MMU) Cache Controller Bus Interface Unit (BIU) Power Management 326

11 XVIII CONTENTS Instruction Cache Data Cache EJTAG Controller System Coprocessor User-Defined Instructions (UDI) Instruction Pipeline Instruction Fetch Execution Memory Fetch Align Writeback Instruction Cache Miss Data Cache Miss Multiply/Divide Operations Branch Delay Memory Management MMU Overview Modes of Operation Virtual Memory Segments User Mode Kernel Mode Debug Mode Overview of the ARM1022E Processor Components of the Processor Integer Unit Registers Integer Core Integer Core Pipeline Prefetch Unit Load/Store Unit Memory Management Unit Caches and Write Buffer Bus Interface Topology Coprocessor Interface Coprocessor Pipeline Debug Unit Halt Mode Monitor Debug-Mode Clocking and PLL ETM Interface Logic Operating States Switching State Switching State During Exception Handling Operating Modes 350 CHAPTER 14 TENSILICA CONFIGURABLE IP CORE Introduction: Moore's Law Revisited Chip Design Process Building the Wrong Chip Fundamental Trends of SoC Design A New SoC for Every System is a Bad Idea Nanometer Technology SoC Design Reform 358

12 XIX SoC Programmability Programmability Versus Efficiency The Key to SoC Design Success An Improved Design Methodology for SoC Design The Configurable Processor as a Building Block Rapid SoC Development Using Automatically Generated Processors The Starting Point: Essential Interfaces and Computation Parallelizing a Task Implications of Automatic Instruction-Set Generation Tensilica Xtensa Architecture Overview Principles of Instruction Set Design Tensilica Xtensa Processor Uniqueness Registers Instruction Width Compound Instructions Branches Instruction Pipeline Limited Instruction Constant Width Short Instruction Format Register Windows Xtensa LX2 Summary 383 CHAPTER 15 DIGITAL SIGNAL PROCESSORS DSP Overview TMS320C55x Characteristics of the TMS320C55x Market Segments DSP Applications Key Features of the C55x Instruction Set Architecture Instruction Pipelining CPU Features Instruction Set Primary Functional Units Instruction Buffer Unit Program Flow Unit Address Data Flow Unit Data Computation Unit Device Special Features Low-Power Dissipation Low-Power Design Memory Accesses Automatic Power Mechanisms Low-Power Enhancements Power Conservation Idle Domains Advanced Technology Processor On-Chip Peripherals On-Chip Memory Analog-to-Digital Converter DSP Clock Generator DMA Controller External Memory Interface I 2 C Module 403

13 Multimedia/SD Card Controller Programmable Timers UART USB Module Emulation and Test Analog Devices ADSP-BF535 Blackfin Processor Portable Low-Power Architecture System Integration Processor Core Instruction Pipeline Instruction Pipeline Flow Memory Architecture Internal (On-Chip) Memory PCI I/O Memory Space Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Interrupt Event Control DMA Controller External Memory Control SDRAM Controller Asynchronous Controller PCI Interface PCI Host Functions PCI Target Function USB Device Real-Time Clock Watchdog Timer Timers Serial Ports Serial Peripheral Interface (SPI) Ports UART Ports Dynamic Power Management Full On Operating Mode Active Operating Mode Sleep Operating Mode Deep Sleep Operating Mode Operating Modes and States 427 INDEX 429