DATASHEET X80120, X Features. Applications. Pinout. Ordering Information

Transcription

1 DTSHEET X80120, X80121 Volage Supervisor/Sequencer Dual Programmable Time Delay wih Local/Remoe Volage Moniors FN8151 Rev 0.00 The X80120 is a volage supervisor/sequencer wih wo buil in volage moniors. This allows he designer o monior up o wo volages and sequence up o hree evens. Low volage deecion circuiry proecs he sysem from power supply failure or brown ou condiions, reseing he sysem and resequencing he volages when any of he moniored inpus fall below he minimum hreshold level. The pin is acive unil all moniored volages reach proper operaing levels and sabilize for a selecable period of ime. Five common low volage combinaions are available, however, Inersil s unique circuis allow he any volage monior hreshold o be reprogrammed for special needs or for applicaions requiring higher precision. manual rese inpu provides debounce circuiry for minimum rese componen coun. civaing he manual rese boh conrols he oupu and resequences he supplies hrough conrol of he ViGDO pins. The X80120 has 2kb of EEPROM for sysem configuraion, manufacuring or mainenance informaion. This memory is proeced o preven inadveren changes o he conens. Pinou V4MON DN V DN QFN PKGE (Top view) V 0 N V SS MR V P (5mm x 5mm) V DN 1 SD WP V1GDO V1MON SL Feaures Dual Volage Monior and Sequencing - Two independen volage moniors - Two ime delay circuis (in circui programmable) - Remoe delay via SMBus - Programmable volage hresholds and delay imes - Sequence up o 3 power supplies. Faul Deecion Regiser - Remoe diagnosics of volage fail even. Debounced Manual Rese Inpu Manufacuring/onfiguraion Memory - 2Kbis of EEPROM - 400kHz SMBus inerface vailable Packages - 20-lead Quad No-Lead Frame (QFN - 5x5mm) pplicaions General Purpose Timers Long Time Delay Generaion ycle Timers / Waveform Generaion ON/OFF Delay Timers Supply Sequencing for Disribued Power Programmable Delay Even Sequencing Muliple D-D ON/OFF Sequencing Volage Window Monioring wih Rese ON/OFF swiches wih Programmable Delay Volage Supervisor wih Programmable Oupu Delays Daabus Power Sequencing 100ms o 5 secs Selecable Delay Swiches TE or Daa cquisiion Timing pplicaions Daapah/Memory Timing pplicaions Daa Pipeline Timing pplicaions Bach Timer/Sequencers djusable Duy ycle pplicaions Ordering Informaion PRT NUMBER V TRIP1 V TRIP4 PKGE X80120Q20I QFN X80121Q20I QFN FN8151 Rev 0.00 Page 1 of 17

2 Block Diagram SD V MR V SS POR LOGI ND DELY ONTROL ND FULT REGISTERS BUS INTERFE SL WP 0 1 V P V1MON V4MON VMON LOGI V REF1 V REF4 OS DIVIDER 4 4 SELET 0.1s 0.5s 1s 5s DELY1 EEPROM 2kbis V SS V1GDO DELY4 DELY IRUIT REPETED 2 TIMES V SS V SS FN8151 Rev 0.00 Page 2 of 17

3 bsolue Maximum Raings Temperaure under bias o +135 Sorage emperaure o +150 V1MON, V4MON pins V V1GDO, pins V pin V SD, SL, WP, 0, 1 pins V MR pin V V P pin v D.. oupu curren m Lead emperaure (soldering, 10 seconds) Recommended Operaing ondiions Temperaure Range (Indusrial) o 85 V o 5.5V UTION: Sresses above hose lised under bsolue Maximum Raings may cause permanen damage o he device. This is a sress raing only; funcional operaion of he device (a hese or any oher condiions above hose lised in he operaional secions of his specificaion) is no implied. Exposure o absolue maximum raing condiions for exended periods may affec device reliabiliy. Elecrical Specificaions (Sandard Seings) Over he recommended operaing condiions unless oherwise specified. SYMBOL PRMETER TEST ONDITIONS MIN TYP MX UNIT D HRTERISTIS V Supply Operaing Range V I Supply urren f SL = 0kHz m V P EEPROM programming volage 9 12 V I P (Noe 3) Programming urren 10 m I LI Inpu Leakage urren (MR) V IL = GND o V 15 µ I LO Oupu Leakage urren (V1GDO,, ) 15 µ V IL Inpu LOW Volage (MR) -0.5 V x 0.3 V V IH Inpu HIGH Volage (MR) V x V V OL OUT (Noe 1) Oupu LOW Volage (, V1GDO, ) Oupu apaciance (, V1GDO, ) I OL = 4.0m 0.4 V V OUT = 0V 8 pf V TRIP1 V1MON Trip Poin Volage (Range) V X V X V V TRIP4 V4MON Trip Poin Volage V ll Versions V VREF (Noe 1) Volage Reference Long Term Drif 10 years mv HRTERISTIS MR (Noe 3) Minimum ime high for rese valid on he MR pin 5 s MRE (Noe 3) DPOR (Noe 3) Delay from MR enable o V1GDO LOW 1.6 s Inernal Device Delay on Power up ms TO (Noe 3) ViGDO urn off ime 50 ns FN8151 Rev 0.00 Page 3 of 17

4 Elecrical Specificaions (Programmable Parameers) Over he recommended operaing condiions unless oherwise specified. SYMBOL PRMETER TEST ONDITIONS MIN TYP MX UNIT SPOR Delay before asserion TPOR1 = 0 TPOR0 = 0 Facory Defaul ms TPOR1 = 0 TPOR0 = 1 (Noe 3) ms TPOR1 = 1 TPOR0 = 0 (Noe 3) s TPOR1 = 1 TPOR0 = 1 (Noe 3) s DELYi Time Delay used in Power Sequencing (i = 1, 4) TiD1 = 0 TiD0 = 0 Facory Defaul ms TiD1 = 0 TiD0 = 1 (Noe 3) ms TiD1 = 1 TiD0 = 0 (Noe 3) s TiD1 = 1 TiD0 = 1 (Noe 3) s Equivalen.. Oupu Load ircui 5V 5V 5V.. Tes ondiions Inpu pulse levels V x 0.1 o V x k 4.6k 4.6k Inpu rise and fall imes 10ns SD V1GDO, Inpu and oupu iming levels V x 0.5 Oupu load Sandard oupu load 30pF 30pF 30pF Iniial Power-up V V TRIPi ViMON DPOR DELYi TO DELYi ViGDO i = 1, 4 FIGURE 1. INITIL POWER UP TIMING FN8151 Rev 0.00 Page 4 of 17

5 MR MR ViGDO DELYi MRE DELYi + SPOR FIGURE 2. MNUL (MR) MR ViMON (i= 1 o 4) DELY1 DELY1 V1GDO DELY4 DELY4 SPOR SPOR ny ViGDO (1s occurance) FIGURE 3. ViGDO, TIMINGS Serial Inerface Over he recommended operaing condiions unless oherwise specified. SYMBOL PRMETER TEST ONDITIONS MIN TYP MX UNIT D HRTERISTIS I 1 cive Supply urren (V ) Read or Wrie o Memory or Rs V IL = V x 0.1 V IH = V x 0.9, f SL = 400kHz 2.5 m I LI Inpu Leakage urren (SL, WP, 0, 1) V IL = GND o V 15 µ I LO Oupu Leakage urren (SD) V SD = GND o V Device is in Sandby 15 µ V IL Inpu LOW Volage (SD, SL, WP, 0, 1) -0.5 V x 0.3 V V IH Inpu HIGH Volage (SD, SL, WP, 0, 1) V x V V HYS Schmi Trigger Inpu Hyseresis Fixed inpu level 0.2 V V relaed level 0.05 x 5 V V OL Oupu LOW Volage (SD) I OL = 4.0m 0.4 V FN8151 Rev 0.00 Page 5 of 17

6 Serial Inerface (oninued)over he recommended operaing condiions unless oherwise specified. (oninued) SYMBOL PRMETER TEST ONDITIONS MIN TYP MX UNIT HRTERISTIS f SL SL lock Frequency 400 khz IN Pulse widh Suppression Time a inpus 50 ns (Noe 1) SL LOW o SD Daa Ou Valid µs BUF (Noe 1) Time he bus is free before sar of new ransmission 1.3 µs LOW lock LOW Time 1.3 µs HIGH lock HIGH Time 0.6 µs SU:ST Sar ondiion Seup Time 0.6 µs HD:ST Sar ondiion Hold Time 0.6 µs SU:DT Daa In Seup Time 100 ns HD:DT Daa In Hold Time 0 µs SU:STO Sop ondiion Seup Time 0.6 µs DH (Noe 1) Daa Oupu Hold Time 50 ns R (Noe 1) SD and SL Rise Time b 300 ns F (Noe 1) SD and SL Fall Time b 300 ns SU:WP WP Seup Time 0.6 µs HD:WP WP Hold Time 0 µs SU:DR 0, 1 Seup Time 0.6 µs HD:DR 0, 1 Hold Time 0 µs SU:VP V P Seup Time 0.6 µs b (Noe 3) apaciive load for each bus line 400 pf W (Noe 2) EEPROM Wrie ycle Time 5 10 ms NOTES: 1. This parameer is based on characerizaion daa. 2. W is he ime from a valid STOP condiion a he end of a wrie sequence o he end of he self-imed inernal nonvolaile wrie cycle. I is he minimum cycle ime o be allowed for any nonvolaile wrie by he user, unless cknowledge Polling is used. 3. This parameer is no 100% esed. Timing Diagrams BUF F HIGH LOW R BUF SL SU:ST SU:DT HD:DT HD:ST SU:STO HD:STO SD IN DH HD:DT SD OUT FIGURE 4. BUS TIMING FN8151 Rev 0.00 Page 6 of 17

7 STRT STOP SL lk 1 lk 9 Slave ddress Bye SD IN SU:WP HD:WP WP SU:DR HD:DR 1, 0 V P SU:VP W FIGURE 5. WP, 0, 1, V P PIN TIMING SL SD 8 h Bi of Las Bye K W Sop ondiion Sar ondiion FIGURE 6. WRITE YLE TIMING Symbol Table WVEFORM INPUTS Mus be seady OUTPUTS Will be seady Pin onfiguraion X80120/21 V 0 N V SS MR May change from LOW o HIGH May change from HIGH o LOW Don are: hanges llowed Will change from LOW o HIGH Will change from HIGH o LOW hanging: Sae No Known V4MON DN V DN (5mm x 5mm) WP V1GDO V1MON SL V P V DN 1 SD FN8151 Rev 0.00 Page 7 of 17

8 Pin Descripions PIN NME DESRIPTION 1 V4 Volage Good Delay Oupu (cive LOW). This open drain oupu goes HIGH when V4MON is less han V REF4 and goes LOW when V4MON is greaer han V REF4. There is user selecable delay circuiry on his pin. 2 V4MON V4 Volage Monior Inpu. Second volage monior pin. If unused connec o V. 3 DN Do No onnec 4 V onnec o V. 5 DN Do No onnec. 6 V P EEPROM programming Volage. 7 V onnec o V. 8 DN Do No onnec. 9 1 ddress Selec Inpu. I has an inernal pull-down resisor. (>10M ypical) The 0 and 1 bis allow for up o 4 X80120 devices o be used on he same SMBus serial inerface. 10 SD Serial Daa. SD is a bidirecional pin used o ransfer daa ino and ou of he device. I has an open drain oupu and may be wire ORed wih oher open drain or open collecor oupus. This pin requires a pull up resisor and he inpu buffer is always acive (no gaed). 11 SL Serial lock. The Serial lock conrols he serial bus iming for daa inpu and oupu. 12 V1MON V1 Volage Monior Inpu. Firs volage monior pin. If unused connec o V. 13 V1GDO V1 Volage Good Delay Oupu (cive LOW). This open drain oupu goes HIGH when V1MON is less han V REF1 and goes LOW when V1MON is greaer han V REF1. There is user selecable delay circuiry on his pin. 14 Oupu. This open drain pin is an acive LOW oupu. This pin will be acive unil all ViGDO pins go inacive and he power sequencing is complee. This pin will be released afer a programmable delay. 15 WP Wrie Proec. Inpu Pin. WP HIGH (in conjuncion wih WPEN bi=1) prevens wries o any memory locaion in he device. I has an inernal pull-down resisor. (>10M ypical) 16 MR Manual Rese. Pulling he MR pin HIGH iniiaes a. The MR signal mus be held HIGH for 5 secs. I has an inernal pull-down resisor. (>10M ypical) 17 V SS Ground Inpu. 18 N No onnec. No inernal connecions ddress Selec Inpu. I has an inernal pull-down resisor. (>10M ypical) The 0 and 1 bis allow for up o 4 X80120 devices o be used on he same SMBus serial inerface. 20 V Supply Volage. Funcional Descripion Power On Rese and Sysem Rese Wih Delay pplicaion of power o he X80120 acivaes a Power On Rese circui ha pulls he pin acive. This signal, if used, prevens he sysem microprocessor from saring o operae while here is insufficien volage on any of he supplies. This circui also does he following: I prevens he processor from operaing prior o sabilizaion of he oscillaor. I allows ime for an FPG o download is configuraion prior o iniializaion of he circui. I prevens communicaion o he EEPROM during unsable power condiions, grealy reducing he likelihood of daa corrupion on power up. I allows ime for all supplies o urn on and sabilize prior o sysem iniializaion. The POR/ circui is acivaed when all volages are wihin specified ranges and he V1GDO and ime-ou condiions are me. The POR/ circui will hen wai SPOR and de-asser he pin. The POR delay may be changed by seing he TPOR bis in regiser R2. The delay can be se o 100ms, 500ms, 1 second, or 5 seconds. TBLE 1. POR DELY OPTIONS TPOR1 TPOR0 SPOR DELY BEFORE SSERTION miliseconds (defaul) miliseconds second seconds FN8151 Rev 0.00 Page 8 of 17

9 Manual Rese The manual rese opion allows a hardware rese of he power sequencing pins. These can be used o recover he sysem in he even of an abnormal operaing condiion. civaing he MR pin for more han 5 s ses all of he ViGDO oupus and he oupu acive (LOW). When MR is released (and if all supplies are sill a heir proper operaing volage) hen he ViGDO and pins will be released afer heir programmed delay periods. Dual Volage Monioring X80120 moniors 2 volage inpus. When he V1MON or V4MON inpu is deeced o be above he inpu hreshold, he respecive oupu (V1GDO or ) goes inacive (LOW). The ViGDO signal is de-assered afer a delay of 100ms. This delay can be changed on each ViGDO oupu individually wih bis in regiser R3. The delay can be 100ms, 500ms, 1s and 5s. Each ViGDO signal remains acive unil is associaed ViMON inpu rises above he hreshold. TBLE 2. ViGDO OUTPUT TIME DELY OPTIONS inpus o he X The ViMON inpus monior he volage o make sure i has reached he minimum desired level. When each volage monior deermines ha is inpu is good, a couner sars. fer he programmed delay ime, he X80120 ses he ViGDO signals LOW. The ViGDO signals can be wire ORed ogeher and ied o an inerrup on he microconroller. ny individual volage failure can be viewed in he Faul Deecion Regiser. In he facory defaul condiion, each ViGDO oupu is insruced o go LOW 100ms afer he inpu volage reaches is hreshold. However, each ViGDO delay is individually selecable as 100ms, 500ms, 1s and 5s. The delay imes are charged via he SMBus during calibraion of he sysem. Power Supplies 5V 3.3V On/Off 1.2V On/Off TiD1 TiD0 DELYi ms (defaul) ms secs secs where i is he specific volage monior (i = 1, 4). X80120/21 V4MON µ V 1 IRQ Faul Deecion The X80120 conains a Faul Deecion Regiser (FDR) ha provides he user he saus of he causes for a pin acive (See Table 20). power-up, he FDR is defauled o all 0. The sysem needs o iniialize he regiser o 09h before he acual monioring can ake place. In he even ha any one of he moniored sources fail, he corresponding bi in he regiser changes from a 1 o a 0 o indicae he failure. When a is deeced by he main conroller, he conroller should read he FDR and noe he cause of he faul. fer reading he regiser, he conroller can rese he regiser bi back o all 1 in preparaion for fuure failure condiions. Flexible Power Sequencing of Muliple Power Supplies The X80120 provides several circuis such as muliple volage moniors, programmable delays, and oupu drive signals ha can be used o se up flexible power monioring or sequencing schemes sysem power supplies. Below are wo examples: 1. Power Up of Supplies In Parallel Using Programmable Delays. (See Figure 7 and Figure 8). V1GDO V1MON MR V 1 V 2 FPG SI V 1 FIGURE 7. EXMPLE PPLITION OF PRLLEL POWER ONTROL 2. Power Up of Supplies Via Relay Sequencing Using Volage Moniors (see Figure 9 and Figure 10). Several power supplies and heir respecive power up sar imes can be conrolled using he X80120 such ha each of he power supplies will sar in a relay sequencing fashion. In he following example, he 1s supply is allowed o power up when he inpu regulaed supply reaches an accepable hreshold. Subsequen supplies power up afer he prior supply has reached is operaing volage. This configuraion ensures ha each subsequen power supply urns on afer he preceding supplies volage oupu is valid. gain, he X80120 offers programmable delays for each volage monior and his delay is selecable via he SMBus during calibraion of he sysem. The X80120 moniors several power supplies, powered by he same source volage, ha all begin power up a he same ime. Each volage source is fed ino he ViMON FN8151 Rev 0.00 Page 9 of 17

10 V1MON an hoose Differen Delays for each Volage Monior 12V Power Supply 5V µ V 1 DELY1 V1GDO Programmable Delay 100ms 500ms 1 sec 5 secs Power 1.2V Supply On/Off V 2 FPG V4MON DELY4 SPOR Programmable Delay Timing no o scale Programmable Delay 5V Power 3.3V Supply On/Off V X80120/21 V4MON V1GDO V1MON MR V 1 V 2 SI V 1 V 2 FIGURE 8. PRLLEL POWER ONTROL - TIMING FIGURE 9. EXMPLE OF RELY POWER SUPPLY SEQUENING V 1 MON (5V) DELY1 V1MON hreshold Programmable Delay 100ms 500ms 1sec 5sec Timing No To Scale Example: Two Independen Power Supplies in relay iming V1GDO Power Supply #2 ON Power Supply #2 OUTPUT (1.2V) DELY4 V4MON hreshold Programmable Delay 100ms 500ms 1sec 5sec Power Supply #3 ON Power Supply #3 OUTPUT (3.3V SPOR FIGURE 10. RELY SEQUENING OF D-D SUPPLIES (TIMING) FN8151 Rev 0.00 Page 10 of 17

11 onrol Regisers and Memory The user addressable inernal conrol, saus and memory componens of he X80120 can be spli up ino hree pars: onrol Regiser (R) Faul Deecion Regiser (FDR) EEPROM array Regisers The onrol Regisers and Faul Deecion Regiser are summarized in Table 4. hanging bis in hese regisers change he operaion of he device or clear faul condiions. Reading bis from hese regisers provides informaion abou device configuraion or faul condiions. Reads and wries are done hrough he SMBus serial por. ll of he onrol Regiser bis are nonvolaile (excep for he WEL bi), so hey do no change when power is removed. The values of he Regiser Block can be read a any ime by performing a random read (see Serial Inerface) a he specific bye address locaion. Only one bye is read by each regiser read operaion. Bis in he regisers can be modified by performing a single bye wrie operaion direcly o he address of he regiser and only one daa bye can change for each regiser wrie operaion.eeprom rray. The X80120 conains a 2kbi EEPROM memory array. This array can conain informaion abou manufacuring locaion and daes, board configuraion, faul condiions, service hisory, ec. ccess o his memory is hrough he SMBus serial por. Read and wrie operaions are similar o hose of he conrol regisers, bu a single command can wrie up o 16 byes a one ime. single read command can reurn he enire conens of he EEPROM memory. Regiser and Memory Proecion In order o reduce he possibiliy of inadveren changes o eiher a conrol regiser of he conens of memory, several proecion mechanisms are buil ino he X These are a Wrie Enable Lach, Block Proec bis, a Wrie Proec Enable bi and a Wrie Proec pin. WEL: Wrie Enable Lach wrie enable lach (WEL) bi conrols wrie accesses o he nonvolaile regisers and he EEPROM memory array in he X This bi is a volaile lach ha powers up in he LOW (disabled) sae. While he WEL bi is LOW, wries o any address (regisers or memory) will be ignored. The WEL bi is se by wriing a 1 o he WEL bi and zeroes o he oher bis of he conrol regiser 0 (R0). I is imporan o wrie only 00h or 80h o he R0 regiser. Once se, WEL remains se unil eiher i is rese o 0 (by wriing a 0 o he WEL bi and zeroes o he oher bis of he conrol regiser) or unil he par powers up again. Noe, a wrie o FDR or RSR does no require ha WEL=1. BP1 and BP0: Block Proec Bis The Block Proec Bis, BP1 and BP0, deermines which blocks of he memory array are wrie proeced. wrie o a proeced block of memory is ignored. The block proec bis will preven wrie operaions o one of four segmens of he array. BP1 BP0 PROTETED DDRESSES (SIZE) WPEN: Wrie Proec Enable The Wrie Proec pin and Wrie Proec Enable bi in he R1 regiser conrol he Programmable Hardware Wrie Proec feaure. Hardware Proecion is enabled when he WP pin is HIGH and WPEN bi is HIGH and disabled when WP pin is LOW or he WPEN bi is LOW. When he chip is Hardware Wrie Proeced, non-volaile wries o all conrol regisers (R1, R2, and R3) are disabled including BP bis, he WPEN bi iself, and he blocked secions in he memory rray. Only he secion of he memory array ha are no block proeced can be wrien. Non Volaile Programming Volage (V P ) RRY LOK 0 0 None (Defaul) None (Defaul) 0 1 0h - FFh (64 byes) Upper 1/ h - FFh (128 byes) Upper 1/ h - FFh (256 byes) ll Nonvolaile wries require ha a programming volage be applied o he VP for he duraion of a nonvolaile wrie operaion. TBLE 3. WRITE PROTET ONDITIONS WEL WP WPEN MEMORY RRY NOT BLOK PROTETED MEMORY RRY BLOK PROTETED WRITES TO R1, R2, R3 PROTETION LOW X X Wries Blocked Wries Blocked Wries Blocked Hardware HIGH LOW X Wries Enabled Wries Blocked Wries Enabled Sofware HIGH X LOW Wries Enabled Wries Blocked Wries Enabled Sofware HIGH HIGH HIGH Wries Enabled Wries Blocked Wries Blocked Hardware FN8151 Rev 0.00 Page 11 of 17

12 BYTE DDR. NME ONTROI/STTUS TBLE 4. REGISTER DDRESS MP BIT MEMORY TYPE 00H R0 Wrie Enable WEL Volaile 01H R1 EEPROM Block onrol WPEN 0 0 BP1 BP EEPROM 02H R2 POR Timing TPOR1 TPOR0 0 0 EEPROM 03H R3 ViGDO TIme Delay T4D1 T4D T1D1 T1D0 EEPROM FF FDR Faul Deecion Regiser V40S 0 0 V10S Volaile TBLE 5. HRDWRE/SOFTWRE ONTROL ND FULT DETETION BITS SUMMRY OPERTION SOFTWRE ONTROL BITS ONTROL/ STTUS LOTION(S) REGISTER BITS DESRIPTION (SEE FUNTIONL FOR DETILS) EEPROM Wrie Enable WEL R0 7 WEL = 1 enables wrie operaions o he conrol regisers and EEPROM. WEL = 0 prevens wrie operaions. EEPROM Wrie Proec WPEN R1 7 WPEN = 1 (and WP pin HIGH) prevens wries o he conrol regisers and he EEPROM. EEPROM Block Proec Time Delay V1GDO Time Delay Time Delay STTUS BITS BP1 BP0 TPOR0 TPOR1 T1D0 T1D1 T4D0 T4D1 R1 4:3 BP1=0, BP0=0 : No EEPROM memory proeced. BP1=0, BP0=1 : Upper 1/4 of EEPROM memory proeced BP1=1, BP0=0 : Upper 1/2 of EEPROM memory proeced. BP1=1, BP0=1 : ll of EEPROM memory proeced. R2 3:2 TPOR1=0, TPOR0=0 : delay = 100ms TPOR1=0, TPOR0=1 : delay = 500ms TPOR1=1, TPOR0=0 : delay = 1s TPOR1=1, TPOR0=1 : delay = 5s R3 1:0 TiD1=0, TiD0=0 : ViGDO delay = 100ms TiD1=0, TiD0=1 : ViGDO delay = 500ms R3 7:6 TiD1=1, TiD0=0 : ViGDO delay = 1s TiD1=1, TiD0=1 : ViGDO delay = 5s 1s Volage Monior V1OS FDR 0 V1OS = 0 : V1GDO pin has been assered (mus be prese o 1). 4h Volage Monior V4OS FDR 3 V4OS = 0 : pin has been assered (mus be prese o 1). Bus Inerface Informaion Inerface onvenions The device suppors a bidirecional bus oriened proocol. The proocol defines any device ha sends daa ono he bus as a ransmier, and he receiving device as he receiver. The device conrolling he ransfer is called he maser and he device being conrolled is called he slave. The maser always iniiaes daa ransfers, and provides he clock for boh ransmi and receive operaions. Therefore, he devices in his family operae as slaves in all applicaions. I should be noed ha he ninh clock cycle of he read operaion is no a don care. To erminae a read operaion, he maser mus eiher issue a STOP condiion during he ninh cycle or hold SD HIGH during he ninh clock cycle and hen issue a STOP condiion. Serial lock and Daa Daa saes on he SD line can change only during SL LOW. SD sae changes during SL HIGH are reserved for indicaing STRT and STOP condiions (See Figure 11). Serial Sar ondiion ll commands are preceded by he STRT condiion, which is a HIGH o LOW ransiion of SD when SL is HIGH. The device coninuously moniors he SD and SL lines for he STRT condiion and does no respond o any command unil his condiion has been me. On power up, he SL pin mus be brough LOW prior o he STRT condiion. Serial Sop ondiion ll communicaions mus be erminaed by a STOP condiion, which is a LOW o HIGH ransiion of SD when SL is HIGH, followed by a HIGH o LOW on SL. fer going LOW, SL FN8151 Rev 0.00 Page 12 of 17

13 can say LOW or reurn HIGH. The STOP condiion also places he device ino he Sandby power mode afer a read sequence. SL from Maser Serial cknowledge cknowledge is a sofware convenion used o indicae successful daa ransfer. The ransmiing device, eiher maser or slave, will release he bus afer ransmiing eigh bis. During he ninh clock cycle, he receiver will pull he SD line LOW o acknowledge ha i received he eigh bis of daa (See Figure 12). The device will respond wih an acknowledge afer recogniion of a STRT condiion and if he correc Device Idenifier and Selec bis are conained in he Slave ddress Bye. If a wrie operaion is seleced, he device will respond wih an acknowledge afer he receip of each subsequen eigh bi word. The device will acknowledge all incoming daa and address byes, excep for he Slave ddress Bye when he Device Idenifier and/or Selec bis are incorrec. The device does no acknowledge any insrucions following a non-volaile wrie operaion, unless he V P pin has he recommended programming volage applied for he duraion of he wrie cycle. In he read mode, he device will ransmi eigh bis of daa, release he SD line, hen monior he line for an acknowledge. If an acknowledge is deeced and no STOP condiion is generaed by he maser, he device will coninue o ransmi daa. The device will erminae furher daa ransmissions if an acknowledge is no deeced. The maser mus hen issue a STOP condiion o reurn he device o Sandby mode and place he device ino a known sae. SL SD Sar Sop Daa Oupu from Transmier Daa Oupu from Receiver Sar Device ddressing cknowledge FIGURE 12. KNOWLEDGE RESPONSE FROM REEIVER ddressing Proocol Overview Depending upon he operaion o be performed on each of hese individual pars, a 1, 2 or 3 Bye proocol is used. ll operaions however mus begin wih he Slave ddress Bye being clocked ino he SMBus por on he SL and SD pins. The Slave address selecs he par of he device o be addressed, and specifies if a Read or Wrie operaion is o be performed. Slave ddress Bye Following a STRT condiion, he maser mus oupu a Slave ddress Bye. This bye consiss of hree pars: The Device Type Idenifier which consiss of he mos significan four bis of he Slave ddress (S7 - S4). The Device Type Idenifier MUST be se o 1010 in order o selec he device. The nex wo bis (S3 - S2) are slave address bis. The bis received via he SMBus are compared o 0 and 1 pins and mus mach or he communicaion is abored. The nex bi, S1, selecs he device memory secor. There are wo addressable secors: he memory array and he conrol, faul deecion and remoe shudown regisers. The Leas Significan Bi of he Slave ddress (S0) Bye is he R/W bi. This bi defines he operaion o be performed. When he R/W bi is 1, hen a RED operaion is seleced. 0 selecs a WRITE operaion (Refer o Figure 13). FIGURE 11. VLID STRT ND STOP ONDITIONS FN8151 Rev 0.00 Page 13 of 17

14 Device Type Idenifier S7 S6 S5 S4 S3 S2 S1 S INTERNL DDRESS (S1) Exernal Device ddress Memory Selec 1 0 MS RED / WRITE R/W INTERNLLY DDRESSED DEVIE 0 EEPROM rray 1 onrol Regiser, Faul Deecion Regiser BIT S0 OPERTION 0 WRITE 1 RED FIGURE 13. SLVE DDRESS FORMT Serial Wrie Operaions Before any wrie operaions can be performed, a programming supply volage (V P ) mus be supplied. This volage is only needed for programming, bu he nonvolaile regisers and EEPROM locaions canno be programmed wihou i. In order o successfully complee a wrie operaion o eiher a onrol Regiser or he EEPROM array, he Wrie Enable Lach (WEL) bi mus firs be se and eiher he WP pin or he WPEN bi mus be LOW. Wries o he WEL bi do no cause a high volage wrie cycle, so he device is ready for he nex operaion immediaely afer he STOP condiion. BYTE WRITE For a wrie operaion, he device requires he Slave ddress Bye and a Word ddress Bye. This gives he maser access o any one of he words in he array. fer receip of he Word ddress Bye, he device responds wih an acknowledge, and awais he nex eigh bis of daa. fer receiving he 8 bis of he Daa Bye, he device again responds wih an acknowledge. The maser hen erminaes he ransfer by generaing a STOP condiion, a which ime he device begins he inernal wrie cycle o he nonvolaile memory. During his inernal wrie cycle, he device inpus are disabled, so he device will no respond o any requess from he maser. The SD oupu is a high impedance. PGE WRITE The device is capable of a page wrie operaion (See Figure 14). I is iniiaed in he same manner as he bye wrie operaion; bu insead of erminaing he wrie cycle afer he firs daa bye is ransferred, he maser can ransmi an unlimied number of 8-bi byes. fer he receip of each bye, he device will respond wih an acknowledge, and he address is inernally incremened by one. The page address remains consan. When he couner reaches he end of he page, i rolls over and goes back o 0 on he same page (See Figure 15). This means ha he maser can wrie 16 byes o he page saring a any locaion on ha page. If he maser begins wriing a locaion 10, and loads 12 byes, hen he firs 6 byes are wrien o locaions 10 hrough 15, and he las 6 byes are wrien o locaions 0 hrough 5. ferwards, he address couner would poin o locaion 6 of he page ha was jus wrien. If he maser supplies more han 16 byes of daa, hen new daa overwries he previous daa, one bye a a ime. The maser erminaes he Daa Bye loading by issuing a STOP condiion, which causes he device o begin he nonvolaile wrie cycle. s wih he bye wrie operaion, all inpus are disabled unil compleion of he inernal wrie cycle. STOPS ND WRITE MODES Sop condiions ha erminae wrie operaions mus be sen by he maser afer sending a leas 1 full daa bye plus he subsequen K signal. If a STOP is issued in he middle of a daa bye, or before 1 full daa bye plus is associaed K is sen, hen he device will rese iself wihou performing he wrie. The conens of he array will no be effeced. KNOWLEDGE POLLING The disabling of he inpus during high volage cycles can be used o ake advanage of he ypical 5ms wrie cycle ime. Once he STOP condiion is issued o indicae he end of he maser s bye load operaion, he device iniiaes he inernal high volage cycle. cknowledge polling can be iniiaed immediaely. To do his, he maser issues a STRT condiion followed by he Slave ddress Bye for a wrie or read operaion. If he device is sill busy wih he high volage cycle hen no K will be reurned. If he device has compleed he wrie operaion, an K will be reurned and he hos can hen proceed wih he read or wrie operaion (See Figure 18). wrie o a proeced block of memory will suppress he acknowledge bi. FN8151 Rev 0.00 Page 14 of 17

15 Signals from he Maser S a r Slave ddress Bye ddress Daa (1) (1 o n o 16) Daa (n) S o p SD Bus Signals from he Slave K K K K FIGURE 14. PGE WRITE OPERTION 7 Byes 5 Byes address = 6 address poiner ends here ddr = 7 address 10 address n-1 FIGURE 15. WRITING 12 BYTES TO 16-BYTE PGE STRTING T LOTION 10 Signals from he Maser S a r Slave ddress Bye ddress S a r Slave ddress S o p SD Bus Signals from he Slave K K K Daa FIGURE 16. RNDOM DDRESS RED SEQUENE Signals from he Maser S a r Slave ddress S o p SD Bus Signals from he Slave K Daa FIGURE 17. URRENT DDRESS RED SEQUENE FN8151 Rev 0.00 Page 15 of 17

16 URRENT DDRESS RED Inernally he device conains an address couner ha mainains he address of he las word read incremened by one. Therefore, if he las read was o address n, he nex read operaion would access daa from address n+1. On power up, he address of he address couner is undefined, requiring a read or wrie operaion for iniializaion. Bye Load ompleed by Issuing STOP. Ener K Polling Issue STRT Issue Slave ddress Bye (Read or Wrie) K Reurned? NO Issue STOP Upon receip of he Slave ddress Bye wih he R/W bi se o one, he device issues an acknowledge and hen ransmis he eigh bis of he Daa Bye. The maser erminaes he read operaion when i does no respond wih an acknowledge during he ninh clock and hen issues a STOP condiion (See Figure 17 or he address, acknowledge, and daa ransfer sequence). YES Operaional Noes The device powers-up in he following sae: High Volage ycle omplee. oninue ommand Sequence? NO Issue STOP The device is in he low power sandby sae. The WEL bi is se o 0. In his sae i is no possible o wrie o he device. YES SD pin is he inpu mode. Daa Proecion The following circuiry has been included o preven inadveren wries: oninue Normal Read or Wrie ommand Sequence PROEED FIGURE 18. KNOWLEDGE POLLING SEQUENE Serial Read Operaions Read operaions are iniiaed in he same manner as wrie operaions wih he excepion ha he R/W bi of he Slave ddress Bye is se o one. There are hree basic read operaions: urren ddress Reads, Random Reads, and Sequenial Reads. The WEL bi mus be se o allow wrie operaions. The proper clock coun and bi sequence is required prior o he STOP bi in order o sar a nonvolaile wrie cycle. The WP pin, when held HIGH, prevens all wries o he array and all he Regiser. programming volage mus be applied o he V P pin prior o any programming sequence. RNDOM RED Random read operaion allows he maser o access any memory locaion in he array. Prior o issuing he Slave ddress Bye wih he R/W bi se o one, he maser mus firs perform a dummy wrie operaion. The maser issues he STRT condiion and he Slave ddress Bye, receives an acknowledge, hen issues he Word ddress Byes. fer acknowledging receips of he Word ddress Byes, he maser immediaely issues anoher STRT condiion and he Slave ddress Bye wih he R/W bi se o one. This is followed by an acknowledge from he device and hen by he eigh bi word. The maser erminaes he read operaion by no responding wih an acknowledge and hen issuing a STOP condiion (See Figure 16 for he address, acknowledge, and daa ransfer sequence). FN8151 Rev 0.00 Page 16 of 17

17 Packaging Informaion 20-Lead Quad Fla No Lead Package (Package ode: Q20) 5mm x 5mm Body wih 0.65mm Lead Pich Pin 1 Inden 3 1 b E E2 e Noe: D 1. The package ouline drawing is compaible wih JEDE MO-220; variaions: WHH-2, excep dimensions D2 and E2. y SYMBOLS D2 L DIMENSIONS IN MILLIMETERS MIN NOM MX 2. The erminal #1 idenifier is a laser marked feaure b D D E E e 0.65 L y 0.08 opyrigh Inersil mericas LL ll Righs Reserved. ll rademarks and regisered rademarks are he propery of heir respecive owners. For addiional producs, see Inersil producs are manufacured, assembled and esed uilizing ISO9001 qualiy sysems as noed in he qualiy cerificaions found a Inersil producs are sold by descripion only. Inersil may modify he circui design and/or specificaions of producs a any ime wihou noice, provided ha such modificaion does no, in Inersil's sole judgmen, affec he form, fi or funcion of he produc. ccordingly, he reader is cauioned o verify ha daashees are curren before placing orders. Informaion furnished by Inersil is believed o be accurae and reliable. However, no responsibiliy is assumed by Inersil or is subsidiaries for is use; nor for any infringemens of paens or oher righs of hird paries which may resul from is use. No license is graned by implicaion or oherwise under any paen or paen righs of Inersil or is subsidiaries. For informaion regarding Inersil orporaion and is producs, see FN8151 Rev 0.00 Page 17 of 17