A Programmable Pulse Generator

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Elvin Bates
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1 A Programmable Pulse Generator Eduardo Sanchez EPFL HEIG-VD To design a programmable pulse generator. The delay between pulses, and the length of duration of each pulse is programmable programmable pulse length programmable pulse delay LoadDelay LoadLength Data 8 pulse Eduardo Sanchez 2

2 / / counter delay pulse 0 counter counter-1 / counter counter-1 counter length pulse 1 / Eduardo Sanchez 3 LoadDelay -1 Dec reg output load DataPath qdelayreg 0 1 dcounter counter LoadLength reg output load qlengthreg d q PulseIn pulse flip-flop Eduardo Sanchez 4

LoadDelay PulseGenerator z LoadDelay control CountIn ci DataPath CountIn pulse pulse PulseIn pi PulseIn LoadLength LoadLength Eduardo Sanchez 5 entity reg is port ( : in std_logic; load : in

3 LoadDelay PulseGenerator z LoadDelay control CountIn ci DataPath CountIn pulse pulse PulseIn pi PulseIn LoadLength LoadLength Eduardo Sanchez 5 entity reg is port ( : in std_logic; load : in std_logic; output : out std_logic_vector (7 downto 0)); end reg; architecture course of reg is process (, ) if ='1' then output <= (others => '0'); else if ('event and ='1') then if load='1' then output <= ; end process; end course; Eduardo Sanchez 6

4 Eduardo Sanchez 7 entity counter is port ( : in std_logic; : out std_logic); end counter; architecture course of counter is signal z : std_logic; signal q : std_logic_vector (7 downto 0); process (, ) if ='1' then q <= (" "); else if ('event and ='1') then if z='1' then q <= ; else q <= q - 1; end process; z <= '1' when q=" " else '0'; <= z; end course; Eduardo Sanchez 8

5 Eduardo Sanchez 9 use work.pulsepackage.all; entity DataPath is port ( : in std_logic; LoadDelay : in std_logic; LoadLength : in std_logic; pulse : out std_logic; CountIn : in std_logic; PulseIn : in std_logic; : out std_logic); end DataPath; Eduardo Sanchez 10

6 architecture course of DataPath is signal Dec, dcounter, qdelayreg, qlengthreg : std_logic_vector (7 downto 0); Dec <= - 1; dreg: reg port map ( =>, =>, => Dec, load => LoadDelay, output => qdelayreg); lreg: reg port map ( =>, =>, => Dec, load => LoadLength, output => qlengthreg); dcounter <= qlengthreg when CountIn='1' else qdelayreg; cnt: counter port map ( =>, =>, => dcounter, => ); Eduardo Sanchez 11 process (, ) if ='1' then pulse <= '0'; else if ('event and ='1') then if PulseIn='1' then pulse <= '1'; else pulse <= '0'; end process; end course; Eduardo Sanchez 12

7 Eduardo Sanchez 13 entity control is port ( : in std_logic; : in std_logic; CountIn : out std_logic; PulseIn : out std_logic); end control; Eduardo Sanchez 14

8 architecture course of control is type state is (init, delaydec, lengthld, lengthdec); signal CurrentState, NextState : state; process (CurrentState, ) CountIn <= '0'; PulseIn <= '0'; NextState <= init; case CurrentState is when init => if ='1' then NextState <= lengthld; else NextState <= delaydec; when delaydec => CountIn <= '1'; if ='1' then NextState <= lengthld; else NextState <= delaydec; Eduardo Sanchez 15 when lengthld => PulseIn <= '1'; CountIn <= '1'; if ='0' then NextState <= lengthdec; when lengthdec => PulseIn <= '1'; end case; end process; if ='0' then NextState <= lengthdec; process (, ) if ='1' then CurrentState <= init; elsif ('event and ='1') then CurrentState <= NextState; end process; end course; Eduardo Sanchez 16

9 Eduardo Sanchez 17 package PulsePackage is component reg port ( : in std_logic; load : in std_logic; output : out std_logic_vector (7 downto 0)); end component; component counter port ( : in std_logic; : out std_logic); end component; Eduardo Sanchez 18

10 component DataPath port ( : in std_logic; LoadDelay : in std_logic; LoadLength : in std_logic; pulse : out std_logic; CountIn : in std_logic; PulseIn : in std_logic; : out std_logic); end component; component control port ( : in std_logic; : in std_logic; CountIn : out std_logic; PulseIn : out std_logic); end component; end PulsePackage; Eduardo Sanchez 19 use work.pulsepackage.all; entity PulseGenerator is port ( : in std_logic; LoadDelay : in std_logic; LoadLength : in std_logic; pulse : out std_logic); end PulseGenerator; Eduardo Sanchez 20

11 architecture course of PulseGenerator is signal z, ci, pi : std_logic; u1: control port map ( =>, =>, => z, CountIn => ci, PulseIn => pi); u2: DataPath port map ( =>, =>, LoadDelay => LoadDelay, end course; LoadLength => LoadLength, =>, pulse => pulse, CountIn => ci, PulseIn => pi, => z); Eduardo Sanchez 21 Eduardo Sanchez 22

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