System Design. Final Review. ILGWEON KANG
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1 System esign Final Review ILGWEON KANG 1
2 SYSTEM ESIGN: uestion 1: Implement the following algorithm. 2
3 ESIGN A ATA SUBSYSTEM Table to list the instructions and the corresponding components. STATE STATEMENT OPERATION CONTROL 3
4 ESIGN A ATA SUBSYSTEM : If, goto ack 1; The symbol A B means o A and B in parallel. is not data, and is just an input! So, nothing to do. ack is not data, but is an output. So mark it. STATE STATEMENT OPERATION CONTROL ack 1 4
5 SCHEMATIC IAGRAM F ATA SUBSYSTEM Control Unit ack 5
6 ESIGN A ATA SUBSYSTEM : ack 0 A X B Y; ata related statements are in blue font. So, write down your statements and operations. STATE STATEMENT OPERATION CONTROL ack 1 ack 0 6
7 ESIGN A ATA SUBSYSTEM : ack 0 A X B Y; o not think of controls, yet. We will do in the next step. STATE STATEMENT OPERATION CONTROL ack 1 ack 0 A X A Load(X) B Y B Load(Y) 7
8 ESIGN A ATA SUBSYSTEM : ack 0 A X B Y; Assign control signals. Then you are done with. Move to. STATE STATEMENT OPERATION CONTROL ack 1 ack 0 A X A Load(X) C0 = 1 B Y B Load(Y) C1 = 1 8
9 SCHEMATIC IAGRAM F ATA SUBSYSTEM X 8 Reg A L 8 A C0 Y Reg B 8 8 L B Control Unit C0 C1 ack C1 9
10 ESIGN A ATA SUBSYSTEM : If ( A > 0 ), goto ; You have A > 0. But, you don t need control signal since it does not assign a new value to your variable. STATE STATEMENT OPERATION CONTROL ack 1 ack 0 A X A Load(X) C0 = 1 B Y B Load(Y) C1 = 1 A > 0 Comp(A, 0) 10
11 SCHEMATIC IAGRAM F ATA SUBSYSTEM X 8 Reg A L C0 8 A 0 (GN) Comparator A 0 A > 0 Y Reg B 8 8 L B Control Unit C0 C1 ack C1 11
12 ESIGN A ATA SUBSYSTEM : A A + B goto ; A A + B: To assign A + B into A. Note you already have the data path A X. So, you should have MUX for X and A+B. STATE STATEMENT OPERATION CONTROL ack 1 ack 0 A X A Load(X) C0 = 1 B Y B Load(Y) C1 = 1 A > 0 Comp(A, 0) A A + B A ß Add(A, B) C2 = 1 12
13 ESIGN A ATA SUBSYSTEM : A A + B goto ; on t forget you should upload your new A to the L register. on t forget you should MUX loading X to A. STATE STATEMENT OPERATION CONTROL ack 1 ack 0 A X A Load(X) C0 = 1, C2 = 0 B Y B Load(Y) C1 = 1 A > 0 Comp(A, 0) A A + B A ß Add(A, B) C0 = 1, C2 = 1 13
14 SCHEMATIC IAGRAM F ATA SUBSYSTEM X 8 8 2:1MUX 0 1 Sel C2 8 Reg A L C0 Adder A 8 A 0 (GN) Comparator A 0 A > 0 A+B B Y Reg B 8 8 L B A > 0 Control Unit C0 C1 C2 ack C1 14
15 ESIGN A ATA SUBSYSTEM : Z A ack 1 goto ; Wire your final output A to Z. STATE STATEMENT OPERATION CONTROL ack 1 ack 0 A X A Load(X) C0 = 1, C2 = 0 B Y B Load(Y) C1 = 1 A > 0 Comp(A, 0) A A + B A ß Add(A, B) C0 = 1, C2 = 1 Z A Wires ack 1 15
16 SCHEMATIC IAGRAM F ATA SUBSYSTEM X 8 8 2:1MUX 0 1 Sel C2 8 Reg A L C0 Adder A A 8 0 (GN) 8 Comparator A 0 A > 0 Z A+B B Y Reg B 8 8 L B A > 0 Control Unit C0 C1 C2 ack C1 16
17 ESIGN A CONTROL SUBSYSTEM Now it is the second half. The second part is very easy and systematic. (1) raw State iagram. (2) Table for Control Subsystem. (3) raw the Logic iagram. 17
18 ESIGN A CONTROL SUBSYSTEM: STATE IAGRAM The number of States is Given: 5. 18
19 ESIGN A CONTROL SUBSYSTEM: STATE IAGRAM : If, goto ack 1; Ignore ack since it does not determine state transition. 19
20 ESIGN A CONTROL SUBSYSTEM: STATE IAGRAM : ack 0 A X B Y; NO CONTROL STATEMENT. Transfer to directly. 20
21 ESIGN A CONTROL SUBSYSTEM: STATE IAGRAM : If ( A > 0 ), goto ; A>0 A 0 Or, just say, (A>0). 21
22 ESIGN A CONTROL SUBSYSTEM: STATE IAGRAM : A A + B goto ; NO CONTROL STATEMENT. Transfer to directly. A>0 A 0 22
23 ESIGN A CONTROL SUBSYSTEM: STATE IAGRAM : Z A ack 1 goto ; NO CONTROL STATEMENT. Transfer to directly. A>0 A 0 23
24 ESIGN A CONTROL SUBSYSTEM: STATE IAGRAM Final Answer: State iagram A>0 A 0 24
25 ESIGN A CONTROL SUBSYSTEM: TABLE F CONTROL raw the skeleton first. Based on #STATES (i.e., 5) and #CONTROLS and #OUTPUTS (i.e., 4). STATE STATEMENT OPERATION CONTROL ack 1 ack 0 A X A Load(X) C0 = 1, C2 = 0 B Y B Load(Y) C1 = 1 A > 0 Comp(A, 0) A A + B A ß Add(A, B) C0 = 1, C2 = 1 Z A Wires ack 1 Table from ata Subsystem. C0 C1 C2 ACK 25
26 ESIGN A CONTROL SUBSYSTEM: TABLE F CONTROL Write down what is each control. C0 C1 C2 ACK C0: Load register A. If 1, then loading. C1: Load register B. If 1, then loading. C2: MUXing A A + B (if 1) or A X (if 0). ACK: Output. 26
27 ESIGN A CONTROL SUBSYSTEM: TABLE F CONTROL Fill-in 1s first. From C0. C0 C1 C2 ACK C0: Load register A. If 1, then loading. C1: Load register B. If 1, then loading. C2: MUXing A A + B (if 1) or A X (if 0). ACK: Output. STATE STATEMENT OPERATION CONTROL ack 1 ack 0 A X A Load(X) C0 = 1, C2 = 0 B Y B Load(Y) C1 = 1 A > 0 Comp(A, 0) A A + B A ß Add(A, B) C0 = 1, C2 = 1 Z A Wires ack 1 Table from ata Subsystem. 27
28 ESIGN A CONTROL SUBSYSTEM: TABLE F CONTROL Fill-in 1s first. From C0. C0 C1 C2 ACK 1 1 C0: Load register A. If 1, then loading. C1: Load register B. If 1, then loading. C2: MUXing A A + B (if 1) or A X (if 0). ACK: Output. STATE STATEMENT OPERATION CONTROL ack 1 ack 0 A X A Load(X) C0 = 1, C2 = 0 B Y B Load(Y) C1 = 1 A > 0 Comp(A, 0) A A + B A ß Add(A, B) C0 = 1, C2 = 1 Z A Wires ack 1 Table from ata Subsystem. 28
29 ESIGN A CONTROL SUBSYSTEM: TABLE F CONTROL Fill-in 1s first. From C0. C0 C1 C2 ACK C0: Load register A. If 1, then loading. C1: Load register B. If 1, then loading. C2: MUXing A A + B (if 1) or A X (if 0). ACK: Output. STATE STATEMENT OPERATION CONTROL ack 1 ack 0 A X A Load(X) C0 = 1, C2 = 0 B Y B Load(Y) C1 = 1 A > 0 Comp(A, 0) A A + B A ß Add(A, B) C0 = 1, C2 = 1 Z A Wires ack 1 Table from ata Subsystem. 29
30 ESIGN A CONTROL SUBSYSTEM: TABLE F CONTROL on t forget both 0 and 1 should be filled in for MUX. C0 C1 C2 ACK C0: Load register A. If 1, then loading. C1: Load register B. If 1, then loading. C2: MUXing A A + B (if 1) or A X (if 0). ACK: Output. STATE STATEMENT OPERATION CONTROL ack 1 ack 0 A X A Load(X) C0 = 1, C2 = 0 B Y B Load(Y) C1 = 1 A > 0 Comp(A, 0) A A + B A ß Add(A, B) C0 = 1, C2 = 1 Z A Wires ack 1 Table from ata Subsystem. 30
31 ESIGN A CONTROL SUBSYSTEM: TABLE F CONTROL on t forget both 0 and 1 should be filled in for MUX. C0 C1 C2 ACK X X 1 1 X C0: Load register A. If 1, then loading. C1: Load register B. If 1, then loading. C2: MUXing A A + B (if 1) or A X (if 0). ACK: Output. For the column C2, i.e., MUX, you can put don t care s to the empty entries. But, it is OK to fill-in with 0s for the empty entries in column C2 since it will eventually help to minimize your logic diagram, i.e., gate. STATE STATEMENT OPERATION CONTROL ack 1 ack 0 A X A Load(X) C0 = 1, C2 = 0 B Y B Load(Y) C1 = 1 A > 0 Comp(A, 0) A A + B A ß Add(A, B) C0 = 1, C2 = 1 Z A Wires ack 1 Table from ata Subsystem. 31
32 ESIGN A CONTROL SUBSYSTEM: TABLE F CONTROL Fill-in 1s first. From C0. C0 C1 C2 ACK X X 1 1 X 1 C0: Load register A. If 1, then loading. C1: Load register B. If 1, then loading. C2: MUXing A A + B (if 1) or A X (if 0). ACK: Output. STATE STATEMENT OPERATION CONTROL ack 1 ack 0 A X A Load(X) C0 = 1, C2 = 0 B Y B Load(Y) C1 = 1 A > 0 Comp(A, 0) A A + B A ß Add(A, B) C0 = 1, C2 = 1 Z A Wires ack 1 Table from ata Subsystem. 32
33 ESIGN A CONTROL SUBSYSTEM: TABLE F CONTROL Fill 0s. The final answer: Table for Control Subsystem. C0 C1 C2 ACK 0 0 X X X 1 C0: Load register A. If 1, then loading. C1: Load register B. If 1, then loading. C2: MUXing A A + B (if 1) or A X (if 0). ACK: Output. STATE STATEMENT OPERATION CONTROL ack 1 ack 0 A X A Load(X) C0 = 1, C2 = 0 B Y B Load(Y) C1 = 1 A > 0 Comp(A, 0) A A + B A ß Add(A, B) C0 = 1, C2 = 1 Z A Wires ack 1 Table from ata Subsystem. 33
34 ESIGN A CONTROL SUBSYSTEM: LOGIC IAGRAM THREE KEY FACTS TO REMEMBER. (Be ready your state diagram and table for control subsystem) A. If a state is receiving more than one arrows, then you need gate before - FF s input. A>0 A 0 B. If a state is sending more than one arrows, then you need AN gates after - FF s output. C. If a control signal is enabled more than one states, then you need gate to generate the control signal. (From P45) C0 C1 C2 ACK 0 0 X X X 1 34
35 ESIGN A CONTROL SUBSYSTEM: LOGIC IAGRAM You need the same number of -FFs with #states. A>0 A 0 35
36 ESIGN A CONTROL SUBSYSTEM: LOGIC IAGRAM has two incoming and two outgoing arrows. A>0 A 0 AN AN 36
37 ESIGN A CONTROL SUBSYSTEM: LOGIC IAGRAM has two outgoings by and. A>0 A 0 AN AN 37
38 ESIGN A CONTROL SUBSYSTEM: LOGIC IAGRAM has two incomings from ( ) and. A>0 A 0 AN AN 38
39 ESIGN A CONTROL SUBSYSTEM: LOGIC IAGRAM is receiving one incoming and one outgoing. A>0 A 0 AN AN 39
40 ESIGN A CONTROL SUBSYSTEM: LOGIC IAGRAM has two incoming and two outgoing arrows. A>0 A 0 AN AN AN AN 40
41 ESIGN A CONTROL SUBSYSTEM: LOGIC IAGRAM has two outgoings by (A>0) and (A>0). A>0 A 0 AN AN (A>0) AN (A>0) AN 41
42 ESIGN A CONTROL SUBSYSTEM: LOGIC IAGRAM has two incomings from and. A>0 A 0 AN AN (A>0) AN (A>0) AN 42
43 ESIGN A CONTROL SUBSYSTEM: LOGIC IAGRAM from with (A>0) and to, one in and one out. A>0 A 0 AN AN (A>0) AN (A>0) AN 43
44 ESIGN A CONTROL SUBSYSTEM: LOGIC IAGRAM from with (A>0) and to, one in and one out. A>0 A 0 AN AN (A>0) AN (A>0) AN 44
45 ESIGN A CONTROL SUBSYSTEM: LOGIC IAGRAM NOT FINISHE! We should generate control signals! AN AN (A>0) AN C0 C1 C2 ACK 0 0 X (A>0) AN 0 0 X X 1 45
46 ESIGN A CONTROL SUBSYSTEM: LOGIC IAGRAM C0 is 1, when and. AN AN C0 (A>0) AN C0 C1 C2 ACK 0 0 X (A>0) AN 0 0 X X 1 46
47 ESIGN A CONTROL SUBSYSTEM: LOGIC IAGRAM ACK is 1, when and. ACK AN AN C0 (A>0) AN C0 C1 C2 ACK 0 0 X (A>0) AN 0 0 X X 1 47
48 ESIGN A CONTROL SUBSYSTEM: LOGIC IAGRAM C1 is 1, when. C2 is 1, when. ACK C2 AN AN C0 C1 (A>0) AN C0 C1 C2 ACK 0 0 X (A>0) AN 0 0 X X 1 48
49 ESIGN A CONTROL SUBSYSTEM: LOGIC IAGRAM ONE!! ACK C2 AN AN C0 C1 (A>0) AN (A>0) AN 49
50 Appendix ILGWEON KANG 50
51 APPENIX: INCREMENT, ECREMENT, AN SHIFT In ata Subsystem, What if you need to implement (1) Increment (INC), i.e., A A+1, or (2) ecrement (EC), i.e., A A-1, or (3) Shift to Right (SHR), i.e., A Shift(A, R, 1), or (4) Shift to Left (SHL), i.e., A Shift(A, L, 1)?? There are two ways!! And both are good to use. 51
52 SCHEMATIC IAGRAM F ATA SUBSYSTEM 1. Using MUX and a separated block (INC, EC, SHR, or SHL). A X.. A A+1 or Inc(A) X 8 8 2:1MUX 0 1 Sel Reg A 8 8 L A C1 C0 Both C1 and C0 should be 1. So that we can update A. INC INC can be replaced by EC, SHR, or SHL block. 52
53 SCHEMATIC IAGRAM F ATA SUBSYSTEM 2. Using the existing load register by adding the control signal. (INC, EC, SHR, or SHL). A X.. A A+1 or Inc(A) X Reg A A 8 8 L INC INC can be replaced by EC, SHR, or SHL. C0 C1 Only C1 should be enabled. And C0 should be disabled. So that we can prevent from malfunc`oning. 53
54 Good Luck!!! 1. I will upload the slides on the class website. 2. I will upload the previous quarter s HW5 for your practice. 54
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