HØGSKOLEN I SØR-TRØNDELAG Avdeling for teknologi

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1 HØGSKOLEN I SØR-TRØNDELAG Avdeling for teknologi Language: English Exam date: 3. December 2014 Duration: Subject code: Subject name: Class: 5 hours TELE2010 3EE Credits: 10 Subject teacher: (navn og telefonnr på eksamensdagen) Bjørn B. Larsen, Kontaktperson(adm.) (fylles ut ved behov kun ved kursemner) Helpers: Oppgavesettet består av: (antall oppgaver og antall sider inkl. forside) Calculator type B 4 tasks on 13 pages Appendix: (antall sider) Comment: Students who sit the examination time out may retain the assignment text. NB! Read through the entire exam before ning work, and dispose time. If something is unclear in the problem set, you should make your own assumptions and explain this in your answer. Good luck!

Examination set TELE2010 3. December 2014 Page 2 of 15 Task 1 (50 %) This is a multiple-choice task: For each question, you must check for the option that you think is right.

2 Examination set TELE December 2014 Page 2 of 15 Task 1 (50 %) This is a multiple-choice task: For each question, you must check for the option that you think is right. If you select not to answer tick the box for "I don t know." Correct answer gives 2 points, wrong answer gives -1 point "I don t know" gives 0 points. Unanswered questions give -1 point. Hedge is allowed. Use the table on the last page. Separate it from the task set and submit it as part of your answers. NB! There are two tables: One to the teacher and one for you. If there is a discrepancy between the contents of the tables, the submitted teacher copy is deemed the wanted responses. Questions about VHDL code concern only the code that is shown. It is assumed that the necessary types and signal / variable is defined correctly. 1. What is correct? A) A tracking AD-converter does not need an output register to keep the value between two conversions. B) A successive approach AD-converter gives the result serially. C) A sub-ranging flash AD-converter has half the number of comparators compared to an ordinary flash AD-converter. D) I don t know 2. What is correct for a variable in VHDL? A) A variable is sued to send a value from one process to another process. B) A variable gets its new value immediately. C) A variable gets its value one delta after the final change in the time queue. D) I don t know 3. What is correct when simulating a variable in VHDL? A) A variable is evaluated when the variables it depends on changes their values. B) If many different values are assigned to a variable at the same time, the simulator will select the final assignment as the new value. C) A variable does not have a time queue.

3 Examination set TELE December 2014 Page 3 of What is correct when synthesizing a VHDL variable? A) The synthesizer will insert a latch if a signal is used before the variables it depends on changes their values. B) The synthesizer will swap the definition sequence such that the signal value is correct if the signal is used before the variables it depends on have been assigned new values. C) If a variable is assigned many different values at the same time instant, the synthesizer will let the first assignment be the new value. 5. What is correct when synthesizing a VHDL signal? A) If a signal is not completely defined on all states the synthesizer will remove the signal. B) If a signal is not completely defined on all states the synthesizer will remove the gate that was supposed to drive the signal. C) If a signal is not completely defined on all the states, the synthesizer will infer a latch that shall remember the signal value. 6. What is this VHDL-code modelling? A) A two-bit counter. B) An AND-gate. C) Divide by two. oppg_1_6: process (q_i) is case (q_in) is when "00" => O <= '0'; when "01" => O <= '0' when "10" => O <= '0' when "11" => O <= '1' when others => O <= '0' end case; end process; 7. What is this code modelling? A) A circular shift register with swapped signal values. B) This has no function at all. C) A parallel register with swapped signal values. oppg_1_7: process (clk) is if rising_edge(clk) then q(msb downto 0) <= q(0 to msb); end process; 8. What is correct when simulating a VHDL variable? A) A variable is used for intermediate values. B) A global variable is used to make the internal values inside a function or a process available to other processes when it has the same name in the processes. C) A variable may be assigned a time queue and behave as a signal if that is appropriate.

4 Examination set TELE December 2014 Page 4 of What is this code modelling? A) Evaluates s_41 = 2(s_ ). B) Evaluates s_41 = 2(previous value of s_ ). C) Nothing. oppg_1_9: process (s_42) is variable v_9: integer range 0 to 127; -- v_9 := s_ ; -- s_41 <= v_9 * 2; -- end process; 10. You are designing a four-bit register that shall make random test vectors when the control signal test is '1'. The register shall not change its value when test is '0'. The register shall trigger on positive edge of the clock signal. Which code does this? A) Oppg_1_10_A: process (clk) if rising_edge(clk) then if test = '1' then q <= q(0) & q(3 downto 1); end process Oppg_1_10_A; B) Oppg_1_10_B: process (clk) if rising_edge(clk) then if test = '1' then q <= q(1) xor q(0) & q(3 downto 1); end process Oppg_1_10_B; C) Oppg_1_10_C: process (clk) if rising_edge(clk) then if test = '1' then q <= q(0) & q(3 downto 1); else q <= i; end process Oppg_1_10_C;

5 Examination set TELE December 2014 Page 5 of You shall design a D-register with asynchronous SET and RESET, that is active high ('1'). RESET has higher priority than SET. The register shall trigger on falling edge of the clocksignal. Which code does this? A) Oppg_1_11_A: PROCESS (a, b, c) BEGIN IF a = '1' THEN q <= '1'; ELSIF b = '1' THEN q <= '0'; ELSIF falling_edge(c) THEN q <= d; END IF; END PROCESS Oppg_1_11_A; B) Oppg_1_11_B: PROCESS (a, b, c) BEGIN IF a = '1' THEN q <= '0'; ELSIF b = '1' THEN q <= '1'; ELSIF falling_edge(c) THEN q <= d; END IF; END PROCESS Oppg_1_11_B; C) Oppg_1_11_C: PROCESS (a, b, c) BEGIN IF falling_edge(c) THEN IF a = '1' THEN q <= '1'; ELSIF b = '1' THEN q <= '0'; ELSE q <= d; END IF; END IF; END PROCESS Oppg_1_11_C; 12. How is the D-algorithm for test-generation? A) The D-path through a sequential circuit must pass a register. B) A fault on the D-path must be propagated to an output or a register to be detected. C) Faults on the D-path must be collected in a signature register and shifted from that. 13. What does the single fault hypothesis tell us? A) The circuit has one or none faults. B) We generate a test for one fault on each vector. C) We may detect all faults present in a circuit if it is not too large.

6 Examination set TELE December 2014 Page 6 of One of the transistors in a logic gate has a fault such that it is always OFF. What do you know about such faults? A) The fault is untestable. B) The fault may be detected by measuring the quiescent current on some test vectors. C) The fault may be detected by two vectors in a sequence. 15. Which statement is correct? A) A circuit with redundancy need not to be tested, because it will always provide the correct answer. B) A circuit with redundancy may sometimes avoid spikes on the output. C) A circuit with redundancy is more effective than one without. 16. What is the smallest number of test vectors for a complete test of an XOR-gate? A) 2 B) 3 C) What is the maximum number of different vectors from an N-bit LFSR (Pseudo random generator)? A) 2 N + 1 B) 2 N C) 2 N Which statement is wrong? A) A signature test may mask multiple faults. B) A signature test will usually not detect more than 50 % of the faults in a circuit. C) A signature test may be enhanced by setting a new star-vector during the test. D) I don t know 19. Which statement is incorrect for a filter in a signal path that shall operate in real time? A) A filter in an FPGA may be utilised for higher sampling frequencies than what is possible in a Digital Signal Processor (DSP). B) A filter in an FPGA will give the same result as on an a DSP. C) A digital filter in an FPGA may have vertical edges (unlimited number of poles). D) I don t know

7 Examination set TELE December 2014 Page 7 of 15 Task 2 (20 %) You are designing a state machine (FSM) that can be used to de-bounce the signal from a switch and provide a stable signal which is one clock period long. The input signal must be active for at least one clock period. If the input is shorter than a clock period it is regarded a transient and there shall be no pulse from the pulse shaper. The figure below shows two examples of input signals from a switch (s) and the corresponding outputs (out). s 1 + ut 1 Clk_2_Hz s 2 ut 2 PulsFormer s ut clk s1 is the signal from an ideal de-bounced switch, while s2 is an example of what a real signal may look like. ut1 and ut2 are the related outputs. We need a pulse that is exactly one clock period long. The FSM in this figure solves the task. 1 START TILSTAND ut s VENT 0 1 GLITCH PULS 1

8 Examination set TELE December 2014 Page 8 of 15 Your entity is like this: library ieee; use ieee.std_logic_1164.all; entity PulseShaper is -- Defines inputs and outputs: port( s, clk : in std_logic ; out : out std_logic ); end PulseShaper; A) Make a block diagram for the FSM with necessary functions and internal signals. Almost anything that resembles this. You may have one or two combinatorial blocks. s Clk current_state combinatorial state_register next_state PulseShaper out Signal names must be included. The VHDL code in part B and C must resemble this schematic diagram. The same number of combinatorial processes, the same names B) Give the VHDL-code that defines the necessary types and signals for the FSM. -- First the type for the states. Wait is named wait_s to avoid conflict with the -- reserved word wait. type states is (start, glitch, pulse, wait_s); -- Defines the signals that are used for current_state and next_state. signal current_state, next_state : states;

9 Examination set TELE December 2014 Page 9 of 15 C) Write the VHDL-code for the architecture of the FSM. The type and signals where defined in part B. You do not need them here, but as this was not specified, you are allowed to include everything. Remember comments to make the code readable! The schematic is with one combinational block, hence the VHDL-code should also be with one combinational process state_register: process (clock) if rising_edge(clock) then current_state <= next_state; end process state_register; -- The combinatorial process: combinational : process (s, current_state) case (current_state) is when start => -- In start out is 0, -- and we jump to glitch if s = 0, else we stay in start. out <= '0'; if (s = '0') then next_state <= glitch ; else next_state <= start ; when glitch => out <= '0'; if (s = '0') then next_state <= pulse ; else next_state <= start ; when pulse => out <= '1'; if (s = '0') then next_state <= wait_s ; else next_state <= start ; when wait_s => out <= '0'; if (s = '0') then next_state <= wait_s;

10 Examination set TELE December 2014 Page 10 of 15 else next_state <= start ; when others => -- Standard ending. -- The FSM is in an illegal state, and we set the output to the safe value, --- and we let next_state be start out <= '0'; next_state <= start ; end case; end process combinational; end architecture rtl ;

11 Examination set TELE December 2014 Page 11 of 15 Task 3 (20 %) The names in the circuit are fault locations for modelled faults. A) Use the D-algorithm to generate a test for F-Stuck-at-0 (SA0). One test vector is sufficient. Copy the schematic to your paper and show and justify how you solve it. Identify the faults on the D-path that are detected by the test. Identify the faults that are not on the D-path but still are detected by this test. A = 1 B1 & F D 1 H D 1 & Q D B = 1 C = 0 E = 1 B2 & G G1= 0 G2 I 1 J Insert D at F. D is defined as 1 for a fault-free signal, and 0 for a signal with a fault. In this case Stuck-at-0. To have F=1 requires AB = 11. Then we propagate D towards the output and set the necessary conditions. This implies that G1 and G must be 0 (for a NOR-gate), and J must be 1 (AND-gate). Finally these requirements are propagated towards the inputs. We need G1=0, which implies that G=0 and BC=10, because B has already been evaluated to 1. G=0 causes I=1 which causes J=1, and the last requirement is satisfied. E may be 0 or 1. The two valid test-vectors are: ABCE = 1100 ABCE = 1101 For both tests, the expected value output is Q = 1. Detected faults on the D-path are:

12 Examination set TELE December 2014 Page 12 of 15 F SA0, H SA0, Q SA0. Detected faults along the D-path are given for the vector ABCE = J SA0, E SA0, A SA0, B1 SA0. B) Generate a test for a delay-fault from A to Q. Explain how it functions. We need to do this test in two steps. We initialize the test by setting the inputs such that a change in A will propagate to Q. Then A is changed and the value on Q is measured. The test input is applied by a register with a separate clock. The output is latched in a register with a separate clock at a time equal to the required maximum delay. The task did not specify if we should test for slow-to-rise or slow-to-fall. Any good solution will be accepted. We may use the vector from part A as the initial vector. We have already shown that this vector detects A SA0. Then the two vectors needed to test the propagation delay are: ABCE = 1101 and The output Q will change from 1 to 0. C) The circuit shall be modified for scan-test. How can you do this? Give a sequence where you utilise scan to apply a test vector and to catch the result and read it. To have F=1 requires AB = 11.

13 Examination set TELE December 2014 Page 13 of 15 Task 4 (10 %) A) Specify and give the definition of the measures used to specify the accuracy (or inaccuracy) to an analogue / digital converter. Linearity. How well the output-voltage fits a straight line. Differential linearity. The difference between to neighbouring steps. Conversion time Conversion rate (MSPS) B) Explain shortly how a dual-ramp A/D-converter operates. _ +

14 Examination set TELE December 2014 Page 14 of 15 C) What is a glitch with D/A-converters? Specify how glitches may appear and how they may be removed ("a de-glitcher"). A glitch is a transient on the output when more than one bit changes its value at the same time. A de-glitcher should be a sample-and-hold circuit, although it might also be a low-pass filter. V inn

15 Kandidatnummer: Eksamen i emne TELE2010 Side av 3. December 2014 Digital systemkonstruksjon Studentens kopi Submittal paper for Task 1. Student copy If there are any discrepancies between the marks on the Teacher copy and the Student copy, the Teacher copy is regarded the intended answer. You may keep this table as your copy. Fill in candidate number and page number. Oppgave a b c d 1 A 2 B 3 C 4 A 5 C 6 B updated 7 C 8 A 9 A 10 B 11 B 12 B 13 A 14 C 15 B 16 B Oppdatert C 18 B 19 C Side 15 av 15

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