Signed integers: 2 s complement. Adder: a circuit that does addition. Sign extension 42 = = Arithmetic Circuits & Multipliers

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Signed integers: 2 s complement N bits -2 N- 2 N-2 2 3 2 2 2 2 Arithmetic Circuits & Multipliers Addition, subtraction Performance issues -- ripple carry -- carry bypass -- carry skip -- carry

sign bit Range: 2 N- to 2 N- 8-bit 2 s complement example: decimal point = 2 7 + 2 6 + 2 4 + 2 2 + 2 = 28 + 64 + 6 + 4 + 2 = 42 If we use a two s complement representation for signed integers, the

1 Signed integers: 2 s complement N bits -2 N- 2 N Arithmetic Circuits & Multipliers Addition, subtraction Performance issues -- ripple carry -- carry bypass -- carry skip -- carry lookahead Multipliers Reminder: Lab #3 due tonight! sign bit Range: 2 N- to 2 N- 8-bit 2 s complement example: decimal point = = = 42 If we use a two s complement representation for signed integers, the same binary addition mod 2 n procedure will work for adding positive and negative numbers (don t need separate subtraction rules). The same procedure will also handle unsigned numbers! By moving the implicit location of decimal point, we can represent fractions too:. = = = Sign extension Consider the 8-bit 2 s complement representation of: 42 = -5 = ~ + = + = What is their 6-bit 2 s complement representation? 42 = -5 = Extend the MSB (aka the sign bit ) into the higher-order bit positions Adder: a circuit that does addition Here s an example of binary addition as one might do it by hand : Adding two N-bit numbers produces an (N+)-bit result + Carries from previous column If we build a circuit that implements one column: we can quickly build a circuit to add two 4-bit numbers Ripplecarry adder 3 4

2 Full Adder building block Subtraction: A-B = A + (-B) The half adder circuit has only the A and B inputs S A B C A B C S CO CO ABC ABC ABC ABC (A A)BC (B B)AC AB(C C) BC AC AB 5 Using 2 s complement representation: B = ~B + ~ = bit-wise complement So let s build an arithmetic unit that does both addition and subtraction. Operation selected by control input: But what about the +? 6 Condition Codes Condition Codes in Verilog Besides the sum, one often wants four other bits of information from an arithmetic unit: To compare A and B, perform A B and use Z (zero): result is = big NOR gate condition codes: N (negative): result is < S N- C (carry): indicates an add in the most significant position produced a carry, e.g., + from last V (overflow): indicates that the answer has too many bits to be represented correctly by the result width, e.g., + V A B S A B S N N N N N N V COUT CIN N N Signed comparison: LT N V LE Z+(N V) EQ Z NE ~Z GE ~(N V) GT ~(Z+(N V)) Unsigned comparison: LTU C LEU C+Z GEU ~C GTU ~(C+Z) Z (zero): result is = N (negative): result is < C (carry): indicates an add in the most significant position produced a carry, e.g., + V (overflow): indicates that the answer has too many bits to be represented correctly by the result width, e.g., + wire signed [3:] a,b,s; wire z,n,v,c; assign {c,s} = a + b; assign z = ~ s; assign n = s[3]; assign v = a[3]^b[3]^s[3]^c; Might be better to use sum-ofproducts formula for V from previous slide if using LUT implementation (only 3 variables instead of 4). 7 8

Modular Arithmetic The Verilog arithmetic operators (+,-,*) all produce full-precision results, e.g., adding two 8-bit numbers produces a 9-bit result.

e., arithmetic is performed modulo 2 word size. Using a fixed word size can lead to overflow, e.g., when the operation produces a result that s too large to fit in the word size.

this is exactly what you want, e.g., when doing index arithmetic for circular buffers of size 2 N.

3 Modular Arithmetic The Verilog arithmetic operators (+,-,*) all produce full-precision results, e.g., adding two 8-bit numbers produces a 9-bit result. Speed: t PD of Ripple-carry Adder C O = AB + AC I + BC I In many designs one chooses a word size (many computers use 32 or 64 bits) and all arithmetic results are truncated to that number of bits, i.e., arithmetic is performed modulo 2 word size. Using a fixed word size can lead to overflow, e.g., when the operation produces a result that s too large to fit in the word size. One can Avoid overflow: choose a sufficiently large word size Detect overflow: have the hardware remember if an operation produced an overflow trap or check status at end Embrace overflow: sometimes this is exactly what you want, e.g., when doing index arithmetic for circular buffers of size 2 N. Correct overflow: replace result with most positive or most negative number as appropriate, aka saturating arithmetic. Good for digital signal processing. Worst-case path: carry propagation from LSB to MSB, e.g., when adding to. t PD = (N-)*(t PD,OR + t PD,AND ) + t PD,XOR (N) CI to CO CI N- to S N- (N) is read order N : means that the latency of our adder grows at worst in proportion to the number of bits in the operands. 9 How about the t PD of this circuit? Alternate Adder Logic Formulation How to Speed up the Critical (Carry) Path? (How to Build a Fast Adder?) A B Cn- Cn-2 C2 C C C in Full Adder C o Is the t PD of this circuit = 2 * t PD,N-BIT RIPPLE? S Generate (G) = AB Propagate (P) = A B Nope! t PD of this circuit = t PD,N-BIT RIPPLE + t PD,!!! Timing analysis is tricky! Note: can also use P = A + B for C o

4 Faster carry logic Let s see if we can improve the speed by rewriting the equations for C OUT : Virtex II Adder Implementation LUT: A B Cout A B C OUT = AB + AC IN + BC IN C OUT S C IN = AB + (A + B)C IN where G = AB = G + P C IN P = A + B generate propagate A B G P Y = A B Cin module fa(input a,b,cin, output s,cout); wire g = a & b; wire p = a ^ b; assign s = p ^ cin; assign cout = g (p & cin); endmodule Actually, P is usually defined as P = A^B which won t change C OUT but will allow us to express S as a simple function : S = P^C IN Cin Dedicated adder logic half-slice = -bit adder 3 4 Virtex II Carry Chain Carry Bypass Adder CLB = 4 Slices = 2, 4-bit adders 64-bit Adder: 6 CLBs A[63:] B[63:] + Y[63:] C i, A B A B A 2 B 2 A 3 B 3 P G P G P 2 G 2 P 3 G 3 C/S C o, C/S C o, C/S C o,2 C/S C o,3 Can compute P, G in parallel for all bits A[63:6] B[63:6] A[7:4] B[7:4] CLB5 CLB Y[64] Y[63:6] Y[7:4] P G C i, C/S C/S Co, P G P 2 G 2 P 3 G 3 C o, C/S C o,2 C/S BP= P P P 2 P 3 C o,3 A[3:] B[3:] CLB Y[3:] CLBs must be in same column 5 Key Idea: if (P P P 2 P 3 ) then C o,3 = C i, 6

5 This image cannot currently be This displayed. image cannot currentl y be This image cannot currently be displayed This image cannot image currently cannot be displayed. currentl y be 6-bit Carry Bypass Adder Critical Path Analysis BP= P P P 2 P 3 BP= P 4 P 5 P 6 P 7 BP= P 8 P 9 P P BP= P 2 P 3 P 4 P 5 BP= P P P 2 P 3 BP2= P 4 P 5 P 6 P 7 BP3= P 8 P 9 P P BP4= P 2 P 3 P 4 P 5 C i, C/S C/S C/S C/S C/S C/S C/S C/S C o, C o, C o,2 C o,4 C o,3 C o,5 C o,6 C o,7 C o, C/S C/S C/S C/S C/S C/S C/S C/S C o,8 C o,9 C o, C o,2 C o,3 C o,4 C i, C/S C/S C/S C/S C/S C/S C/S C/S C o, C o, C o,2 C o,4 C o,3 C o,5 C o,6 C o,7 C o, C/S C/S C/S C/S C/S C/S C/S C/S C o,8 C o,9 C o, C o,2 C o,3 C o,4 C o,5 C o,5 What is the worst case propagation delay for the 6-bit adder? Assume the following for delay each gate: P, G from A, B: delay unit P, G, C i to C o or Sum for a C/S: delay unit 2: mux delay: delay unit For the second stage, is the critical path: BP2 = or BP2 =? Message: Timing analysis is very tricky Must carefully consider data dependencies for false paths 7 8 Carry Bypass vs Ripple Carry Carry Lookahead Adder (CLA) Ripple Carry: t adder = (N-) t carry + t sum Carry Bypass: t adder = 2(M-) t carry + t sum + (N/M-) t bypass Recall that C OUT = G + P C IN where G = A&B and P = A^B For adding two N-bit numbers: t adder ripple adder M = bypass word size N = number of bits being added C N = G N- + P N- C N- = G N- + P N- G N-2 + P N- P N-2 C N-2 = G N- + P N- G N-2 + P N- P N-2 G N P N-...P C IN bypass adder C N in only 3 gate delays* : for P/G generation, for ANDs, for final OR *assuming gates with N inputs 4..8 N Idea: pre-compute all carry bits as f(gs,ps,c IN ) 9 2

Carry Lookahead Circuits The 7482 Carry Lookahead

computed for groups of bits (instead of just for

This allows us to choose the maximum fan-in we want

carry chain using these equations: C J+ = G IJ + P IJ

where I < J and J+ < K generate a carry from bits I

part of the block or if it is generated in the

thru the high part Log 2 (N) 8-bit CLA (P/G

6 Carry Lookahead Circuits The 7482 Carry Lookahead Unit 2 22 Block Generate and Propagate G and P can be computed for groups of bits (instead of just for individual bits). This allows us to choose the maximum fan-in we want for our logic gates and then build a hierarchical carry chain using these equations: C J+ = G IJ + P IJ C I G IK = G J+,K + P J+,K G IJ P IK = P IJ P J+,K where I < J and J+ < K generate a carry from bits I thru K if it is generated in the high-order (J+,K) part of the block or if it is generated in the low-order (I,J) part of the block and then propagated thru the high part Log 2 (N) 8-bit CLA (P/G generation) P/G generation st level of lookahead Hierarchical building block 23 From Hennessy & Patterson, Appendix A 24

8-bit CLA (carry generation) 8-bit CLA (complete) Log 2 (N) t PD = Θ(log(N)) 25 26 Unsigned Multiplication Combinational Multiplier (unsigned) AB i called a partial product x A 2 B 2 A B A A 3 B B 3

7 8-bit CLA (carry generation) 8-bit CLA (complete) Log 2 (N) t PD = Θ(log(N)) Unsigned Multiplication Combinational Multiplier (unsigned) AB i called a partial product x A 2 B 2 A B A A 3 B B 3 A 3 B A 2 B A B A 2 B A B A B AB X3 X2 X X * Y3 Y2 Y Y X3Y X2Y XY XY + X3Y X2Y XY XY + X3Y2 X2Y2 XY2 XY2 + X3Y3 X2Y3 XY3 XY Z7 Z6 Z5 Z4 Z3 Z2 Z Z multiplicand multiplier Partial products, one for each bit in multiplier (each bit needs just one AND gate) x x x x y z y + A 3 B A B 2 A 3 B 2 A 2 B 2 A B 2 A 3 B 3 A 2 B 3 A B 3 A B 3 Propagation delay ~2N x x y2 z Multiplying N-bit number by M-bit number gives (N+M)-bit result Easy part: forming partial products (just an AND gate since B I is either or ) Hard part: adding M N-bit partial products z7 z6 z5 x z4 x z3 y3 z

8 Combinational Multiplier (signed!) X3 X2 X X * Y3 Y2 Y Y X3Y X3Y X3Y X3Y X3Y X2Y XY XY + X3Y X3Y X3Y X3Y X2Y XY XY + X3Y2 X3Y2 X3Y2 X2Y2 XY2 XY2 - X3Y3 X3Y3 X2Y3 XY3 XY Z7 Z6 Z5 Z4 Z3 Z2 Z Z x x x x y z y 2 s Complement Multiplication Step : two s complement operands so high order bit is 2 N-. Must sign extend partial products and subtract the last one X3 X2 X X * Y3 Y2 Y Y X3Y X3Y X3Y X3Y X3Y X2Y XY XY + X3Y X3Y X3Y X3Y X2Y XY XY + X3Y2 X3Y2 X3Y2 X2Y2 XY2 XY2 - X3Y3 X3Y3 X2Y3 XY3 XY Z7 Z6 Z5 Z4 Z3 Z2 Z Z (Baugh-Wooley) Step 3: add the ones to the partial products and propagate the carries. All the sign extension bits go away! X3Y X2Y XY XY + X3Y X2Y XY XY + X2Y2 XY2 XY2 XY2 + X3Y3 X2Y3 XY3 XY3 + - z7 z6 z5 x z4 x x z3 y3 x z2 y2 z NB: There are tricks we can use to eliminate the extra circuitry we added 29 Step 2: don t want all those extra additions, so add a carefully chosen constant, remembering to subtract it at the end. Convert subtraction into add of (complement + ). X3Y X3Y X3Y X3Y X3Y X2Y XY XY + + X3Y X3Y X3Y X3Y X2Y XY XY + + X3Y2 X3Y2 X3Y2 X2Y2 XY2 XY2 + + X3Y3 X3Y3 X2Y3 XY3 XY3 B = ~B Step 4: finish computing the constants X3Y X2Y XY XY + X3Y X2Y XY XY + X2Y2 XY2 XY2 XY2 + X3Y3 X2Y3 XY3 XY3 + Result: multiplying 2 s complement operands takes just about same amount of hardware as multiplying unsigned operands! 3 Baugh Wooley Formulation The Math no insight required Assuming X and Y are 4-bit twos complement numbers: X = -2 3 x 3 + Σ x i 2 i Y = -2 3 y 3 + Σ y i 2 i i= i= The product of X and Y is: XY = x 3 y Σ x i y 3 2 i Σ x 3 y j 2 j Σ Σ x i y j 2 i+j i= j= i= j= For twos complement, the following is true: 3 -Σ x i 2 i = Σ x i 2 i + i= i= 2 2 The product then becomes: XY = x 3 y Σ x i y 3 2 i Σ x 3 y j 2 j ΣΣx i y j 2 i+j i= j= i= j= = x 3 y Σ x i y 3 2 i+3 + Σ x 3 y j 2 j+3 + Σ Σx i y j 2 i+j i= j= i= j= = x 3 y (x 2 y 3 + x 3 y 2 )2 5 + (x y 3 + x 3 y + x 2 y 2 +)2 4 + (x y 3 + x 3 y + x y 2 + x 2 y )2 3 + (x y 2 + x y + x 2 y )2 2 + (x y + x y )2 +(x y )2 2 s Complement Multiplication X3Y X2Y XY XY + X3Y X2Y XY XY + X2Y2 XY2 XY2 XY2 + X3Y3 X2Y3 XY3 XY3 + z 7 x 3 z 6 x 3 z 5 x 2 x 3 x 2 x z 4 x 3 x 2 x x 32 x 2 x x z 3 y 3 x x z 2 y 2 x z y z y

Multiplication in Verilog You can use the * operator to multiply two numbers: Multiplication on the FPGA Hardware multiplier block: two 8-bit twos complement (signed) operands wire [9:] a,b; wire

9 Multiplication in Verilog You can use the * operator to multiply two numbers: Multiplication on the FPGA Hardware multiplier block: two 8-bit twos complement (signed) operands wire [9:] a,b; wire [9:] result = a*b; // unsigned multiplication! If you want Verilog to treat your operands as signed two s complement numbers, add the keyword signed to your wire or reg declaration: wire signed [9:] a,b; wire signed [9:] result = a*b; // signed multiplication! t PD ns In the XC2V6: 6 columns of mults, 24 in each column = 44 mults Remember: unlike addition and subtraction, you need different circuitry if your multiplication operands are signed vs. unsigned. Same is true of the >>> (arithmetic right shift) operator. To get signed operations all operands must be signed. To make a signed constant: sh37c Sequential Multiplier Bit-Serial Multiplication S N Assume the multiplicand (A) has N bits and the multiplier (B) has M bits. If we only want to invest in a single N-bit adder, we can build a sequential circuit that processes a single partial product at a time and then cycle the circuit M times: P S N- S N B M bits + LSB N+ NC xn A N Init: P, load A and B Repeat M times { P P + (B LSB ==? A : ) shift P/B right one bit } Done: (N+M)-bit result in P/B C P B A Init: P = ; Load A,B Repeat M times { Repeat N times { shift A,P: Amsb = Alsb Pmsb = Plsb + Alsb*Blsb + C/ } shift P,B: Pmsb = C, Bmsb = Plsb } (N+M)-bit result in P/B 35 36

Combinational Multiplier (unsigned) Useful building block: Carry-Save Adder X3 X2 X X * Y3 Y2 Y Y -------------------- X3Y X2Y XY XY + X3Y X2Y XY XY + X3Y2 X2Y2 XY2 XY2 + X3Y3 X2Y3 XY3 XY3

pipelining: delay through each partial product (except the last) is just t PD,AND + t PD,. No carry propagation time!

10 Combinational Multiplier (unsigned) Useful building block: Carry-Save Adder X3 X2 X X * Y3 Y2 Y Y X3Y X2Y XY XY + X3Y X2Y XY XY + X3Y2 X2Y2 XY2 XY2 + X3Y3 X2Y3 XY3 XY Z7 Z6 Z5 Z4 Z3 Z2 Z Z multiplicand multiplier Partial products, one for each bit in multiplier (each bit needs just one AND gate) x x x x y z y Good for pipelining: delay through each partial product (except the last) is just t PD,AND + t PD,. No carry propagation time! Propagation delay ~2N x x y2 z x x y3 z2 z7 z6 z5 37 z4 z3 Last stage is still a carry-propagate adder (CPA) 38 This is called a 3:2 counter by multiplier hackers: counts number of s on the 3 inputs, outputs 2- bit result. Wallace Tree Multiplier... Wallace Tree * Four Bit Multiplier Wallace Tree: Combine groups of three bits at a time O(log.5 M) Higher fan-in adders can be used to further reduce delays for large M. CPA 4:2 compressors and 5:3 counters are popular building blocks. 39 *Digital Integrated Circuits J Rabaey, A Chandrakasan, B Nikolic 4

11 Multiplication by a constant If one of the operands is a constant, make it the multiplier (B in the earlier examples). For each bit in the constant we get a partial product (PP) may be noticeably fewer PPs than in the general case. For example, in general multiplying two 4-bit operands generates four PPs (3 rows of full adders). If the multiplier is say, 2 (4 b), then there are only two PPs: 8*A+4*A (only row of full adders). But lots of s means lots of PPs can we improve on this? If we allow ourselves to subtract PPs as well as adding them (the hardware cost is virtually the same), we can re-encode arbitrarily long contiguous runs of bits in the multiplier to produce just two PPs. Booth Recoding: Higher-radix mult. Idea: If we could use, say, 2 bits of the multiplier in generating each partial product we would halve the number of columns and halve the latency of the multiplier! M/2 x A N- A N-2 A 4 A 3 A 2 A A B M- B M-2 B 3 B 2 B B... 2 = - = where indicates subtracting a PP instead of adding it. Thus we ve reencoded the multiplier using,,- digits aka canonical signed digit greatly reducing the number of additions required. 4 Booth s insight: rewrite 2*A and 3*A cases, leave 4A for next partial B K+,K *A = *A = *A A = 2*A 4A 2A = 3*A 4A A product to do! 42 Booth recoding On-the-fly canonical signed digit encoding! current bit pair from previous bit pair B K+ B K B K- action add add A add A add 2*A sub 2*A sub A sub A add A in this bit means the previous stage needed to add 4*A. Since this stage is shifted by 2 bits with respect to the previous stage, adding 4*A in the previous stage is like adding A in this stage! -2*A+A -A+A 43 Summary Performance of arithmetic blocks dictate the performance of a digital system Architectural and logic transformations can enable significant speed up (e.g., adder delay from O(N) to O(log 2 (N)) Similar concepts and formulation can be applied at the system level Timing analysis is tricky: watch out for false paths! Area-Delay trade-offs (serial vs. parallel implementations) 44

Lab 4 Car Alarm - Design Approach Read lab/specifications carefully, use reasonable interpretation Use modular design don t put everything into labkit.v Design the FSM!

Use hex display: show state and time Use logic analyzer in Vivado Car Alarm Inputs & Outputs Inputs: passenger door switch driver door switch ignition switch hidden switch brake pedal switch Outputs:

12 Lab 4 Car Alarm - Design Approach Read lab/specifications carefully, use reasonable interpretation Use modular design don t put everything into labkit.v Design the FSM! Define the inputs Define the outputs Transition rules Logical modules: fsm.v timer.v // the hardest module!! siren.v fuel_pump.v Run simulation on each module! Use hex display: show state and time Use logic analyzer in Vivado Car Alarm Inputs & Outputs Inputs: passenger door switch driver door switch ignition switch hidden switch brake pedal switch Outputs: fuel pump power status indicator siren Figure : System diagram showing sensors (inputs) and actuators (outputs) 6. Fall 23 Lecture Car Alarm CMOS Implementation Debugging Hints Lab 4 Cloaking device Fuel pump relay Design Specs Operating voltage 8-8VDC Operating temp: -4C +65C Attitude: sea level Shock/Vibration Implement a warp speed debug mode for the one hz clock. This will allow for viewing signals on the logic analyzer or Modelsim without waiting for 27/25 million clock cycles. Avoids recomplilations. Notes Protected against 24V power surges CMOS implementation CMOS inputs protected against 2V noise spikes On state DC current <ma Include T_PASSENGER_DELAY and Fuel Pump Disable System disabled (cloaked) when being serviced. assign warp_speed = sw[6]; (posedge clk) begin if (count == (warp_speed? 3 : 26_999_999)) count <= ; else count <= count +; end assign one_hz = (count == (warp_speed? 3 : 26_999_999)) ; Fall 23 Lecture 8 48

always #5 clk=!clk; always begin #5 tick = ; # tick = ; #5; end initial begin // Initialize Inputs clk = ; tick = ;.

integer irepeat; // this will just wait ns, repeated 32x. // simulation only! Cannot implement # in hardware!

// @(posedge clk); // add to index on posedge end // other loops: forever, while 6. Fall 23 Lecture 8 49 6.

13 always #5 clk=!clk; always begin #5 tick = ; # tick = ; #5; end initial begin // Initialize Inputs clk = ; tick = ;... One Hz Ticks in Modelsim To create a one hz tick, use the following in the Verilog test fixture: For Loops, Repeat Loops in Simulation integer i; // index must be declared as integer integer irepeat; // this will just wait ns, repeated 32x. // simulation only! Cannot implement # in hardware! irepeat =; repeat(32) begin #; irepeat = irepeat + ; end // this will wait #ns before incrementing the for loop for (i=; i<6; i=i+) begin #; // wait # before increment. clk); // add to index on posedge end // other loops: forever, while 6. Fall 23 Lecture Fall 23 Lecture 8 5 Edge Detection Student Comments All very reasonable except for lab 4, Car Alarm. Total pain in the ass. The labs were incredibly useful, interesting, and helpful for learning. Lab 4 (car alarm) is long and difficult, but overall the labs are not unreasonable. reg signal_delayed; clk) signal_delayed <= signal; assign rising_edge = signal &&!signal_delayed; assign falling_edge =!signal && signal_delayed; 6. Fall 23 Lecture

Arithmetic Circuits & Multipliers

Arithmetic Circuits & Multipliers Addition, subtraction Performance issues -- ripple carry -- carry bypass -- carry skip -- carry lookahead Multipliers Reminder: Lab #3 due tonight! Pizza Wed 6p 1 Signed