Name: Nouketcha Franklin Lab partner: Chika Nna

Transcription

1 Name: Nouketcha Franklin Lab partner: Chika Nna 05/08/2012 ENEE307 Spring 2012 Instructor: Agis Iliadis SECTION: 0106 Lab Station: #G Lab# 06: Logic Circuits

2 I- Introduction Logic circuits are at the center of modern digital electronic devices. This lab is an attempt to build a 4X4 ROM and some logic gates from basic transistors operation. II- Design and Pspice 4X4 ROM In a BJT ROM, logic one is programmed by placing a BJT at the junction of a vertical BIT line (BL) and a horizontal word line (WL) as shown on the pspice design figure 1. During the read operation, the WL is brought high. The presence of a BJT emitter follower causes the BL to go high. When the BJT is absent, the corresponding BL remains low. OF FTI ME = 0. 5ms DSTM5 ONTIME = 0.5msCLK DELAY = STARTAL = 0 OPPAL = 1 W ord1 BI T1 Q11 BI T2 BI T3 BI T4 Q5 W ord2 Q9 Q17 W ord3 Q13 Q8 W ord4 Q6 Q10 5v 1 D1 1N 4001 D2 1N 4001 D3 1N 4001 D4 1N R1 1k R2 1k R3 1k R4 1k Figure 1: design of a 4X4 Read only memory (ROM)

3 The first word line here is activated with a digital clock, and the state of each BIT line was measured with a voltage probe as indicated figure1. The simulation confirmed that when there is no BJT connected, the BIT line is low when the word line is activated. When there is a BJT connected, the BIT line get activated when the word line get activated. The simulation result of the 4X4 Rom above is shown in figure2. For this run, the BIT s position was moved (shifted down) so that each BIT line s state could be visualized separately. Figure 2: result for first word The green line is the clock pulse that activates the word line. There were no transistors on the second and third BIT line; as a result, BIT line 2 and 3 remained low. BIT line 1 and 4 had transistor connected to them; as a result, they went high every time the word line was high. Figure 3 shows the simulation result for the second word which has BJT s on BIT 2 and 3, as expected they went high every time word two was high.

4 Figure 3: Result for second word The NAND Gate design The NAND gate takes in two inputs and gives an output which is low only when both input are high. Table 1 shows the truth table for a 2 inputs NAND gate shown on Figure 5. Input1 Input2 1 2 U1A output Input 1 Input 2 Output Figure 4: the NAND showing input and output Table 1: Truth table for NAND gate A NAND gate can be designed with transistors as shown on figure 5. In an electronic circuit, mechanical switches are not used. The switching action is performed by a transistor with an input voltage switching the circuit. A typical NAND gate has three stages: first is the Input stage (multi-emitter transistor), second the driver stage, and third the output stage. When the BJT is in cut-off BE junction is reversed biased. When a forward voltage is applied to the BE junction, it takes some time for the BE junction transition capacitance to charge up.

5 Figure 5: Pspice design of NAND gate Figure 6: The NAND Simulation result Time is also required for minority carries to diffuse across the base and enter the collector. This results in the delay time, which is of the order of a nanosecond for a typical BJT. The delay is shown in figure7 and 14.

6 Figure 7: NAND gate operation at higher frequency Extra Credit: Another Logic the: the not gate. Since (X.X) =X +X =X, the Not gate can be built by combining the two inputs of the NAND Gate as shown on figure 8 5dc 1 0 R1 1.5k R2 120 R4 3.9k CLK1 Q4 OF FTI ME =.5m DSTM1 S ON TIME =.5m SCLK DELAY = STARTAL = 0 OPPAL = 1 in1 in2 Q1 Q2 Q3 D1 1N 4001 out Q5 R3 1k 0 Figure 8: NOT gate design for Pspice simulation The NOT gate, simulation shows that the just the input inverted.

7 Figure 9: the NOT Pspice simulation result When used as an inverter, this NAND gates will have a transfer characteristic as shown in Figure 10. The low level and high level input and output values are indicated in figure 12. Figure 10: Inverter transfer characteristic.

8 Figure 11: Transfer characteristic displaying minimum High input and maximum low input. III- Experiment A simple Rom was successfully built. The NAND gate Figure 12: a single bit line having a transistor is high whenever word line is high

9 Figure 1 the output of a NAND gate with a low input is always high independently of other input Figure 13: NAND gate (blue shows the output. green is first input. second input was a logic high not shown here because oscilloscope only had two probes.) The delay time:

10 Figure 14: Measurement of propagation delay time The not Gate Figure 15: not Gate output

11 Conclusion This Lab was successfully completed. The 4X4 ROM was stimulated, a ROM with a single word and a Single BIT line was also built. The NAND logic gate was successfully stimulated and built. As extra credit, the NOT was gate was designed and built. Both the NAND gate and the NOT gate meet the required expectation; they meet the expiations of the truth table. The hardest part of the Lab was the understanding of the functioning of those Logic gates; the transitioning of BJT s transistor between the cut-off and saturation mode. The connection is now clear. Silicon is doped to form either a P-type or N type material. Putting P-type and N-type doped silicon together gives rises to transistors. With transistors, logic gate can be created. With logic gates, it is possible to design binary adders, multiplexers, decoders, which are the basic components of ALU and therefore CPU for computers. Memories are also designed with transistors. This class gave a better understanding of the functioning of electronic devices.