Roadmap Past, Present and Future

Transcription

1 Roadmap Past, Present and Future Paolo Gargini Chairman ITRS2.0 Fellow IEEE, Fellow I-JSAPI Intel Fellow ( ) 1

2 Multiple Stories 1. Introduction ITRS Equivalent Scaling NNI Nanoelectronics Research Initiative (NRI) MPU power limits More than Moore 1. Heterogeneous Integration First Selection of post CMOS devices Equivalent scaling fully in production Scaling acceleration ITRS 15.ITRS Post CMOS map of devices IRDS D D POWER Scaling 2

3 Second Update of Moore s Law X/Year 2X/2Year Log2 of the number of components per integrated function Year International Electron Device Meeting, December

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5 Moore s s Law and Dennard s Scaling Laws Convergence => 30% LINEAR FEATURE REDUCTION S=0.7 50% 50% AREA READUCION GENERATION TO GENERATION 5

6 Phase 1 First Age of Scaling (Self-aligned Silicon Gate) 6

7 IC Industry at a Glance ( ) Driver Cost/transistor -> 50% Reduction How 2x Density/2 years (Moore) Method Geometrical Scaling (Dennard) 7

8 The Incredible Shrinking Silicon Technology of the 90 s Salicide Gate Spacer Salicide Salicide Gate Spacer Salicide 0.35 µ Salicide Gate 0.18µ 1999 Spacer Salicide 8

9 Gate Dielectric Scaling 4 You Are Here! Gate 1.2nm SiO 2 Tox equivalent (nm) Silicon substrate Monolayers 1997 NTRS From My Files 9

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11 Multiple Stories 1. Introduction ITRS Equivalent Scaling NNI Nanoelectronics Research Initiative (NRI) MPU power limits More than Moore 1. Heterogeneous Integration First Selection of post CMOS devices Equivalent scaling fully in production Scaling acceleration ITRS 15.ITRS Post CMOS map of devices IRDS D D POWER Scaling 11

12 1998 ITRS Update Participation extended to: EECA, EIAJ, KSIA, TSIA at WSC on April 23,1998 1st Meeting held on July 10/11,1998 in San Francisco 2nd meeting held on December 10/11,1998 at SFO 50% of tables in 1997 NTRS required some changes 1998 ITRS Update posted on web in April 1999 Tutorial for SEMI 12

13 ITRS

14 Phase 2 Second Age of Scaling (Equivalent Scaling) 14

15 The Ideal MOS Transistor Metal Gate Insulator Source Drain Fully Surrounding Metal Electrode Fully Enclosed, Depleted Semiconductor High-K Gate Insulator Band Engineered Semiconductor Low Resistance Source/Drain From My Files 15

16 ITRS 7/11/

17 IC Industry at a Glance (2003->2021) Driver Cost/transistor-> 50% Reduction How 2x Density/2 years (Moore) Method Equivalent Scaling ( ITRS1.0) 17

18 The Start of the ITRS Micro Tech 2000 Workshop Report 1992NTRS 1994NTRS 1997NTRS Europe Japan Korea Taiwan USA 1998 ITRS Update 1999 ITRS 2000 ITRS Update 2001 ITRS 2002 ITRS Update 18

19 High-k/Metal-Gate (year 2000) 19

20 Four year pace of introduction of Equivalent Scaling into production 20

21 Incubation Time Early Invention Focused Research Introduction Manufacturing Strained Silicon Source Metal Gate Insulator Drain HKMG Raised S/D MultiGates <11 years 21

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25 IEEE, ISSCC: Transistor s 60 th year commemorative supplement 25

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27 Multiple Stories 1. Introduction ITRS Equivalent Scaling NNI Nanoelectronics Research Initiative (NRI) MPU power limits More than Moore 1. Heterogeneous Integration First Selection of post CMOS devices Equivalent scaling fully in production Scaling acceleration ITRS 15.ITRS Post CMOS map of devices IRDS D D POWER Scaling 27

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29 NRI Funded Universities Finding the Next Switch Notre Dame Illinois-UC Michigan Cornell Purdue Penn State UT-Dallas GIT SUNY-Albany GIT Harvard Purdue RPI Columbia Caltech MIT NCSU Yale UVA TUNNEL FET GRAPHENE SPIN LOGIC UC Los Angeles C Berkeley UC Irvine UC Sana Barbara Stanford U Denver Portland State U Iowa SPIN GRAPHENE UT-Austin Rice Texas A&M UT-Dallas ASU Notre Dame U. Maryland NCSU Illinois UC Over 30 Universities in 20 States Columbia Harvard Purdue UVA Yale UC Santa Barbara Stanford Notre Dame U. Nebraska/Lincoln U. Maryland Cornell Illinois UC Caltech UC Berkeley MIT Northwestern Brown U Alabama 29

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36 Multiple Stories 1. Introduction ITRS Equivalent Scaling NNI Nanoelectronics Research Initiative (NRI) MPU power limits More than Moore 1. Heterogeneous Integration First Selection of post CMOS devices Equivalent scaling fully in production Scaling acceleration ITRS 15.ITRS Post CMOS map of devices IRDS D D POWER Scaling 36

37 MM+MtM=Heterogeneous Integration 2006 More than Moore: Diversification Analog/RF Passives HV Power Sensors Actuators Biochips More Moore: Miniaturization Baseline CMOS: CPU, Memory, Logic 130nm 90nm 65nm 45nm 32nm 22nm Information Processing Digital content System-on-chip (SoC) Interacting with people and environment Non-digital content System-in-package (SiP) Combining SoC and SiP: Heterogeneous Integration 16 nm.. V Beyond CMOS

38 iphone June 2007 On January 9, 2007 Steve Jobs announced the iphone at the Macworld convention, receiving substantial media attention,[16] and that it would be released later that year. On June 29, 2007 the first iphone was released. 38

39 Tablet April 2010 A WiFi-only model of the tablet was released in April 2010, and a WiFi+3G model was introduced about a month later 39

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41 Multiple Stories 1. Introduction ITRS Equivalent Scaling NNI Nanoelectronics Research Initiative (NRI) MPU power limits More than Moore 1. Heterogeneous Integration First Selection of post CMOS devices Equivalent scaling fully in production Scaling acceleration ITRS 15.ITRS Post CMOS map of devices IRDS D D POWER Scaling 41

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43 22 nm Tri-Gate Transistor Gates Fins Mark Bohr, Kaizad Mistry, May

44 Question How many more technology generations can Equivalent Scaling be extended for? 44

45 Multigate FET Offers a Simple Way for Scaling and Improving Performance Semicon Japan, December 6,

46 Mark Bohr, August 11,

47 Mark Bohr, August 11,

48 Fin FET Moore s Law Acceleration 48

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51 Technology Node Scaling 14 Today s Challenge Technology Node (nm) ITRS 51

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53 Micron/ Intel 20-nm 64G MLC NAND Flash 53

54 NAND Relative Wafer Cost 54

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59 Vertical Logic Architecture 59

60 3D Moore s Law Acceleration 60

61 3D Architecture 61

62 Multiple Stories 1. Introduction ITRS Equivalent Scaling NNI Nanoelectronics Research Initiative (NRI) MPU power limits More than Moore 1. Heterogeneous Integration First Selection of post CMOS devices Equivalent scaling fully in production Scaling acceleration ITRS 15.ITRS Post CMOS map of devices IRDS D D POWER Scaling 62

63 Phase 3 Third Age of Scaling (3D Power Scaling) 63

64 IC Industry at a Glance (2021->203X) Driver Cost/transistor & power reduction How 2x Density/2 years (Moore) Method 3D Power Scaling (ITRS2.0) 64

65 The Different Ages of Scaling (Different methods for different times) 1 Geometrical Scaling ( ) 1 Reduction of horizontal and vertical physical dimensions in conjunction with improved performance of planar transistors 2 Equivalent Scaling (2003~2021) Reduction of only horizontal dimensions in conjunction with introduction of new materials and new physical effects. New vertical structures replace the planar transistor 3D Power Scaling (2021~203X) Transition to complete vertical device structures. Heterogeneous integration in conjunction with reduced power consumption become the technology drivers 65

66 Beyond 2020 O P S Y S T E M Customized Functionality Outside System Connectivity System Integration Heterogeneous Integration More than Moore A P P L E T S More Moore Beyond Moore ITRS

67 21th Anniversary of TRS 1991 Micro Tech 2000 Workshop Report NTRS 1994NTRS 1997NTRS Europe Japan Korea Taiwan USA 1998 ITRS Update 1999 ITRS 2000 ITRS Update 2001 ITRS 2002 ITRS Update 2003 ITRS 2004 ITRS 2006 ITRS Update 2005 ITRS Update 2007 ITRS 2008 ITRS Update 2009 ITRS 2010 ITRS Update 2011 ITRS 2012 ITRS Update 2013 ITRS 67

68 From ITRS to ITRS 2.0 Beyond 2020 Beyond 2020 O P S Y S T E M Customized Functionality Outside System Connectivity System Integration Themes A P P L E T S April 2014 Focus Teams System Integration System Integration Outside System Connectivity Outside System Connectivity Heterogeneous Integration Heterogeneous Integration More than Moore Heterogeneous Components Beyond Moore Beyond CMOS More Moore More Moore Manufacturing Factory Integration Heterogeneous Integration More than Moore More Moore Beyond Moore ITRS 2012 Dec 2015 RC4 2 Dec 2015 RC4 3 April

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71 Q: How do we get back to exponential performance scaling? IEEE Rebooting Computing Initiative 71

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77 NAND Flash Year of Production D NAND Flash uncontacted poly 1/2 pitch F (nm) D NAND minimum array 1/2 pitch - F(nm) 80nm 80nm 80nm 80nm 80nm 80nm 80nm Number of word lines in one 3D NAND string Dominant Cell type (FG, CT, 3D, etc.) FG/CT/3D FG/CT/3D FG/CT/3D FG/CT/3D FG/CT/3D FG/CT/3D FG/CT/3D Product highest density (2D or 3D) 256G 384G 768G 1T 1.5T 3T 4T 3D NAND number of memory layers Maximum number of bits per cell for 2D NAND Maximum number of bits per cell for 3D NAND

78 DRAM TECHNOLOGY YEAR OF PRODUCTION Half Pitch (Calculated Half pitch) (nm) DRAM cell size (µm 2 ) DRAM cell FET structure RCAT+Fi n RCAT+Fin VCT VCT VCT VCT VCT Cell Size Factor: a Array Area Efficiency V int (support FET voltage) [V] Support min. V tn (25C, G m,max, V d =55mV) Minimum DRAM retention time (ms) DRAM soft error rate (fits) Gb/1chip target 8G 8G 16G 16G 32G 32G 32G 78

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81 Conclusions Geometrical Scaling led the IC Industry for 3 decades ITRS 1.0 Cooperative and distributed research and manufacturing methods highlighted by ITRS emerged as cost effective means of reducing costs since the mid-90s FCRP, NRI, Sematech, IMEC and Government organizations actively cooperated in advanced research Equivalent Scaling saved the Semiconductor Industry since the beginning of the previous decade Preliminary evaluation of post-cmos candidates published in 2010 ITRS 2.0 3D Power Scaling is the next phase of (accelerated) scaling Post CMOS devices and emerging architectures are being jointly evaluated->itrs/ieee RC->IRDS 81