SkyFlash FP7 Project
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1 SkyFlash FP7 Project Development of Rad-Hard non volatile Flash memories for space applications ( Cristiano Calligaro, RedCat Devices, ASI Agenzia Spaziale Italiana Workshop Settimo Programma Quadro Space Foundations Roma, 29 Maggio 2012 Auditorium Via Rieti
2 FP7 Space Call 3 Activities Activity: 9.1 Space-based applications at the service of European Society Area 9.1.1: Pre-operational validation of GMES services and products SPA Stimulating the development of downstream GMES services SPA Stimulating the development of GMES services in specific areas SPA Contributing to the S in GMES Developing pre-operational service capabilities for Maritime Surveillance SPA Coordination of national activities for land monitoring SPA Fostering downstream activities and links with regions Activity: 9.2. Strengthening the foundations of Space science and technology Area 9.2.1: Research to support space science and exploration SPA Exploitation of space science and exploration data SPA Space transportation for space exploration Area 9.2.2: Research to support space transportation and key technologies SPA Space technologies Area 9.2.3: Research into reducing the vulnerability of space assets SPA Security of space assets from space weather events SPA Security of space assets from on-orbit collisions Activity: 9.3 Cross-cutting activities Area 9.3.2: International Cooperation SPA EU-Russia Cooperation in GMES (SICA) SPA International Cooperation in GMES / Deforestation (SICA) SPA EU-South Africa Cooperation in GMES (SICA) SPA EU-Russia Cooperation for Strengthening Space Foundations Area 9.3.5: Studies and events in support of European Space Policy SPA European Space Policy Studies SkyFlash Project ASI Worshop FP7 Space Foundations 2
3 SkyFlash: Why? ESA is demanding for ITAR-Free silicon process to be used for space applications (ASICs); CMOS process is becoming a choice for rad-hard ASICs if combined with RHBD (Rad Hard By Design) techniques; Old antifuse based NVMs (Non Volatile Memories) are not fabricated any more (dismission of production lines); Floating gate/trap are becoming a choice for space apps in particular if compared with Advanced NVMs (FeRAMs, MRAMs, PCMs); Space applications are asking for increased storage capability (on board systems with enhanced boot software, mass storage units for GMES satellites, etc ). A mature standard CMOS process using Flash-based memory cells combined with RHBD techniques may represent an answer to space community needs concerning NVMs SkyFlash Project ASI Worshop FP7 Space Foundations 3
4 ESA efforts against NVMs (1/2) This Tender aims at evaluating COTS flash memories for a possible introduction in low-dose applications with enhanced ECC/EDAC SkyFlash Project ASI Worshop FP7 Space Foundations 4
5 ESA efforts against NVMs (2/2) This Tender asks for an assessment on DRAM and new proceess/materials (ferroelectric, magnetic, chalcogenide) for a possible use in mass storage units SkyFlash Project ASI Worshop FP7 Space Foundations 5
6 SkyFlash main targets The main target of SkyFlash Project is to define a Rad-Hard By Design (RHBD) CMOS roadmap for NVMs development in order to enable space community to have a reference on how to use a standard CMOS process for space apps. (Scientific) The secondary target is to obtain a prototype (e.g. 1Mbit Rad-Hard Flash Memory) in order to validate the overall approach. (Implementation) The third target is to share this knowledge with space community (ESA). (Exploitation) SkyFlash Project ASI Worshop FP7 Space Foundations 6
7 SkyFlash: Who? Design & Technology Radiation Testing Project Coordinator RCD Memory Design Expertise UPD Memory Radiation Testing Expertise UMI Power Electronics Expertise UCY Analog Design Expertise SkyFlash UJY High Energy Radiation Testing Expertise UU Protons Radiation Testing Expertise TS CMOS Silicon Expertise USC Gamma Ray Testing Expertise SkyFlash Project ASI Worshop FP7 Space Foundations 7
8 RedCat Devices SkyFlash Project ASI Worshop FP7 Space Foundations 8
9 University of Milano, Dept. of Physics SkyFlash Project ASI Worshop FP7 Space Foundations 9
10 University of Padova, RREACT SkyFlash Project ASI Worshop FP7 Space Foundations 10
11 Tower Semiconductor SkyFlash Project ASI Worshop FP7 Space Foundations 11
12 University of Jyvaskyla, RADEF SkyFlash Project ASI Worshop FP7 Space Foundations 12
13 University of Cyprus, HER SkyFlash Project ASI Worshop FP7 Space Foundations 13
14 University of Uppsala, TSL SkyFlash Project ASI Worshop FP7 Space Foundations 14
15 University of Santiago de Compostela, GIR SkyFlash Project ASI Worshop FP7 Space Foundations 15
16 SkyFlash on Cordis SkyFlash Project ASI Worshop FP7 Space Foundations 16
17 SkyFlash Workplan We are here!!! Kickoff meeting Milestone1 Milestone2 Milestone3 Final Meeting Management Management Management First Test Chip Design Management WP1 WP2 Testing Chip Refinement WP3 WP4 Testing Final Chip Design WP5 WP6 Scientific and Technological Coordination Dissemination Testing Dissemination WP7 WP8 WP SkyFlash Project ASI Worshop FP7 Space Foundations 17
18 Workpackage List and PMs Distribution WP1/9 WP2 WP3 WP4 WP5 WP6 WP7 WP8 tot RCD UMI UPD TS UJY UCY UU USC Totale WP1/9 Management and Scientific Coordination WP2 First Test Chip Design WP3 First Radiation Testing Campaign WP4 Chip Refinement WP5 Second Radiation Testing Campaign WP6 Final Chip Design WP7 Third Radiation Testing Campaign WP8 Dissemination of Results SkyFlash Project ASI Worshop FP7 Space Foundations 18
19 input data output data NVM failures under irradiation A standard COTS Flash memory has several problems either for TID and SEE. SEL, SEB (hard errors) SEU, MBU (soft errors) SEGR (hard errors) TID (leakage) high voltage generator program and erase sensing circuit row decoder Array SEFI (soft errors) voltage references column decoder Charge Loss SkyFlash Project ASI Worshop FP7 Space Foundations 19
20 input data output data RH NVM expertise required (Design) RCD UMI UCY TS Memory Design Expertise Power Electronics Expertise Analog Design Expertise CMOS Silicon Expertise high voltage generator program and erase sensing circuit row decoder Array voltage references column decoder Memory Architecture SkyFlash Project ASI Worshop FP7 Space Foundations 20
21 input data output data RH NVM expertise required (Testing) X Rays Heavy Ions HE Heavy Ions Protons Gamma Rays UPD UJY UU USC Memory Testing Expertise High Energy Testing Expertise Protons Testing Expertise Gamma Ray Testing Expertise high voltage generator program and erase sensing circuit row decoder Array voltage references column decoder Memory Architecture SkyFlash Project ASI Worshop FP7 Space Foundations 21
22 NVM from RH point of view NV memory cell (microflash, sflash) Periphery (row/col decoders, sensing) Flash knowledge RH NV Die SRAM knowledge P/E Algorithms (state machines for P/E) I/Os (PAD, power distribution) Italy-Israel Cooperation Program: RIFlash Project (Eureka Label, closed on Dec. 2009) 1. Study of basic arrays containing ONO based memory cell for TID purposes (charge loss); 2. Study of single ELT shaped transistors, rad-hard PADs and rad-hard logics (NANDs, NORs, etc ); 3. Partners: RedCat Devices, Tower Semiconductor, Univ. of Calabria, Univ. of Milano, IMM-CNR Catania Italy-Israel Cooperation Program: RAMSES Project (Eureka Label, closed on Jul. 2011) 1. Study of RHBD architectures for SRAMs (stand-alone and embedded); 2. Partners: RedCat Devices, Tower Semiconductor, Univ. of Calabria, Univ. of Milano, Univ. of Padova Italy-Israel Cooperation Program: ATENA Project (Eureka Label, started on Jan. 2012) 1. Study of testing equipment for rad-hard NVMs, SRAMs and APSs in Gamma-Ray Chambers; 2. Partners: RedCat Devices, Tower Semiconductor, Active Technologies, Univ. of Calabria, Univ. of Palermo SkyFlash Project ASI Worshop FP7 Space Foundations 22
23 SkyFlash NVM Cell Candidates Nitride spacers to store the information 3.3V transistors OTP ~100 cycles ONO structure to store the information PM transistors (5V) 10k cycles S-Flash CEONOS SkyFlash Project ASI Worshop FP7 Space Foundations 23
24 SkyFlash NVM Architecture (RHBD-AL) The basic architecture is similar to RC7C1024RHS (1Mbit SRAM) SkyFlash Project ASI Worshop FP7 Space Foundations 24
25 Single Bit Layout 1.4mm x 0.7mm SkyFlash Project ASI Worshop FP7 Space Foundations 25
26 RC27F1024SKY1 OTP Full Chip Layout 10.5 mm SkyFlash Project ASI Worshop FP7 Space Foundations
27 Thanks for your Attention! SkyFlash Project ASI Worshop FP7 Space Foundations 27
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