CS221: VHDL Introduction
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1 CS221: VHDL Introduction Dr. A. Sahu DeptofComp.Sc.&Engg. Indian Institute of Technology Guwahati 1
2 Outline Requirement of VHDL Model : Entity & Architecture VHDL Basic language concepts, design methodology Online Demo in Class Examples, GHDL, GTKWAVE 2
3 VHDLTutorial ForwardedByFrankVahid:DigitalDesign Frank Design Googlesearch VHDLTutorial: Learnby Example 3
4 RequirementofHDL Time how the behavior of the system changes with time creating waveforms Periodic Signals : Clocks Concurrency: Specify: Processes P1 and P2 execute in parallel x = x + 1 y = a b P1 P2 Structure, Composition and Interconnection: Block A consists of two blocks: X1 and Y1 Block X is duplicated A B X Wire W connects A and B X1 Y1 W X2 4
5 RequirementofHDL Electrical Characteristics Current Levels, Tri stating Sensitivity : Rising edge/falling edge Otherprogrammingconstructs Text and File I/O, useful in simulation/debugging Bit true data types Not so important in SW, Important in HW int<6:0>var;specifythebit widthofvariables int 6:0 var; Specify the bit width of variables Modules and Interfaces : Ports InputPortP P Input Port Q Input Port R outportw InoutPort X 5
6 FundamentalVHDLObjects EntityandArchitecturePair VHDL Model Consists of Two Parts Entity Architecture Entity Represent External Interface Arch Represent Contents/Function ality 6
7 VHDL:Entity Entity:RepresentExternalInterface External A B Y Model Name Entity has Interface: No functionality Port Name ENTITY and_gate IS PORT( A: IN BIT; B: IN BIT; Y: OUT BIT ); END and_gate; Port Type Port Direction 7
8 VHDL: Architecture, Specifying functionality ARCHITECTURE data_flow OF and_gate IS y <= a ANDb; END data_flow; May have multiple architectures for given entity different views different levels of detail 8
9 Specifying Concurrency Concurrent Signal Assignments Ci Ai Bi + Si Co ARCHITECTURE data_flow OF fulladderis full_adderis si <= ai XORbi XORci; co<=(aiandbi)or(biandci)or(aiandci); ANDci) OR(aiANDci); END data_flow; 9
10 OrderofExecution Execution independent of Specification ARCHITECTURE data_flow OF full_adderis si <= ai XORbi XORci; co <= (aiandbi) OR(bi ANDci) OR(aiANDci); END data_flow; ARCHITECTURE data_flow OF full_adderis co <= (aiandbi) OR(bi ANDci) OR(aiANDci); si <= ai XORbi XORci; END data_flow; 10
11 ModellingCombinationalLogic One concurrent assignment for each output i1 i2 i3 i4 o1 o2 o3 o4 ARCHITECTURE data_flow OFcomb_ logicis o1 <= i1 andi2; o2<=(i2ori3)xor(i1andi4); ori3) o3 <=...; o4 <=...; END data_flow; 11
12 WhenLogicComplexityIncrease Temporary SIGNALS needed Avoid redundant evaluations X f g h Y=g (f(x)) Z=h (f(x)) X f t=f(x) g h Y=g (t) Z=h (t) Ports : X,Y,Z Signal :t 12
13 SIGNALS Represent intermediate wires/storage Internal notvisibleoutsideentity outside entity ENTITY comb_logic IS PORT(i1, i2, i3, i4:inbit; o1, o2: OUT BIT); END comb_logic; ARCHITECTURE data_flow OFcomb_logic IS o1 <= (i1 andi2 andi3) xori2; o2<=(i1andi2andi3)ori4; i2 i3) ori4; END data_flow; ENTITY comb_logic IS PORT(i1, i2, i3, i4: IN BIT; o1, o2:outbit); END comb_logic; ARCHITECTURE dt data_flow1 OFcomb_logic IS SIGNAL temp: BIT; temp <= (i1 andi2 andi3); o1<=tempxori2; o2 <= temp or i4; END data_flow; 13
14 SIGNALS executedwheni1 i1, i2, or i3 changes executed when temp or i2 changes SIGNALS are associated with time/waveforms PORT is a special type of SIGNAL ARCHITECTURE data_flow1 OFcomb_logic IS SIGNAL temp: BIT; temp <= (i1 andi2 andi3); o1<=tempxori2; o2 <= temp or i4; END data_flow; 14
15 ModellingDelays:inertialdelay inertial delay Models actual hardware Spikes suppressed y<=inertialnotaafter10ns; NOT AFTER10 y <= NOT a AFTER10 ns; inertial delay is default A Y
16 ModellingDelays:transportdelay delay Models wires/transmission lines used in more abstract modelling Spikes propagated y <= TRANSPORT NOT a AFTER10 ns; A Y
17 DescribingBehavior:Processes Signal assignment statements OK for simple behavior Complex behavior requires moreconstructs conditionals (IF, CASE) loops (FOR, WHILE) Use VHDL PROCESS 17
18 VHDL PROCESS PROCESS is sequential Processes are concurrent w.r.t each other Signal assignment is a simple special case Architecture consists of a set of Processes (and signal assignments) at top level Processes communicate using signals ARCHITECTUREx ofa IS f<=g+1; p1: PROCESS IF(x) THEN... ELSE...;... ENDPROCESS; p2: PROCESS FORiin1 TO5 LOOP a (i) <= 0; ENDLLOOP; LOOP;... END PROCESS; ENDx; 18
19 PROCESSExecutionSemantics Execution Semantics NeedtodefinewhenProcessisexecuted define is executed suspending/resuming execution more complex than signal assignment ( evaluate when any signal on RHS changes ) No notion of completion of execution needs to emulate hardware 19
20 ProcessSensitivityList Process is sensitive to signals on Sensitivity List All processes executed once at time=0 Suspended at end of process Reactivated when event occurs on any signal in sensitivity list PROCESS(a, b) c <= a ANDb; END PROCESS; Sensitivity List = a, b 20
21 Process and Signal Assignment ARCHITECTUREx ofy IS PROCESS(a, b) c <= a ANDb; END PROCESS; ENDx; ARCHITECTUREx ofy IS c <= a ANDb; ENDx; Identical Need not use PROCESS for modelling simple combinational behaviour 21
22 ProcessSynchronization Sensitivity list is optional wait is general synchronization mechanism Implicit infinite loop in process Execution continues until suspended by wait statement PROCESS wait on a,b; c <= a andb; END PROCESS; PROCESS (a,b) c< <= aandb andb; END PROCESS; Identical 22
23 SynchronizationwithWAITs Synchronisationwith withwaitwait moreflexible Both sensitivity list and wait not allowed in same process process can have any number of waits For combinational logic, place ALL input signals in sensitivity list For sequential logic, use waits appropriately 23
24 WAIT Examples PROCESS waitfor10ns; outp<= inp; END PROCESS Sampleinput every 10ns PROCESS(clk, reset) IFreset THEN q <= 0 ; ELSIF clk event and clk= 1 d <= q; ENDIF; END PROCESS FlipFlop with Reset PROCESS wait until clk event and clk= 1 ; d <= q; END PROCESS Edge Triggered D FlipFlop PROCESS outp<= inp; END PROCESS Error! (no waits) (Compare signal assignment at architecture level) 24
25 ProcessVariables Variables used for local computations within processes Not associated with events/transactions unlike signals Assignment of value is immediate unlikesignals PROCESS VARIABLE result : BIT; wait until clk eventand clk= 1 ; result := 0 ; for iin0 to6 loop result := result XORinp(i); end loop; outp <= result; END PROCESS; 25
26 StructuralDescription Instantiation and Interconnection Hierarchy ENTITY x IS PORT(a (a, b:inbit BIT, c:outbit); END x; ENTITY y IS PORT(a:INBIT BIT, b:outbit); END y; ARCHITECTURE xaof x IS c <= a AND b; END xa; ARCHITECTURE yaof y IS b <= NOT a; END xa; a b X c Y Z z contains X1 Y1 instances Of x and y 26
27 InstantiationandInterconnection and Interconnection 11 ENTITYz IS PORT (p, q: IN BIT, r: OUT BIT); ENDx; ARCHITECTURE structural OF z IS COMPONENT xc PORT(a, b: IN BIT; c: OUT BIT); END COMPONENT; COMPONENT yc PORT(a, b: IN BIT; c: OUT BIT); END COMPONENT; FOR ALL: xcuse WORK.x(xa); FOR ALL: ycuse WORK.y(ya); SIGNALt: BIT; x1: xcportmap(p (p, q, t); y1: ycport MAP (t, r); END structural; X1 Z Y1 Component declaration Configuration specification (which architecture?) Temporary signal Instantiation 27
28 InstantiationandInterconnection and Interconnection 22 a b X c X1 Y1 Instance name Componentname name Z x1: xcport MAP (p, q, t); y1: ycport MAP (t, r); Same name implies connection Port association list: order of names determines connectivity: a pp b q c t 28
29 Port Mapping COMPONENT xc PORT(a, b: IN BIT; c: OUT BIT); END COMPONENT; Mapping by position: preferred for short port lists x1: xcport MAP (p, q, t); Mapping by name: preferred for long port lists x1: xcport MAP(b => q, a => p, c => t); In both cases, complete port mapping should be specified 29
30 Test Benches Purpose test correctness of Design Under Test (DUT) provide input stimulus observe outputs compare against expected outputs Test Bench is also a VHDL model 30
31 Test Bench Modelling Design Under Test Bench Test (DUT) Signals Test bench a separatevhdl entity Ports are connected to DUT s ports i/pportcorrespondingtodut so/pport port to DUTs o/p port o/p port corresponding to DUT s i/p port Test benchinstantiatesthedut the Stimulus generation and output monitoring in a separatevhdlprocess process Signals are connected to DUT s ports 31
32 32
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