Asynchronous Circuits Races, Cycles and Effect of Hazards

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Shon Baldwin Briggs
6 years ago
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1 synchronous ircuits aces, ycles and Effect of Hazards ll circuits have problems, but asynchronous circuits have more problems The ifference etween synchronous Feedback in igital ircuits The ifference etween synchronous and Synchronous Feedback Synchronous feedback must wait for for the clock. signals must not change when the clock does. lways behave like the state table says synchronous feedback comes immediately with only gate delays. s can come at any time. ircuits may not behave as the state table says. LK ad ; eliminate Good ; FIG. 2- Illustrates synchronous and asynchronous feedback synchronous feedback. the only delay in the feedback loop is the propagation delay of the gates. Synchronous feedback. The feedback is delayed until the active clock edge. 2

2 The 3 Forms of synchronous Feedback The 3 Forms of synchronous Feedback FIG. 2-2 The three ( one is fake) forms of asynchronous feedback circuits Q O n odd number of inversions in loop. OSILLTO Output inverts input. ircuit oscillates. LTH S=0 FEEK = Q N Q L n even number of inversions. The output reinforces the input. If Q L was originally high, it stays high. If Q L was originally low, it stays low. The circuit remembers It is a latch. This circuit remembers. ut only when S=0 and = NO FEEK Q N This circuit only appears to have feedback. =, O gate stops the feedback. =0, N gate stops feedback. There is never a complete feedback loop! synchronous feedback circuits oscillate or remember. They oscillate if the feedback loop has an odd number of inversions. They remember if the feedback loop has an even number of inversions. 3 The 3 Forms of synchronous Feedback FIG. 2-3 FIG. 2-4 Sensitized Paths signal path is sensitized if a change in its input changes its output. Sensitized and unsensitized paths INPUT 0 INPUT 0 0 OUTPUT OUTPUT=0 Sensitized path. signal change goes through both N and O gates. Unsensitized path. signal change cannot go through the N gate. feedback path must be sensitized for the circuit to remember/oscillate In practical circuits, the feedback is only sensitized part of the time. pparent feedback path is never sensitized FEEK This circuit remembers. When S=0 S=0 = Q N and = signal change can propagate around the loop NO FEEK Q N =0 shuts off the N gate. = shuts off the O gate. There is never a sensetized feedback loop! 4

3 eview of Synchronous State Machines nalysis of synchronous ircuits FIG. 2-5 eview of Synchronous State Machines The state is the collective output of all flip-flops and latches. The next state is the state after the clock edge. state machine using flip-flops. x INPUT GTE LOGI Synchronous feedback. a + b + c + Q = The present state is value of the present Q outputs The next state is the value of a + b + c + the present inputs. FIG. 2-6 state machine is defined by its next state table. State Graph and Next State Table for a Mythological ircuit. x= x= x= x=0 x= 0 x= 0 x=0 x=0 c + x=0 x= The next state is different for different inputs. Only 4 of the 8 states are shown here. 5 State Variables For synchronous State Variables For synchronous ircuits In synchronous circuits (with flip-flops) Each flip-flop can remember one bit. Each flip-flop holds a state variable. The present state is the flip-flop output(s) The next state is the the input(s), a + In asynchronous circuits Each feedback loop can latch one bit Each feedback loop holds a state variable. The state is the value fed back to the input. The next state is vaule out of the gate. FIG. 2-7 synchronous circuits the state is value on the feedback lead. Mark an on the wire where you want to read the state. Write, the present state on the output side. Write a +, the next state, on the input side. Synchronous and asynchronous state variables Synchronous feedback. a + The present state is value at It is an input to the logic gates The next state value is a+, It is the onput from the logic gates synchronous feedback. 2 a + The present state is It is an input to the logic gates The next stat is a + It is the onput from the logic gates In steady state, the asynchronous present state = next state, = a + On an input change, a + may change. This will immediately change and give a new state. 6

4 elation etween and a + FIG. 2-8 elay separates a + and Very small delay in wire a + 0 Very small delay in wire a + elation etween and a + synchronous feedback model. a + comes out of circuit. fter a short delay it reenters the circuit as travels through the sensitized path and emerges as a +. The state is continuously regenerated by a + a + is continuously recalculated from and inputs n input change may change a +. fter the wire delay this will change. will stay in this new state until an input changes a + again. 2 a + We usually put an on the schematic to show where a+ changes to. Should the be at or 2?* * The is thinking point where a + changes to. It can be anywhere in the feedback path 7 elation etween and a + Where To Put The Loop reaks FIG. 2-9 reak each independent feedback loop with an (push button). n independent feedback loop can store one bit. two loops both broken. a+ b+ FIG. 2- Sometimes two independent loops are really one Then cut them with one. One independent feedback loop which looks like two. FIG. 2- Extra breaks: nalysis will still work with several breaks in one loop. dds unnecessary states, make more work. When in doubt, use extra breaks. One feedback loop. n unnecessary extra break. 8

5 Tracing the Signals nalysis of an synchronous ircuit Tracing the Signals typical analysis:. reak the feedback loops at the appropriate places, and in FIG Write equations relating the values on the input side of the break (a + and b + ) with values on the output side (, ) and the inputs (s). That is a + = f(,,s), b + = g(,,s). 3. Make a state table. FIG. 2-2 Sample ircuit For nalysis. s s s a + b + a + = f(,,s) = + s b + = g(,,s) = s s= ) reak the circuit at and. 2) Write equations for a +,b + 3) Make a state table showing the next states for each state 9 FIG. 2-3 Tracing State hanges on the Sample ircuit. a) Initially s= 0; State==00 off s=0 a + =0 b + =0 =0 =0 c) Travel through the break, state = = a + =0 =0 on e) Now state = = b + = = Tracing the Signals b) hange s to ; State = =00 Soon the next state () becomes the state. a + =0 =0 b + = =0 d) Soon the next state a + b + will go to a + = =0 on b + = = on f) little later the next state a + b + will go to off a + = = b + = = g) ircuit settles down in state== a + = = off off b + =0 =0 a + = = b + =0 = off The states traveled through are: 00 -> -> -> 00 and are stable states. We circle stable states. The other states are transient.

6 Tracing the Signals FIG. 2-4 Tracing State hanges on the Next State Table. s= Stable states: where next state = present state. are circled Transient intermediate states: all other states nalysis Start and end on stable states. Travel on the next state side of table. Path through next states is the same as the path through the present states. States traveled through when s rises > -> -> elays and the Sample ircuit The sequence of state changes is independent of the circuit delays. With random delays on all gates and all wires, the states would still change 00 -> -> -> e sure s does not change again until the final stable state is reached. This circuit is delay Independent. Not all circuits are this well behaved. ircuits with aces ircuits Where elays Matter ircuits with aces FIG. 2-5 ircuit where state changes depend on delays s # #3 #2 #4 a + b + Next-State Equations a + = f(,,s) = + s b + = g(,,s) = + s Substitute values for, and s into the next-state equations, to generate state table data. s= This circuit does not always behave like the state table The sequence of states passed through depends on delays We will see: If # and #2 are faster, ends in state if #3 and #4 are faster, end in state, if they are equal, end in state. The circuit has a race. 2

7 FIG. 2-6 nalysis of a acy ircuit a) Initially s=0; State==00 s=0 a + =0 =0 b + =0 =0 ircuits with aces b) s changes, the next state a + b + = ut only if the delay through gate # and #2 equals the delay through #3 and #4 # off #3 a + = =0 #2 b + = =0 #4 c) = feeds back to three gates. s a + = = b + = = s d) The feedback blocks the output on s and s but reestablishes it through. State change is 00 -> LOKE s a + = = b + = = s 3 ircuits with aces FIG. 2-7 The nalysis of acy ircuit With Fast Upper Gates. d) If gates #3 and #4 are slow, after s changes, next state a + b + =. # #3 slow fast a + = #2 = b + =0 #4 =0 FIG. 2-8 nalysis When the Slow Upper Gates e) = will feed back to give a stable state 00 -> # #3 #2 a + = = #4 b + =0 =0 LOKE b) s changes, if gates # and #2 are slow, state first changes toa + b + =. slow # a + =0 =0 #2 b + = = #4 #3 c) = will feed back to give a stable state 00 -> LOKE a + =0 =0 b + = = 4

8 ircuits with aces nalysis of acy ircuit Using State Table Get next-state equations from the circuit. Use them to build a state table. Note any two-bit change in the state. when in state 00, s goes 0 next state is Identify races by: two-bit (or more) change in a state variable. The possible results from the double-bit change is shown in FIG FIG. 2-9 State-Table and Equations for the acy ircuit in FIG s Shows a + and b + are functions of only the present state and the inputs. # #3 #2 #4 a + b + Next-State Equations a + = f(,,s) = + s b + = g(,,s) = + s Substitute values for, and s into the next-state equations, to generate state table data. TWO IT HNGE IN STTE s= ircuits with aces FIG The Three Possible Outcomes of the ace in the acy ircuit. Path in the state-table Path when delay for Path when delay for if delays are equal. (via gates # and #2) is slower. (via gates #3 and #4) is slower. is so s=0 s=0 slow it s= stays until it is too late. 00 (The stable state is reached). 00 If gates # and #2 are fastest, the stable next state will be =. If gates #3 and #4 are fastest, the stable next state will be =. With equal delays, the stable next state will be =. t aces Have a Simultaneous Two-it hange in the State Variables Look for double-bit change in a state variables, and you will find the races. 6

9 Noncritical, and Other Non-important Noncritical, and Other Non-important aces. Not all races are a problem: Noncritical aces Some races take different paths but end in the same final stable state. These are called noncritical races. FIG. 2-2 and FIG Unused aces ( Who ares aces) Some races are in a part of the state table which is never used. FIG aces To Equivalent States (States that could be merged) The final states of the race might be equivalent. The machine would externally behave the same no matter how the race came out. 7 Noncritical, and Other Non-important FIG. 2-2 Noncritical ace With Three Paths. s=0 # s #3 a + =0 =0 #2 b + =0 =0 #4 Next-State Equations a + = f(,,s) = + s b + = g(,,s) = s + s= slow slow FIG The Three Possible Paths Individually Shown. Path for equal delays. Gates # and #2 are slower. Gates #3 and #4 are slower. s= Then is slower than s= is slow so next state becomes Then is slower than s= The race is noncritical. No matter which path you take, you always end in state 8

10 Noncritical, and Other Non-important Who ares ace. This ace is in state as s changes. The stable states and all the transitions between them are shown. The Who ares race is between unstable states. Further, no useful transition goes through it. The circuit does not use the transition. No one cares if it has a race. FIG s=0 ircuit With a Who ares ace. Next-State Equations a + = + s + s s a + s b + b + = s State Graph 00 s=0 s= ace in a never used transition 9 aces etween Transient States Where aces etween Transient States Where One ares! ace etween Transient States, ut On a Path etween Stable States. FIG showed a who cares race between unused transient states. This race is between transient states, but should not be ignored. It is an intermediate transition in the path between two stable states > -> The second transition from has a double bit change. The circuit may end up in the stable state. UNWNTE TNSITION FIG s= WHT ESIGNE WNTE 20

11 The Two Types of ycles: Oscillations (ycles)in State Tables. ycles are oscillations They are transitions that once entered, never reach a stable state. In theory they oscillate - forever, or until an input change takes them out of the cycle. In practice, some may quickly fall into a stable state. The Two Types of ycles:. The oscillation continue forever or until turned off. These have: no stable state in the path of the cycle no races in the path. 2. The circuit only oscillates a few cycles before falling into a stable state. These have: a stable state in the column, a race in the path.. For three or more state variables, also check the race can reach a stable state. 2 FIG s ycle Which Will ontinue Oscillating Forever. # #2 a + Electronic oin Tosser No Stable States In olumn When, It will oscillate forever. There are two feedback paths The one through gate #2 oscillates (odd number of inverters). The one through gate # is a latch. (even number of inverters). The circuit will: oscillate when, and latch the last output value when s -> 0. The Two Types of ycles: State Next State a + s= FIG s ycle, With Stable States In olumn, ut No aces, Will ontinue Forever. Stable States In the olumn Without a ace s #3 s a + b + From the state table; there is a cycle. From the circuit; the loop oscillates. The loop stays fixed at =0. The loop oscillating cannot make = The loop oscillating cannot reach a stable state. s=

12 sychronous State-Machines With sychronous State-Machines With Several Variables. With only one external input. Single input asynchronous circuits have two types of races. aces between the state bits. 2. aces between a state variable and an input. These are called essential hazards and will not be discussed. With two or more inputs. In addition, with multiple inputs, one can have- 3. aces between the two inputs Multiple synchronous s are Miserable aces between two inputs cannot be handled by this theory. Theoreticians usually state- Nearly simultaneous input changes are not allowed. Practical designers must force rationally behavior for double changes. One might: esign the machine to work properly for all states a race might enter. Interlock the signals so they cannot change at the same time. Feeds the multiple input signals separately into a synchronous circuit. 23 Two-input State-Table With aces ouble input changes are not allowed. The State-Table has 4 other races.. Start at with sx= -> sx=. This race leads into a cycle 2. Start at with sx=00 -> sx=. This wraps around the table. The final state must be stable. It may be any of 00, or. sychronous State-Machines With FIG Two input async. circuit sx=00 sx= sx= sx= NO NO 00 NO NO NO NO NO NO FIG ) a + b + 2) No means we don t allow two inputs to change at once. a + b

13 sychronous State-Machines With Two-input State-Table With aces (ont) ouble input changes are not allowed. The races continued: 3. Start at with sx= -> sx=. No race on first hop 2nd hop has a race, and leads into the same cycle as ) FIG Start at with sx= -> sx=00. This may end in either states 00 or FIG Two input async. circuit sx=00 sx= sx= sx= NO NO 00 NO NO NO NO NO NO 3) a + b + 4) a + b State variable races with double input variable changes. State marked NO NO = The double input change will make a mess of the circuit function. We take steps to make sure it will never happen (not allowed). Or (next year) follow all possibilities 25 sychronous State-Machines With emoval of aces ace-free designs can be done by careful state assignment. race is a double-bit state-variable change. Thus states connected to another state, must differ in value by one-and-only-one bit In the Karnaugh map, adjacent squares differ by only one bit. States can be assigned by plotting them on the Karnaugh map. FIG. 2-3 ssigning it-patterns to States Using a Karnaugh Map. djacent Karnaugh map 0 squares differ by one bit F 00 E F 0 Print the state names on map place connected states in adjacent squares. onnected states must differ by only one bit ead the state assignment off the map E = 000 = 0 = 0 F = 0 = 0 E = 26

14 sychronous State-Machines With FIG ssigning it-patterns to ifficult State Graphs y dding States. difficult state graph K Triangular states connections like, can never all differ by only one bit Here and could not be made adjacent because of the triangle K K α dd a temporary state α to eliminate the triangle The new state assignment without races 0 00 α K FIG ssigning it-patterns to States Using Flow-Through States. difficult state graph x,y=0,d K x,y=, xy=, x,y=0, Triangular connections x,y=, x,y=0,d K x,y=, x,y=0, Since x,y=, sends both and to, let flow through. ( acts as a transient state) 0 00 K ace free ssignment dding extra state variables will eventually solve the race problem. However it may make the circuit larger and slightly slower. 27 Find ace Free ssignment for the State Table State. Y=00 Next State Y= Y= Y= sychronous State-Machines With () ircle stable states. State. Y=00 Next State Y= Y= Y= (2) Fill in the allowed (single input change) transitions from to other stable states. State Y=00 Next State Y= Y= Y= (3) Fill in the other transitions between stable states, for single column input changes. State Y=00 Next State Y= Y= Y= 28

15 jump Finding ace Free ssignment State. Y=00 Next State Y= Y= Y= evise some next states to be flow-through states (two hops) to avoid races. State Y=00 Next State Y= Y= Y= sychronous State-Machines With (3) Sketch transitions on a state table. Try to make transitions horizontal or vertical. To many angles (5) Get rid of 3 sided loops. 00 wrap around 0 an get rid of some angles flow through transition states (6) Move state (7) otate map locations to map (4) Get rid of angles and jumps 00 3 sided loops are bad map to place in ace Free ssignments State. Y=00 Next State Y= Y= Y= (9) Fill in new transient states and race-free assignment. State Y=00 Next State Y= Y= Y= =000 =000 =0 =000 =0 =0 =0 =0 =000 = = = = =0 =0 =0 =0 -- =0 =0 =0 =000 =0 flow through transition states sychronous State-Machines With 00 0 (8) Get race-free state assignment off map =000 =0 = =0 =0 30

16 sychronous State-Machines With Hazards an Poison synchronous Machines FIG Example: The Hazard in the Transparent -Latch The simple form of -latch (transparent latch) is just a MU. The latch has a static- hazard when,q =,. This glitch can feed back and latch itself. Q q MU G s the clock falls The 0 may get latched as Q=0 Even though =, and Q old = Q Q q + Q q + = + Q SET =, Q= q + = + q + = + To mask the hazard Keep Q = across the change in q + = + Q +Q Q q + Q q + = + Q +Q SET =, Q= q + = + + q + = Hazard-free latch 3 sychronous State-Machines With ommon Hazard-Free -Latch ircuit FIG Explanitory note (not for examination purposes) This -latchcircuit is often used and is hazard free. nalysis of the transistor circuits will show this is about 30% larger than the latch with the hazard, and smaller than the last circuit with the masking gate. q + Q q + = + q(+) No hazard Q 32

Asynchronous Circuits Races, Cycles and Effect of Hazards

Asynchronous Circuits Races, Cycles and Effect of Hazards synchronous ircuits aces, ycles and Effect of Hazards ll circuits have problems, but asynchronous circuits have more problems 1 The ifference etween synchronous Feedback in igital ircuits The ifference