EECS150 - Digital Design Lecture 3 - Field Programmable Gate Arrays (FPGAs) Project platform: Xilinx ML

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1 EECS150 - igital esign Lecture 3 - Field Programmable Gate Arrays (FPGAs) January 25, 2010 John Wawrzynek Spring 2011 EECS150 - Lec03-FPGA Page 1 Project platform: Xilinx ML Spring 2011 EECS150 - Lec03-FPGA Page 2

2 FPGA Overview Basic idea: two-dimensional array of logic blocks and flip-flops with a means for the user to configure (program): 1. the interconnection between the logic blocks, 2. the function of each block. Simplified version of FPGA internal architecture: Spring 2011 EECS150 - Lec03-FPGA Page 3 Why are FPGAs Interesting? Technical viewpoint: For hardware/system-designers, like ASICs only better! Tape-out new design every few minutes/hours. oes the reconfigurability or reprogrammability offer other advantages over fixed logic? ynamic reconfiguration? In-field reprogramming? Self-modifying hardware, evolvable hardware?

3 Why are FPGAs Interesting? Staggering logic capacity growth (10000x): Year Introduced evice Logic Cells logic gate equivalents 1985 XC XC7V2000T 1,954,50 15,3,480 FPGAs have tracked Moore s Law better than any other programmable device. Why are FPGAs Interesting? Logic capacity now only part of the story: on-chip RAM, high-speed I/Os, hard function blocks,... Modern FPGAs are reconfigurable systems Xilinx Virtex-5 LX110T 10GBps Serdes Ethernet MACs PCI express Phy But, the heterogeneity erodes the purity argument. Mapping is more difficult. Introduces uncertainty in efficiency of solution. 4 ALUs 148 3Kb AM Blocks

4 Why are FPGAs Interesting? Have been an archetype for the semiconductor industry as a whole: from: mattrhodes.net Putting the FPGA Business in Perspective. How large is it compared to others? from: mattrhodes.net

Why are FPGAs Interesting? Have attracted an huge amount of investment for new ventures: Most startups have failed. Why? Business dominated by Xilinx and Altera Why are FPGAs Interesting?

5 Why are FPGAs Interesting? Have attracted an huge amount of investment for new ventures: Most startups have failed. Why? Business dominated by Xilinx and Altera Why are FPGAs Interesting? FPGAs at the leading edge of IC processing: Xilinx V7 out next year with 28nm TSMC processing Foundaries like FPGAs - regularity help get process up the learning curve High-volume commitment gets interest of foundry (Gives FPGAs a competitive edge over ASICs, which usually are built on an older process.)

ASICs, Ian Kuon and Jonathan Rose, FPGA 0 Versus ASICs: area 40X, delay 3-4X, power 12X How can this be?

6 Why are FPGAs Interesting? FPGAs have been wildly successful even though they are inefficient in silicon area, energy, and performance : Measuring the Gap Between FPGAs and ASICs, Ian Kuon and Jonathan Rose, FPGA 0 Versus ASICs: area 40X, delay 3-4X, power 12X How can this be? Is there something more important than silicon efficiency? ie Photos: Virtex FPGA vs. Pentium IV FGPA Vertex chip looks remarkably structured Very dense, very regular structure Full-Custom Pentium chip somewhat more random in structure Large on-chip memories (caches) are visible Fall 2010 CS Lec01 Intro Page 12

FPGAs are in widespread use FPGAs Power Net-Centric Battlefield on Many Fronts Far more designs are implemented in

INSIE Make MicroBlaze Processing Roar With Hardware Acceleration FPGAs Help RN Track Particles Approaching Speed of

Software in Medical evice esign Taming Power raw in Consumer MPUs Plugging into High-Volume Consumer Products INSIE

into Hot Startup Spartan-3E: A New Era How to Beat Your Son Multimedia for Automotive at Guitar Hero Using Xilinx

1i Software and SystemVerilog Control Your esigns SERIAL I/O Fall 2010 CS 294 - Lec01 Intro Page 13 Extend Your

arrangement of interconnection wires, and the basic functionality of the logic blocks.

7 FPGAs are in widespread use FPGAs Power Net-Centric Battlefield on Many Fronts Far more designs are implemented in FPGA than in custom chips. INSIE Make MicroBlaze Processing Roar With Hardware Acceleration FPGAs Help RN Track Particles Approaching Speed of Light Xcell Automotive Innovators Hit Hit High Top Gear in river Assistance with FPGA Platforms Hardware Trumps Software in Medical evice esign Taming Power raw in Consumer MPUs Plugging into High-Volume Consumer Products INSIE Algorithm evelopers Power New A System on Xilinx Automotive FPGA Platform Engineer Turns Blown HIGH VOLUME Engine into Hot Startup Spartan-3E: A New Era How to Beat Your Son Multimedia for Automotive at Guitar Hero Using Xilinx FPGA SP Algorithms Tips and Tricks for ESIGN TOOLS Using FPGA Editor New ISE 7.1i Software and SystemVerilog Control Your esigns SERIAL I/O Fall 2010 CS Lec01 Intro Page 13 Extend Your Reach SUBS FPGA Variations Families of FPGA s differ in: physical means of implementing user programmability, arrangement of interconnection wires, and the basic functionality of the logic blocks. Most significant difference is in the method for providing flexible blocks and connections: Anti-fuse based (ex: Actel) + Non-volatile, relatively small fixed (non-reprogrammable) Several floating gate or eprom style approaches have been used. One now by Actel. Fall 2010 CS Lec01 Intro Page 14

8 Floating-gate / EPROM / FLASH based (ex: Actel, others) FPGA Variations + Non-volatile + reprogrammable larger size then anti-fuse requires special process Fall 2010 CS Lec01 Intro Page 15 User Programmability Latch-based (Xilinx, Altera, ) + reconfigurable volatile relatively large. Latches are used to: 1. control a switch to make or break cross-point connections in the interconnect 2. define the function of the logic blocks 3. set user options: within the logic blocks in the input/output blocks global reset/clock Configuration bit stream is loaded under user control Fall 2010 CS Lec01 Intro Page 1

9 Background (review) for upcoming A MUX or multiplexor is a combinational logic circuit that chooses between 2 N inputs under the control of N control signals. A latch is a 1-bit memory (similar to a flip-flop). Spring 2011 EECS150 - Lec03-FPGA Page 17 Idealized FPGA Logic Block 4-input look up table () implements combinational logic functions Register optionally stores output of Fall 2010 CS Lec01 Intro Page 18

10 4- Implementation n-bit is implemented as a 2 n x 1 memory: inputs choose one of 2 n memory locations. memory locations (latches) are normally loaded with values from user s configuration bit stream. Inputs to mux control are the CLB inputs. Result is a general purpose logic gate. n- can implement any function of n inputs! Fall 2010 CS Lec01 Intro Page 19 as general logic gate An n-lut as a direct implementation of a function truth-table. Each latch location holds the value of the function corresponding to one input combination. Example: 4-lut Example: 2-lut Implements any function of 2 inputs. How many of these are there? How many functions of n inputs? Fall 2010 CS Lec01 Intro Page 20

FPGA Generic esign Flow esign Entry: Create your design files using: schematic editor or HL (hardware description languages: Verilog, VHL) esign Implementation: Logic synthesis (in case of using HL

11 FPGA Generic esign Flow esign Entry: Create your design files using: schematic editor or HL (hardware description languages: Verilog, VHL) esign Implementation: Logic synthesis (in case of using HL entry) followed by, Partition, place, and route to create configuration bit-stream file esign verification: Optionally use simulator to check function, Load design onto FPGA device (cable connects PC to development board), optional logic scope on FPGA check operation at full speed in real environment. Fall 2010 CS Lec01 Intro Page 21 Example Partition, Placement, and Route Idealized FPGA structure: Example Circuit: collection of gates and flip-flops Circuit combinational logic must be covered by 4-input 1-output s. Flip-flops from circuit must map to FPGA flip-flops. (Best to preserve closeness to CL to minimize wiring.) Best placement in general attempts to minimize wiring. Vdd, GN, clock, and global resets are all prewired. Fall 2010 CS Lec01 Intro Page 22

12 Example Partition, Placement, and Route OUT IN Example Circuit: collection of gates and flip-flops A A B B Two partitions. Each has single output, no more than 4 inputs, and no more than 1 flip-flop. In this case, inverter goes in both partitions. Note: the partition can be arbitrarily large as long as it has not more than 4 inputs and 1 output, and no more than 1 flip-flop. Fall 2010 CS Lec01 Intro Page 23 Xilinx FPGAs (interconnect detail) Fall 2010 CS Lec01 Intro Page 24

Project platform: Xilinx ML505-110 Spring 2011 EECS150 - Lec03-FPGA Page 25 FPGA: Xilinx Virtex-5

13 Project platform: Xilinx ML Spring 2011 EECS150 - Lec03-FPGA Page 25 FPGA: Xilinx Virtex-5 XC5VLX110T Virtex-5 die photo Spring 2011 EECS150 - Lec03-FPGA Page 2 A die is an unpackaged part!"#$%&'()

14 Ball Grid Array (BGA) Flip-Chip Package From die to PC board... Copper Heatspreader Thermal Interface Material Underfill Epoxy Adhesive Epoxy* Flip Chip Solder Bump Silicon ie Solder Ball Organic Build-Up Substrate Spring 2011 EECS150 - Lec03-FPGA Page 27!"#$%&'() BANK 40 I/O BANK 40 I/O BANK 40 I/O BANK 40 I/O Figure -3: Banks of I/O placed on chip floor plan BANK 20 I/O BANK 20 I/O CONFIG BANK 20 I/O BANK 20 I/O BANK 40 I/O BANK 40 I/O BANK 40 I/O BANK 40 I/O ug190 03_02130 Virtex-5 XC5VLX30 I/O Banks Colors on this package pinout map to banks. A B C E F G H J K L M N P R T U V W Y AA AB AC A AE AF A B C E F G H J K L M N P R T U V W Y AA AB AC A AE AF Spring 2011 EECS150 - Lec03-FPGA Page 28!"#$%&'()

15 Colors represent different types of resources: Logic Block RAM SP (ALUs) Clocking I/O Serial I/O + PCI A routing fabric runs throughout the chip to wire everything together. Spring 2011 EECS150 - Lec03-FPGA Page 29!"#$%&'() Routing fabric requires many interconnect layers. Spring 2011 EECS150 - Lec03-FPGA Page 30!"#$%&'()

16 Configurable Logic Blocks (CLBs) Slices define regular connections to the switching fabric, and to slices in CLBs above and below it on the die. CLB Slice(1) Switch Matrix Slice(0) CIN CIN UG190_5_01_12205 The LX110T has 17,280 slices. Spring 2011 EECS150 - Lec03-FPGA Page 31 X-Y naming convention for slices X0, X2,... are lower CLB slices. X1, X3,... are upper CLB slices. Y0, Y1,... are CLB column positions. CLB Slice X1Y1 CLB Slice X3Y1 Slice X0Y1 Slice X2Y1 CIN CIN CIN CIN CLB Slice X1Y0 CLB Slice X3Y0 Slice X0Y0 Slice X2Y0 Lower-left corner of the die. UG190_5_02_12205 Spring 2011 EECS150 - Lec03-FPGA Page 32

17 Atoms: 5-input Look Up Tables (s) 5 A[:2] (1) (0) (1). (0). A[:2] Computes any 5- input logic function. Timing is independent of function (0) (1) Latches set during configuration. 33 Spring 2011 EECS150 - Lec03-FPGA Page Virtex-5 -s: Composition of 5-s May be used as one -input ( out) or as two 5-input S ( and 5) Figure 3: Block iagram of a Virtex-5 -Input WP245_03_05100 The LX110T has 9,120 -s - delay is 0.9 ns Combinational logic (post configuration) Spring 2011 EECS150 - Lec03-FPGA Page 34

18 ([:1]) (C[:1]) (B[:1]) A[:1] A[:1] A[:1] The simplest view of a slice SLI (Optional) (Optional) () () (C) (C) (B) (B) Four -s Four Flip-Flops Switching fabric may see combinational and registered outputs. (A[:1]) () A[:1] (Optional) (Optional) (A) (A) An actual Virtex-5 slice adds many small features to this simplified diagram. We show them one by one... Spring 2011 EECS150 - Lec03-FPGA Page 35 SLI Two 7-s per slice... ([:1]) A[:1] F7BMUX (C[:1]) A[:1] (CMUX) (C) (Optional) Extra multiplexers (F7AMUX, F7BMUX) (CX) () (B[:1]) A[:1] F7AMUX Extra inputs (AX and CX) (AMUX) (A[:1]) A[:1] (A) (Optional) (AX) Spring 2011 EECS150 - Lec03-FPGA Page 3

19 Or one 8-s per slice... SLI ([:1]) A[:1] F7BMUX (C[:1]) A[:1] F8MUX Third multiplexer (F8MUX) (CX) (BMUX) (B[:1]) A[:1] F7AMUX (Optional) (B) Third input (BX) (A[:1]) (AX) (BX) () A[:1] Configuring the n of an n-... Spring 2011 EECS150 - Lec03-FPGA UG Page 37 Extra muxes to chose option... Inputs X FE/LAT MUX From eight 5-s... to one 8-. C Inputs CX F7BMUX F8MUX FE/LAT C CMUX C Combinational or registered outs. B Inputs BX FE/LAT B BMUX B Flip-flops unused by s can be used standalone. A Inputs AX (X) F7AMUX A AMUX FE/LAT A Spring 2011 EECS150 - Lec03-FPGA Page 38 UG190_5_25_05050 Flip-flops...

20 Slice flip-flop properties... Output HIGH LOW Each state element may be edge-triggered or latch. X CX BX AX C Output B Output A Output C HIGH LOW B HIGH LOW A HIGH LOW C Reset Type Sync Async B A Clock enable, clock polarity, and set/reset lines in a slice are shared. Each state element may respond differently to set/reset signal. Next: The vertical dimension... Spring 2011 EECS150 - Lec03-FPGA Page 39 From From X S3 (To Next Slice) I3 MUXCY Virtex 5 Verical Logic Carry Chain Block (CARRY4) CO3 O3 MUX/* MUX We can map ripple-carry addition onto carry-chain block. (Optional) From C S2 MUXCY CO2 CMUX/C* From C CX I2 O2 CMUX C (Optional) From B S1 MUXCY CO1 BMUX/B* From B BX I1 O1 BMUX B From A From A AX S0 I0 CYINIT 0 1 MUXCY CIN CO0 O0 (Optional) AMUX/A* AMUX A (Optional) * Can be used if unregistered/registered outputs are free. Spring 2011 CIN (From Previous Slice) EECS150 - Lec03-FPGA Page 40 UG190_5_24_05050 The carry-chain block also useful for speeding up other adder structures and counters.

21 Putting it all together... a SLIL X ROM X Reset Type Sync Async HIGH LOW MUX The previous slides explain all SLIL features. CMUX C C5 C4 C3 C2 C1 CX B B5 B4 B3 B2 B1 BX AX ROM ROM ROM 0/1 C CX B BX A AX Spring 2011 EECS150 - Lec03-FPGA Page HIGH LOW HIGH LOW HIGH LOW C C BMUX B B AMUX A A About 50% of the 17,280 slices in an LX110T are SLILs. The other slices are SLIMs, and have extra features. 41 CIN UG190_5_04_ A[:2] Recall: 5- architecture... (1) (0) (1). (0) (0) (1). A[:2] 32 Latches. Configured to 1 or 0. Some parts of a logic design need many state elements. SLIMs replace normal 5-s with circuits that can act like 5-s, but can alternatively use the 32 latches as RAM, ROM, shift registers. Spring 2011 EECS150 - Lec03-FPGA Page 42

22 Normal - inputs. Memory write address A SLIM -... Memory data input I2 PRAM4/32 SPRAM4/32 L32 L1 RAM I1 ROM MC31 W-W WA7 WA8 Normal 5/- outputs. Memory data input. Control output for chaining s to make larger memories. A 1.1 Mb distributed RAM can be made if all SLIMs of an LX110T are used as RAM. Spring 2011 EECS150 - Lec03-FPGA Page 43 A[7:0] W WE Many RAM configurations possible... 8 () (WE/) RAM25X1S I1 A[:1] WA[8:1] WE I1 A[:1] WA[8:1] WE I1 A[:1] WA[8:1] WE I1 A[:1] WA[8:1] WE SPRAM4 SPRAM4 SPRAM4 SPRAM4 F7BMUX (AX) F7AMUX (CX) A7 (BX) F8MUX O Output Registered Output (Optional) UG190_5_14_05050 Example configuration: Single-port 25b x 1, registered output. A complete list:! Single-Port 32 x 1-bit RAM! ual-port 32 x 1-bit RAM! uad-port 32 x 2-bit RAM! Simple ual-port 32 x -bit RAM! Single-Port 4 x 1-bit RAM! ual-port 4 x 1-bit RAM! uad-port 4 x 1-bit RAM! Simple ual-port 4 x 3-bit RAM! Single-Port 128 x 1-bit RAM! ual-port 128 x 1-bit RAM! Single-Port 25 x 1-bit RAM A 128 x 32b RAM has a 1.1ns access time. Figure 5-14: istributed RAM (RAM25X1S) Spring 2011 EECS150 - Lec03-FPGA Page 44

23 SLIM shift register (one of many). SHIFTIN () 32-bit Shift Register WE SHIFTOUT(31) Address (A[4:0]) 5 MUX UG190_5_1_05050 See Virtex-5 User Guide for an complete list of shift-register types. Spring 2011 EECS150 - Lec03-FPGA Page 45 SLIL vs SLIM... SLIL SLIM Reset Type Sync Reset Type Sync X ROM X Async HIGH LOW MUX I I2 W-W WA7 WA8 PRAM4/32 SPRAM4/32 L32 L1 RAM ROM I1 MC31 X Async HIGH LOW MUX CMUX X C C5 C4 C3 C2 C1 CX B B5 B4 B3 B2 B1 BX AX ROM ROM ROM CIN SLIM adds memory 0/1 C CX B BX A AX HIGH LOW HIGH LOW HIGH LOW C C BMUX B B AMUX A A UG190_5_04_0320 features to s, + muxes. I2 PRAM4/32 SPRAM4/32 L32 L1 RAM I1 ROM MC31 W-W WA7 WA8 I2 PRAM4/32 SPRAM4/32 L32 L1 RAM I1 ROM MC31 W-W WA7 WA8 I2 PRAM4/32 SPRAM4/32 L32 L1 RAM I1 ROM MC31 W-W WA7 WA8 Spring 2011 WE WE EECS150 - Lec03-FPGA CIN Page 4 CI C C5 C4 C3 C2 C1 CX BI B B5 B4 B3 B2 B1 BX AI AX WSGEN 0/1 C CX B BX A AX HIGH LOW HIGH LOW HIGH LOW CMUX C C BMUX B B AMUX A A UG190_5_03_04100

24 Virtex-5 SP48E Slice Efficient implementation of multiply, add, bit-wise logical. LX110T has 4 in a single column. Spring 2011 EECS150 - Lec03-FPGA Page 47 Spring 2011 EECS150 - Lec03-FPGA Page 48

25 To be continued... Throughout the semester, we will look at different Virtex-5 features in-depth. Switch fabric Block RAM SP48 (ALUs) Clocking I/O Serial I/O + PCI Spring 2011 EECS150 - Lec03-FPGA Page 49!"#$%&'()

CS Digital Systems Project Laboratory

CS Digital Systems Project Laboratory CS 194- igital Systems Project Laboratory Lecture 1 Virtex-5 Microarchitecture Not a professor. John is OK. 2008-9- John Lazzaro (www.cs.berkeley.edu/~lazzaro) And also, an introduction to the project.