2.5D interposer, 3DIC and TSV Interconnects Applications, market trends and supply chain evolutions

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1 2.5D interposer, 3DIC and TSV Interconnects Applications, market trends and supply chain evolutions Dr Lionel Cadix CEA LETI Infineon VTI Synopsys Xilinx Micron 2012

2 Outline Introduction Global 3D TSV market forecast Infrastructure & Supply Chain Market & application focus Conclusions and perspectives

3 Introduction

4 Moore is less Transition to 3D The rapid evolution of 3D thinking in the IC community is astonishing Two years ago, the big question was Why 3D? One year ago, the questions were When 3D? and How 3D? In less than a decade from now, we will wonder Why 2D? Despite no more Moore the quest remains Cost? Size? Performance? Which will determine when and how 3D happens

«3 kinds of 3D» Advanced Packaging Platforms

2 Die 3 Die 4 Sensor Middle-End Process Steps

5 «3 kinds of 3D» Advanced Packaging Platforms WL- Optics WL- Capping 3D WLCSP 3DIC 2.5D Interposer Embedded IC Flip Chip WLCSP FO WLP MEMS IC Capping Memory Logic IC Die 1 Die 2 Die 3 Die 4 Sensor Middle-End Process Steps Wafer Bonding TSV RDL Balling Bumping Balling

6 Global 3DIC Market forecast

7 Wafer count (12 eq.) Global TSV Chip Wafer Forecast Breakdown by segment (12 eq. Wafers) Global TSV Chip Wafer Forecast (All 3D Platforms) Breakdown by Segment (12''eq wafers) 10,000,000 Yole Developpement July D Stacked NAND Flash 3D Wide IO Memory 8,000,000 Logic 3D SiP / SoC 6,000,000 3D Stacked DRAM MEMS / Sensors 4,000,000 LED 2,000,000 RF, Power, Analog & Mixed signal Imaging & Optoelectronics

Revenues (M$) 140 2011 Global 3D TSV Revenues Breakdown by top players 2011 global 3D TSV revenues* - Including internal production lines - Breakdown by top players (M$) * Middle-end activity

5D Interposer 60 3D WLCSP 40 20 0 *Other Nemotek, Q-Tech, ITRI, Toyota, Honda Research Institute, Sematech, UMC, Toshiba, TI As of 2011, the top three players for 3D TSV revenues were involved in 3D

8 Revenues (M$) Global 3D TSV Revenues Breakdown by top players 2011 global 3D TSV revenues* - Including internal production lines - Breakdown by top players (M$) * Middle-end activity revenues including TSV etching, Filling, RDL, Bumping, wafer test & wafer level assembly total 3D TSV activity revenues ~ $344 Million 3DIC 2.5D Interposer 60 3D WLCSP *Other Nemotek, Q-Tech, ITRI, Toyota, Honda Research Institute, Sematech, UMC, Toshiba, TI As of 2011, the top three players for 3D TSV revenues were involved in 3D WLCSP activity Xintec is the top player by far, with $130M However, this picture will change soon as important revenues are generated over the next few years with 3DIC and 2.5D Interposer products Copyrights Yole Développement SA. All rights reserved.

3D WLCSP: the Most Mature 3D TSV Platform 3D WLCSP is the preferred solution today for the efficient assembly of small-size optoelectronic chip like CMOS image sensors.

More than 90% of the revenues in this area Toshiba $26.7M 10% 2012 9 2011 3D WLCSP platform Middle-End revenues* JCET/JCAP $21.6M 8% China WLCSP $66.

9 3D WLCSP: the Most Mature 3D TSV Platform 3D WLCSP is the preferred solution today for the efficient assembly of small-size optoelectronic chip like CMOS image sensors. At the moment, it is also the most mature 3D TSV platform, as we estimate the market to be ~ $272M in 2011 for the middle-end processing factories serving this specific market. More than 90% of the revenues in this area Toshiba $26.7M 10% D WLCSP platform Middle-End revenues* JCET/JCAP $21.6M 8% China WLCSP $66.0M 24% Including internal production lines Breakdown by top players (M$) Samsung $18.2M 7% STMicroelectronics $2.3M 1% Others* $5.3M 2% Total = $272M *Others = Oki, G-MEMS, Nemotek, Q-Tech Copyrights Yole Développement SA. All rights reserved. * Middle End activity revenues including TSV etching, Filling, RDL, Bumping, wafer test & wafer level assembly Xintec $130.0M 48% Yole Developpement July 2012 come from low-end and low-resolution CMOS image sensors manufacturing (typically CIF, VGA, 1MPx and 2MPx sensors). Xintec in Taiwan is the leader for 3D WLCSP packaging today, followed by China WLCSP, Toshiba and JCAP. Main features Mostly 200mm wafer-level packaging industrial infrastructure Important investments are still expected from major companies moving to 300mm. Indeed, this move to 12 is necessary to move to the high-end CMOS image sensors market (> 8MPx resolution) where sensors are today on the transition from backside illumination to real 3DIC packaging architecture which we will soon call «3D BSI», where photodiodes are vertically stacked directly onto the DSP / ROIC wafer and connected by means of TSVs.

Wafer count (12''eq. wafers) 2.5D interposer 2010-2017 wafer forecasts breakdown by component/ic type 2.5D Interposer platform wafer forecast breakdown by IC type (12''eq.

5D Camera Interposer Module with system - partitioning - - applications - - are expected - 19,585 to be 41,889 the CPU - - - - 34,184 62,089 98,244 146,623 biggest drivers for the volume adoption of

adopt - the partitioning - 9,734 89,273 approach 223,832using 438,331 2.

10 Wafer count (12''eq. wafers) 2.5D interposer wafer forecasts breakdown by component/ic type 2.5D Interposer platform wafer forecast breakdown by IC type (12''eq.wafers) 3,000,000 Yole Developpement July ,500,000 2,000,000 1,500,000 1,000, , APE/BB (Smartphone) ,641 CIS & 2.5D Camera Interposer Module with system - partitioning - - applications - - are expected - 19,585 to be 41,889 the CPU ,184 62,089 98, ,623 biggest drivers for the volume adoption of 3DIC technology in the next five years APE (Tablet) ,274 59, , , ,461 GPU , , , , ,037 Other The Logic motivations (ASIC, FPGA, ASSP ) to adopt - the partitioning - 9,734 89,273 approach 223,832using 438, D 670,290 Interposers 970,722 are: MEMS (3D Capping) - 1,241 1,899 8,048 31,411 59,825 92, ,943 High Power Better LED (3D electrical Silicon Substrate) performance 4,395 8,759 18,890 45,188 91, , , ,715 RF Devices Better (Filtering, yield IPD etc.) 10,952 13,863 18,869 26,534 35,753 46,422 58,540 77,706 Reduced cost TOTAL (12''eq. Wafers) Copyrights Yole Développement SA. All rights reserved.

The Future 3DIC Market is Driven by Stacked Memories & Logic SOC Applications 3DIC technology is seen today as a new paradigm for the future of the semiconductor industry, as it will enable several

11 The Future 3DIC Market is Driven by Stacked Memories & Logic SOC Applications 3DIC technology is seen today as a new paradigm for the future of the semiconductor industry, as it will enable several more decades of chip evolution at ever lower cost, higher performance and smaller-size features 3DIC Platform Middle-End Revenues by 2017 (M. US$) Breakdown by IC type Power Devices (IGBT, PA, PMU) $172 M 10% Other Logic (ASIC, FPGA, ASSP ) $76 M 5% MEMS/Sensor $87 M 5% DRAM $363 M 22% * Middle-end activity revenues including TSV, Filling, RDL, Bumping, wafer test & wafer level assembly Low-End ASIC $110 M 7% CIS $63 M 4% Total = $1.7B Wide IO Memory $325 M 19% NAND Flash Memory $66 M 4% Logic SoC (APE, BB/APE) $404 M 24% Yole Developpement July D stacked DRAM and 3D Logic SOC applications are expected to be the biggest drivers for the volume adoption of 3DIC technology followed by CMOS image sensors, power devices and MEMS Copyrights Yole Développement SA. All rights reserved.

12 Infrastructure & Supply Chain Analysis

Traditional IC Packaging Supply Chain* * Main business models represented in red Substrate material suppliers (FR4, BT resin, Cu clad, etc ) Package substrate

& Final test «Back-end» Sub-Module / Sub-systems Design & Assembly System / Product Fab-less IC players IDMs (Integrated Device Manufacturers) Wafer foundries

substrate) SiP design houses ODM / EMS / DMS (electronic design & manufacturing services) OEMs (Original Equipment Makers) Front-end related materials

13 Traditional IC Packaging Supply Chain* * Main business models represented in red Substrate material suppliers (FR4, BT resin, Cu clad, etc ) Package substrate laminate suppliers PWB suppliers (motherboard) Design of chip & package Silicon Manufacturing «Front-end» Wafer Level Packaging «Middle -end» Package Assembly & Final test «Back-end» Sub-Module / Sub-systems Design & Assembly System / Product Fab-less IC players IDMs (Integrated Device Manufacturers) Wafer foundries Wafer Bumping houses SiP module houses BE assembly & Test houses Test houses OSATs (Open Source Assembly & Test houses) WLP houses (no need for traditional substrate) SiP design houses ODM / EMS / DMS (electronic design & manufacturing services) OEMs (Original Equipment Makers) Front-end related materials suppliers FE related equipment suppliers BE Packaging materials suppliers BE Packaging equipment suppliers Passive comp. & SMT materials SMT equipment suppliers

Transforming IC Packaging Supply Chain* * Existing business models represented in red, new business models in orange Substrate material suppliers (FR4, BT resin, Cu clad, etc ) Package substrate

14 Transforming IC Packaging Supply Chain* * Existing business models represented in red, new business models in orange Substrate material suppliers (FR4, BT resin, Cu clad, etc ) Package substrate laminate suppliers PWB suppliers (motherboard) Design of chip & package Silicon Manufacturing «Front-end» Wafer Level Packaging «Middle -end» Package Assembly & Final test «Back-end» Sub-Module / Sub-systems Design & Assembly System / Product IDMs (Integrated Device Manufacturers) Fab-smart players (foundry services + focused internal investment in manufacturing & critical IP) Fab-less IC players Wafer foundries Integrated wafer / package manufacturing foundries OSATs (Open Source Assembly & Test houses) WLP houses (no need for traditional substrate) ODM / EMS / DMS (electronic design & manufacturing services) SiP design houses OEMs (Original Equipment Makers) Wafer Bumping houses PCB / PWB houses with Embedded die capability Front-end related materials suppliers FE related equipment suppliers BE Packaging materials suppliers BE Packaging equipment suppliers Passive comp. & SMT materials SMT equipment suppliers

Package substrate laminate suppliers Design Silicon of chip & package Manufacturing

suppliers (motherboard) Sub-Module / Sub-systems Design & Assembly System / Product IDMs

manufacturing & critical IP) Integrated wafer / package manufacturing foundries Fab-less IC

materials suppliers FE related equipment suppliers 15 OEMs (electronic design &

houses) Wafer Bumping houses 2012 ODM / EMS / DMS SiP design houses PCB / PWB houses with

15 Transforming IC Packaging Supply Chain* * Existing business models represented in red, new business models in orange Substrate material suppliers (FR4, BT resin, Cu clad, etc ) Package substrate laminate suppliers Design Silicon of chip & package Manufacturing «Front-end» Wafer Level Packaging Package Assembly & Final test «Middle -end» «Back-end» PWB suppliers (motherboard) Sub-Module / Sub-systems Design & Assembly System / Product IDMs (Integrated Device Manufacturers) Fab-light players (outsourcing + focused investment in manufacturing & critical IP) Integrated wafer / package manufacturing foundries Fab-less IC players Wafer foundries WLP houses (no need for traditional substrate) Front-end related materials suppliers FE related equipment suppliers 15 OEMs (electronic design & manufacturing services) (Original Equipment Makers) OSATs (Open Source Assembly & Test houses) Wafer Bumping houses 2012 ODM / EMS / DMS SiP design houses PCB / PWB houses with Embedded die capability BE Packaging materials suppliers BE Packaging equipment suppliers Passive comp. & SMT materials SMT equipment suppliers

16 3D IC & TSV Market & Application Focus

17 What are the Markets for 3D ICs? Gaming / Graphic application engines High-performance computers / Network & Storage components / Green Data servers Automotive Medical Lower Volumes 3D IC opportunities High-end Multimedia Smart-phones / PMP Wireless Connectivity / Network Center High Volumes High-performance Digital Video Notebooks / MID connectivity devices High-density Solid State Storage & µ-cards 3D integrated ICs will be introduced in a variety of applications, all with their own specifications, challenges and individual roadmaps!

3D TSV Application Segmentation 3D TSV Applications Imaging MEMS & Sensors HB-LED RF, Power, Analog & Mixed Signal

Pressure sensors Si-micro FBAR filters Oscillators µprobes µfluidic / IJ µvalves Fingerprint sensors IR-bolometer Opto

converters Stacked DRAM StackedNAND Flash StackedNOR / PCRAM 3D SiP Wide IO BB CPU / GPU FPGA High.

18 3D TSV Application Segmentation 3D TSV Applications Imaging MEMS & Sensors HB-LED RF, Power, Analog & Mixed Signal Stacked memories Logic 3D- SiP/SoC LED Gyros WLP CIS BSI CIS 3D integrated CIS Wafer level auto-focus Acceleros Pressure sensors Si-micro FBAR filters Oscillators µprobes µfluidic / IJ µvalves Fingerprint sensors IR-bolometer Opto (laser, VCSEL) Micro-mirrors Mobile µ-flash Automotive Projection engine General Lighting PA MOSFET IGBT IPD DC-DC converters Stacked DRAM StackedNAND Flash StackedNOR / PCRAM 3D SiP Wide IO BB CPU / GPU FPGA High. Perf ASICs 3D SoC Baseband / DSP MCU / Processors Touchscreen controller Low-end ASICs PMIC Copyrights Yole Développement SA. All rights reserved.

Global 3DIC & TSV roadmap Hybrid Memory Cube DDR3 stack Stacked Memories Logic 3D SiP/SoC Wide IO stack NAND Flash stack DDR3 stack Ultimate Heterogeneous 3DIC 3D SiP GPU DDR3 CPU MEMS

Logic Digital FPGA FPGA FPGA FPGA FPGA Wide IO Analog Wide IO APE HB-LED modules Power, Analog & RF LED LED LED IPD LED LED LED Driver Driver IGBT & Power MOSFET PA 3D IPD MEMS & Sensors

19 Global 3DIC & TSV roadmap Hybrid Memory Cube DDR3 stack Stacked Memories Logic 3D SiP/SoC Wide IO stack NAND Flash stack DDR3 stack Ultimate Heterogeneous 3DIC 3D SiP GPU DDR3 CPU MEMS ASIC Digital Wide IO APE Analog RF Mem. Digital Analog 3D SoC Logic RF Mem. Logic Digital FPGA FPGA FPGA FPGA FPGA Wide IO Analog Wide IO APE HB-LED modules Power, Analog & RF LED LED LED IPD LED LED LED Driver Driver IGBT & Power MOSFET PA 3D IPD MEMS & Sensors Capping MEMS Capping Sapphire or Silicon MEMS Logic MEMS MEMS ASIC ASIC MEMS Capping Power GaN MOSFET IPD Capping Analog/RF FBAR < BSI CIS BSI CIS DSP + mem CIS DSP SOC CIS SOC CIS 3D WLCSP FSI SOC CIS Imaging & Opto DSP mem SOC CIS LED

20 Silicon/Glass 3D Interposer Technology Segments We identified the following technology segments for 3D interposers: MEMS and sensors 3D capping interposers System partitioning interposers Interposers for CMOS image sensors 3D LED silicon substrates 3D Integrated Passive Devices (IPDs) Miscellaneous interposers «System partitioning» interposers MEMS & sensor 3D capping inteposers 3D LED silicon submounts Miscellaneous interposers Interposers for CMOS image sensors 3D integrated passive devices Copyrights Yole Développement SA. All rights reserved.

21 2012 hottest topic: «System-Partitioning» Interposers Definition and drivers «System-partitioning» Interposers enable the integration of at least one logic IC with one or several memory Ics, and possible even mixed signal or analog ICs They will progressively replace monolithic SoC, or SiP Adoption of «system-partitioning» Interposers is driven by Performance Electrical performance is enhanced by placing the various ICs close to one another and by interconnecting them with very high-density and large IO buses, thus enabling high bandwidth between the neighboring ICs on the interposer From a thermal standpoint, 2.5D integration enables similar benefits to those of 3D integration, without the thermal drawbacks of overheating of 3D integration In addition, «system-partitioning» Interposers can act as heat spreaders across the package surface area Cost Yield Each stacked circuit is built using a specific technology tailored to its function (memory, logic, etc.) Some large logic chips can be cut down into several circuits with higher front-end manufacturing yields Lead applications for «system-partitioning» are GPUs, FPGAs, large ASICs and APE+memory for tablets PCB Silicon interposer «System-partitioning» Interposers are generally large (exceeding 20x20mm²) Memory Logic Analogue BGA Laminate Copyrights Yole Développement SA. All rights reserved.

Interposers for FPGA Focus on Xilinx Virtex 7 HT Last fall, Xilinx announced a single-layer, multi-chip silicon interposer for its 28nm 7 series FPGAs Key features Two million logic cells for a high

22 Interposers for FPGA Focus on Xilinx Virtex 7 HT Last fall, Xilinx announced a single-layer, multi-chip silicon interposer for its 28nm 7 series FPGAs Key features Two million logic cells for a high level of computational performance,and high bandwidth Four slice processed in 28 nm 25 x 31mm, 100 µm thick silicon Interposer 45 um pitch microbumps and 10 µm TSV 35 x 35 mm BGA with 180 µm pitch C4 bumps Even if the infrastructure had been ready for full 3D stacking, the 2.5D Interposer would still have been the right choice for FPGAs since the 10,000 routing connections would have used up valuable chip area, making the chip slices larger and more costly than they are now Courtesy of Xilinx Virtex 7 HT will consist of three FPGA slices and two 28 gbps SerDes chips on an Interposer capable of operating at 2.8 Tb/sec! Source: Yole Developpement & Phil Garrou for imicronews Copyrights Yole Développement SA. All rights reserved.

Interposers for Large CPUs and GPUs Limitation/Bottleneck in conventional 2D architecture Beyond eight cores, processors will lose performance benefits in a 2D configuration.

5D Interposers will be soon be mandatory for increasing the performance of high-performance computers! Power 8 by IBM will be based on 2.5D Interposers Haswel, Intel GPU on 2.

23 Interposers for Large CPUs and GPUs Limitation/Bottleneck in conventional 2D architecture Beyond eight cores, processors will lose performance benefits in a 2D configuration. This is a fundamental bottleneck that IBM and Intel are working on 2D SoC partitioning and use of 2.5D Interposers will be soon be mandatory for increasing the performance of high-performance computers! Power 8 by IBM will be based on 2.5D Interposers Haswel, Intel GPU on 2.5D Interposers for laptops, with lots of on-board memory and an ultra-large data bus IBM Power 7+: four 32nm CMOS multi-core CPU dies are placed side by side on a silicon Interposer. (Courtesy of SemiAccurate.com) Cross-section pictures of an IBM 3D stacked module demonstrator with TSVs in the thinner die (courtesy of Chipworks) Copyrights Yole Développement SA. All rights reserved.

Networking Applications Cisco seriously considering silicon Interposers Because

limit the size of silicon Interposers to a max.

with naked dies mounted on both sides of the Interposer As of Q2/2012, Cisco is

management issues The 3D SiP architecture hosts bare dice on both sides of the

24 Networking Applications Cisco seriously considering silicon Interposers Because higher memory bandwidth is needed for networking applications, and because steppers limit the size of silicon Interposers to a max. of 26x32mm (as estimated by Cisco), Cisco proposes a new architecture: the 3D SiP, with naked dies mounted on both sides of the Interposer As of Q2/2012, Cisco is still building test vehicles with ITRI, and is still concerned with thermal management issues The 3D SiP architecture hosts bare dice on both sides of the Interposer (cross-section drawing and top view), Source: Cisco and ITRI, ECTC Copyrights Yole Développement SA. All rights reserved.

5D is unanimously praised as the solution for this purpose GPU-RAM bandwidth is the key factor for rendering performance Sept 2011, Teiji Yutaka, SVP

25 GPU for Gaming Sony s PS4 (2013) will have its GPU and memory stacked on a 2.5D Silicon Interposer with a 512-wide data bus. This will likely be an AMD chip Future gaming platforms will offer 3D imagery, which requires fast & high bandwidth computing power 2.5D is unanimously praised as the solution for this purpose GPU-RAM bandwidth is the key factor for rendering performance Sept 2011, Teiji Yutaka, SVP Technology Platform, Sony Computer Entertainment An Interposer module for (Yole s assumption) an AMD GPU demonstrator, Courtesy of Global Foundries, Copyrights Yole Développement SA. All rights reserved.

End Application Interposers technical and

segments System partitioning interposers MEMS and

image sensors 3D LED silicon substrates 3D

interposers Mobile/wireless Application processor

with interposer in 2012 Emerging Emerging for RF

PCs Data centers & servers Wired telecom

in 2014 GPUs in 2013, CPUs in 2015 CPUs in 2014

In research phase Wireless telecom infrastructure?

2012 in smart TV BSI with interposer in 2012

26 End Application Interposers technical and marketing segmentation and status Technical segments System partitioning interposers MEMS and sensor 3D capping interposers Interposers for CMOS image sensors 3D LED silicon substrates 3D Integrated Passive Devices (IPDs) Miscellaneous interposers Mobile/wireless Application processor + memory for tablets in 2013 HVM since 2011 BSI with interposer in 2012 Emerging Emerging for RF front-end and DC/DC converters Silicon PoP? Gaming GPUs in CPUs in 2015 HVM since 2011 Industrial and medical PCs Data centers & servers Wired telecom infrastructure FPGA in 2012, High perf processors in 2014 GPUs in 2013, CPUs in 2015 CPUs in 2014 FPGA in 2012, ASICs in 2015 Silicon substrates & IPDs for medical? Voltage regulators. In research phase Voltage regulators. In research phase Wireless telecom infrastructure?? Home consumer (DSC, MP3, TV, white goods) FPGA 2012 in smart TV BSI with interposer in 2012 Aerospace/mil/hi reliability ASICs in 2017 Silicon substrates for high temp operation? Automotive FPGA and ASICs in 2018 Emerging? General lighting Emerging

27 Summary: Interposers expected applications production roadmap CPUs CMOS image sensors APEs (smartphones) APEs (in tablets)? GPUs LED silicon substrates FPGAs, networking, & storage & HDTV ASICs BAW filters, RF devices

28 Conclusion & Perspectives

29 Main Conclusions Market & Applications 3DIC technology is considered today as a new paradigm for the future of the semiconductor industry! 3DIC will enable several more decades of chip evolution at ever lower cost, higher performance and smaller-size features Cost Size 3D stacked DRAM & 3D Logic SOC = biggest drivers for volume adoption of 3DIC technology Today, the market is driven by high-end applications using 2.5D partitioning Interposers Large-die FPGAs and ASICs are on the way to being commercialized for industrial applications, and are also expected to grow in the near future in the gaming and smart TV markets 2013 will likely be the key turning point for the first true implementation of 3DIC technology in significant volume, driven by the commercialization of HMC In terms of value, the 3D TSV market will reach $40B in 2017, growing more than 10 times faster than the global semiconductor industry! Performance

30 Main Conclusions Supply Chain Many supply-chain possibilities for 2.5D/3DIC integration Innovative business model evolutions Leading wafer foundries are now extending to package, assembly & test integrated services Large IDMs have now opened full turnkey manufacturing services to bring key design wins and manufacturing volume from leading IC fabless/fab-light companies in-house Leading packaging, assembly & test houses have the possibility of developing their own 2.5D / 3DIC technology ecosystems For the players unable to develop vertically into front-end/middle-end/back-end assembly & test, there is an urgent need to settle a genuine collaborative ecosystem Key challenge for these future virtual IDM ecosystems To determine the ownership and responsibilities between each party involved in the manufacturing process flow To develop several different flexible supply chains with fair value distribution

31 Thank you for your kind attention! Infineon VTI Xilinx Synopsys Micron CEA LETI 2012

3DIC & TSV interconnects business update

3DIC & TSV interconnects business update ASET presentation. Infineon VTI Xilinx Synopsys Micron CEA LETI 2012 Copyrights Yole Developpement SA. All rights reserved. Fields of Expertise Yole Developpement