EE115C Spring 2013 Digital Electronic Circuits. Mon & Wed 8:00-9:50am BH 5249
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1 EE115C Spring 2013 Digital Electronic Circuits Mon & Wed 8:00-9:50am BH 5249
2 Topics Covered: Introduction to Digital ICs Current equations and parasitic effects of MOS devices Technology and layout of digital circuits The CMOS inverter Static operation (VTC, noise margins) Propagation delay, power Combinational logic and advanced circuit styles Design and sizing (W/L) of logic gates Static, dynamic behavior, and power Interconnect: R, and C Arithmetic blocks (data paths) Sequential logic (latches, flip-flops) Timing analysis EE115C Spring
3 Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT S n+ G DEVICE n+ D EE115C Spring
4 Course Objectives Understand, design, and optimize digital circuits with respect to different quality metrics: Power dissipation Speed Prerequisites: EE115A (analog circuits) M16 (logic design) EE115C Spring
5 Textbook Publisher: Prentice Hall 2003 EE115C Spring
6 EE115C Instructors Instructor Sina Basir-Kazeruni Office hours: Eng-IV (5 th Floor Lounge) Mon 12:00 1:00pm Thu 8:00 10:00am TA Abishek Manian Office hours: Eng-IV (TA Room) Wed 12:00-1:00pm Fri 12:00-1:00pm EE115C Spring
7 EE115C Weekly Schedule * Discussion sessions cover identical material EE115C Spring
8 Online Resources Three places to bookmark: EEWeb Piazza Wiki Grades Q&A Course material EE115C Spring
9 Grades on EEWeb grades EE115C Spring
10 Q&A on Piazza EE115C Spring
11 Submission of assignments Personal queries Before you , think of WHY can t you post the question on Piazza EE115C Spring
12 Create account EE115C Spring
13 Create a wiki account using your UCLA username (EE/SEAS/BOL) EE115C Spring
14 24-hour Account Activation #1: create account #2: us your Username #4: access local pages #3: WAIT 24 hours EE115C Spring
15 Course Material Lecture notes Homeworks CAD tutorials Class project EE115C Spring
16 Schedule and Syllabus Intro, Scaling MOS IV Model MOS RC Model CMOS Inverter VTC Delay Analysis Power Consumption CMOS Logic Gate Sizing Logical Effort Wires, Elmore Delay Midterm Stick Diagrams, Adder Blocks Adders, Layout Design Rules Pass-Transistor Logic Basic Tree Adders Latches and Flip-Flop No Class Setup and Hold Times Timing Analysis Perspectives / Review EE115C Spring
17 Grading Policy & Organization 14% 25% 25% 35% 1% 7 homeworks Project Miderm Final Survey EE115C Spring
18 Gantt Chart Hw #1 Hw #2 Hw #3 Hw #4 Hw #5 Hw #6 Hw #7 Project Midterm Final Exam EE115C Spring
19 Exams: Closed Book Midterm: Mon May 06, 8:00-9:50am 1 page of notes Final: Mon Jun 10, 6:30pm-9:30pm 1 sheet (2 pages) of notes EE115C Spring
20 Lab Sessions Week 2: regular discussion Weeks 8 & 9: extra sessions (project help) project disc = lab start extra labs due Week EE115C Spring
21 Software Cadence software Online documentation and tutorials 90nm CMOS technology (Cadence GPDK) 9 metal layers Important tools / skills Design Capture: Virtuoso Schematic / Layout Editor Circuit Simulation: / Ocean Design Verification (DRC, LVS, Extraction): Assura/QRC (Courtesy: IBM) Updated tutorials (Cadence 6) available on the wiki Old page: EE115C Spring
22 EE115C Design Flow schematic symbols & CDFs schematic Virtuoso simulation Analog Env. models layouts & pcells Vitruoso layout VXL compare results (finish) Assura database verification DRC & LVS RCX simulation Analog Env. models EE115C Spring
23 Anatomy of the Flow: Cadence PDK Database schematic symbols & CDFs schematic Virtuoso simulation Analog Env. models layouts & pcells Vitruoso layout VXL compare results (finish) Assura database verification DRC & LVS RCX simulation Analog Env. models EE115C Spring
24 Anatomy of the Flow: Virtuoso Schematic and Layout Editor schematic symbols & CDFs schematic Virtuoso simulation Analog Env. models layouts & pcells Vitruoso layout VXL compare results (finish) Assura database verification DRC & LVS RCX simulation Analog Env. models EE115C Spring
25 Anatomy of the Flow: Assura Design Verification schematic symbols & CDFs schematic Virtuoso simulation Analog Env. models layouts & pcells Vitruoso layout VXL compare results (finish) Assura database verification DRC & LVS RCX simulation Analog Env. models EE115C Spring
26 Anatomy of the Flow: Simulation Environment schematic symbols & CDFs schematic Virtuoso simulation Analog Env. models layouts & pcells Vitruoso layout VXL compare results (finish) Assura database verification DRC & LVS RCX simulation Analog Env. models EE115C Spring
27 Flow Walkthrough: Enter the Flow 1 schematic symbols & CDFs schematic Virtuoso simulation Analog Env. models layouts & pcells Vitruoso layout VXL compare results (finish) Assura database verification DRC & LVS RCX simulation Analog Env. models EE115C Spring
28 Flow Walkthrough: #1: Schematic Capture 1 schematic symbols & CDFs schematic Virtuoso 2 simulation Analog Env. models layouts & pcells Vitruoso layout VXL compare results (finish) Assura database verification DRC & LVS RCX simulation Analog Env. models EE115C Spring
29 Flow Walkthrough: #2: Circuit Simulation 1 schematic symbols & CDFs schematic Virtuoso 2 simulation Analog Env. models 3 layouts & pcells layout Vitruoso VXL compare results (finish) Assura database verification DRC & LVS RCX simulation Analog Env. models EE115C Spring
30 Flow Walkthrough: #3: Layout Capture 1 schematic symbols & CDFs schematic Virtuoso 2 schematic simulation results 3 layouts & pcells layout Vitruoso VXL compare results (finish) 4 Assura database verification DRC & LVS RCX simulation Analog Env. models EE115C Spring
31 Flow Walkthrough: #4: Design Verification 1 schematic symbols & CDFs schematic Virtuoso 2 schematic simulation results 3 layouts & pcells layout Vitruoso VXL compare results (finish) 4 Assura database verification DRC & LVS RCX 5 simulation Analog Env. models EE115C Spring
32 Flow Walkthrough: #5: Post-Layout Simulation 1 schematic symbols & CDFs schematic Virtuoso 2 schematic simulation results 3 6 layouts & pcells layout Vitruoso VXL compare results (finish) 4 6 Assura database verification DRC & LVS RCX 5 simulation Analog Env. models EE115C Spring
33 Flow Walkthrough: #6: Comparison of Results 1 schematic symbols & CDFs schematic Virtuoso 2 schematic simulation results 3 6 layouts & pcells layout Vitruoso VXL compare results (finish) 4 6 Assura database verification DRC & LVS RCX 5 post-layout simulation results EE115C Spring
34 Online Tutorials: Start from Here (Use Design-Flow Path Later) Tutorial # Content Learning Tutorial 1 Tutorial 2 Tutorial 3 Tutorial 4 Tutorial 5 Tutorial 6 Account and Tool Setup Hierarchical Schematic and Simulation Virtuoso Layout Editing (DRC, LVS) Schematic-driven Layout (Virtuoso XL) Hierarchical Design and Post-Layout Verification Advanced simulation using OCEAN environment Account and Cadence library setup, transistor IV curves. Technology calibration (Ring OSC, FO4), simulator. Layout rules (DRC, LVS), custom standard cell (INVX1). Advanced layout, standard-cell design (NAND2X1). Hierarchical design, post-layout verification. Automating simulations and data measurement. EE115C Spring
35 Assignment 1: Getting Cadence to Work After setting up Cadence (classwiki / Tool setup): Complete Tutorial 1.1 posted on classwiki. Turn in a screenshot ( ee115c.s13@gmail.com) We are looking for this and this EE115C Spring
36 EE115C Spring 2013 Digital Electronic Circuits Lecture 1: Introduction
37 Look Familiar? EE115C Spring
38 A Look Under the Hood Cell Processor Computer that acts like cells in a biological system High-performance distributed computing 10x faster than other CPUs IBM, Sony, Toshiba Let s look back to see how it all started EE115C Spring
39 A Bit of History The First Computer (1832) The Babbage Difference Engine 25,000 parts cost: 17,470 EE115C Spring
40 The First Digital Electronic Computer Zuse Z3 (1941) Binary 5 10 Hz 22b words 2K relays Google images Device: Electromechanical relay EE115C Spring
41 Five Years Later ENIAC (1946) 150kW $500K $6M today Decimal 5M joints hand-soldered 18K tubes Google images Device: Vacuum tube EE115C Spring
42 The First PC Simon (1950) 4 ops: +, x, >, S 2b Reg/ALU $600 Google images Device: Electromechanical relay EE115C Spring
43 What is the Machine s Future? Mr. Berkeley's answer: "Simon has two futures. In first place Simon can grow. With another chassis and some wiring and engineering, the machine will be able to compute decimally. Perhaps in six months more, we may be able to have it working on real problems. In the second place, Simon may start a fad of building baby mechanical brains, similar to the hobby of building crystal radio sets that swept the country in the 1920's." [1956 Berkeley Enterprises Report] EE115C Spring
44 Squee (The Electronic Robot Squirrel) Eye Google images Hand [1956 Berkeley Enterprises Report] EE115C Spring
45 The Transistor Revolution (1948) First transistor Bell Labs (1948) EE115C Spring
46 The First Integrated Circuit (1958) Texas Instruments (Sep 12, 1958) 7/16" wide and containing two transistors, mounted on a bar of germanium (Image courtesy of Texas Instruments, Inc.) EE115C Spring
47 The First Integrated Circuits (1960 s) Bipolar logic (1960 s) ECL 3-input Gate Motorola (1966) EE115C Spring
48 Integrated Electronics BJT IC 1948 (Bell Labs) 1958 (TI) kHz μp 1971 (Intel) EE115C Spring
49 Intel 4004 Microprocessor (1971) 2,300 transistors (12mm 2 ) 108 KHz operation (10mm) EE115C Spring
50
51 Moore s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term, this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000. [G. Moore, Electronics, 1965] EE115C Spring
52
53 Transistors / cm 2 40 years 2,000,000x improvement 100M 4B Courtesy: Broadcom 2M 50K 2K 10μm μm μm nm nm 2012 EE115C Spring
54 Voltage: V DD, V T Size: W, L, t ox EE115C Spring
55 Dennard s Classical MOSFET Scaling (1974) Scaling Factor Device or Circuit Parameter 1/κ κ 1/κ 1/κ 1/κ 1/κ 1/κ 2 1 : Device dimension t ox, L, W : Doping concentration Na : Voltage V : Current I : Capacitance εa/t ox : Delay time/circuit VC/I : Power dissipation/circuit VI : Power density VI/A R. Dennard, JSSC, Oct EE115C Spring
56 Constant E-field Scaling Voltage and size scale by the same factor, S (S > 1) E = V/L = constant Outcomes: More transistors/area 1/S 2 Faster delay 1/S Lower energy/op 1/S 3 Problem: V T scaling (exponential leakage) EE115C Spring
57 Constant E-field Scaling Ended at the 130nm node EE115C Spring
58 Frequency (MHz) Historical Scaling Trends Power density Leakage power Pentium Pentium Pro Pentium 486 Const V DD Const E General Year Courtesy: S. Borkar (Intel) EE115C Spring
59 Technology Scaling is Power Driven Bipolar NMOS CMOS??? power wall power wall power wall CMOS delivered better cost performance It was more energy efficient It improved the integration level EE115C Spring
60 Module Heat Flux (W/cm 2 ) Bipolar Power Wall CMOS Technologies: bipolar, nmos, CMOS Constant voltage scaling: increasing power Courtesy: Roger Schmidt (IBM) EE115C Spring
61 Scaling Scenarios: Fixed V, Fixed E, General Parameter Relation Fixed V Fixed E General W, L, t ox 1/S 1/S 1/S V DD, V T 1 1/S 1/U Area/Device WL 1/S 2 1/S 2 1/S 2 C ox 1/t ox S S S C gate C ox WL 1/S 1/S 1/S k n, k p C ox W/L S S S I sat C ox WV 1 1/S 1/U Current Density I sat / Area S 2 S S 2 /U R on V / I sat Intr. Delay R on C gate 1/S 1/S 1/S Power I sat V 1 1/S 2 1/U 2 P Density Power/Area S 2 1 S 2 /U 2 EE115C Spring
62 General Scaling Size scaling S > Voltage scaling U Voltage scaling slowing down V T determined by leakage t ox also set by leakage Current increasing by stressing silicon EE115C Spring
63 CMOS Scaling is Continuing to Change 1990 s: both V DD and L scaling 2000 s: V DD scaling slowing down, L scaling 2010 s: rate of L scaling slowing down 100 L delayed Energy Efficiency (GOPS/mW) 10 1 L & V DD mostly L Energy efficiency = 1 C sw V DD2 (1+E lk /E sw ) Technology Generation (nm) EE115C Spring
64 More than Moore: [ITRS 2010] EE115C Spring
65 Approaching Atomic Limits Hair 20nm FET Si atom 0.25nm 200,000x 80x 1x EE115C Spring
66 Scaling Toward 10nm Node Bulk/SOI CMOS Multi-gate CMOS Post-Silicon 5 nm 65nm 45nm 32nm 22nm 16nm 5 nm 12nm Technology: alternative structures and materials, post-silicon devices Design: billion transistors, GHz operation Source: K. Cao (ASU) EE115C Spring
67 CMOS Replacement? Replacing CMOS by another more energy efficient technology is a distant prospect now Low-power high-speed CMOS technology is becoming an indispensable, rather than desirable, technology Power is the main challenge we need to address EE115C Spring
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