Design of VLSI Circuits and Systems

Transcription

1 EE M216A Fall 2010 Design of VLSI ircuits and Systems Prof. Dejan Marković University of alifornia, Los Angeles, USA ourse Description This course focuses on advanced concepts of VLSI circuit and system design in state of the art MOS technologies. Topics include: ircuit level optimization using gate size, supply and threshold voltage; layout of circuit blocks optimized for speed, power, or area. Advanced concepts of retiming, place and route will be employed in class projects, in addition to the design of custom blocks. The applications include micro processors, signal and multimedia processors, portable devices, memory and periphery. ourse topics are continuously updated to track unique technological features such as power leakage, interconnect, clock and power distribution, impact of device variability on the design. This quarter, special focus will be given to design optimization and scaling. EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 2 2

2 EE115 vs. EEM216A EE115 (introductory material) Basic transistor and circuit models Basic circuit design styles and logic gates Design of custom blocks (adders, memories, ) EEM216A (advanced material) Transistor models of varying accuracy Design under constraints: power, area, performance, robustness More advanced design techniques Learning challenges in the coming years reating new solutions to challenging design problems EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 3 3 lass Topics Fundamentals Technology and modeling Scaling and limits of scaling Design for nano scale MOS Static MOS, transistor sizing, buffer design, high speed MOS design styles, (dynamic logic) Process variations, leakage Design techniques for low power and low voltage Power minimization at technology, circuit, architecture levels Energy delay optimization Arithmetic ih i circuits i System level issues Timing strategies, logic synthesis lock and power distribution Physical design EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 4 4

3 Teaching Staff Instructor Prof. Dejan Marković Office hours Tu & Th 10:30 11:45am E Eng IV Bldg. MSOL TA Fang Li Yuan Reader TBD Admin Kim H Office: Eng IV EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 5 5 lass Material Textbook: J. Rabaey, A. handrakasan, B. Nikolic, Digital Integrated ircuits: A Design Perspective, (2nd Edition), Prentice Hall, Other books: N. Weste, D. Harris, MOS VLSI Design: A ircuits and Systems Perspective, (3rd Edition), Addison Wesley, A. handrakasan, W. Bowhill, F. Fox, Design of High Performance Microprocessor ircuits, IEEE Press, W.J. Dally and J.W. Poulton, Digital System Engineering, ambridge University Press, B. Wong, A. Mittal, Y. ao, G.W. Starr, Nano MOS ircuit and Physical Design, Wiley Interscience, Selected papers: Available on classwiki Linked from IEEE Xplore ( (need to be logged in to a campus machine) EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 6 6

4 Other Sources ore material IEEE Journal of Solid State ircuits (JSS) IEEE International Solid State ircuits onference (ISS) European Solid State ircuits onference (ESSIR) Symposium on VLSI ircuits (VLSI) ustom Integrated ircuits onference (I) Other conferences and journals AD topics International onference on omputer Aided Design (IAD) Design Automation onference (DA) EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 7 7 lass Organization & Grading Grading: Homeworks (4) 15% Labs (2) 4% Project 30% Midterm 25% Final exam 25% ourse survey 1% Phase 1 lass project Phase 2 Final PPT Week H1 H2 H3 H4 Fri 10/8 Mon 10/18 Fri 10/29 M Wed 11/3 Fri 11/12 L1 Mon L2 Fri S 11/22 11/26 F Fri 12/10 EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 8 8

5 lass Website EEweb: grades only lasswiki: notes, handouts, assignments, AD tools, references, classwiki EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 9 9 lasswiki reate an account: use your ULA username! EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 10 10

6 Homework #0 / Action Items Get an EE account (if you haven t already) Sign up for classwiki Use your ee/seas username to sign up Once you sign up, I need to add you to ee216a group Server and AD tool info is on the wiki EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide AD Tools adence & Synopsys software Phased out Electric software Online documentation and tutorials 90nm MOS technology adence gpdk090 & gsclib & Synopsys generic 90nm library 9 metal layers Important tools / skills from EE115 Design apture: Virtuoso Schematic / Layout Editor ircuit Simulation: Spectre / Ocean Design Verification (DR, LVS, Extraction): Assura/Diva/QR EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 12 12

7 EEM216A Goals Understanding the basic building blocks of VLSI Transistors/Wires Logic Gates and Layout Datapath Blocks Be able to conceptually model a system Logic Optimization State Machine Design (RTL) Be able to build a system (using a subset of the tools) Verilog Modeling Synthesis Place and Route Understanding the constraints and tradeoffs Delay analysis (gates and interconnects) locking methodology System integration issues (Power/Ground routing, Noise) EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide EE M216A.:. Fall 2010 Lecture 1 Digital Integrated ircuit Design: Trends and hallenges Prof. Dejan Marković ee216a@gmail.com

8 Moore s Law In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months He made a prediction that semiconductor industry will double its effectiveness every 18 months The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. ertainly over the short term, this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000. [G. Moore, Electronics, 1965] EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide Moore s Law 1965 EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 16 16

9 Moore s Law 2005 EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide Evolution in omplexity EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 18 18

10 Microprocessor Examples Moore s law Number of transistors Logic density Die size Frequency Power EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide #1: Number of Transistors Transistors on lead microprocessors double every 2 years Transistors (MT) X growth in 1.96 years! Pentium 4 Pentium Pro (P6) Pentium (P5) 486 (P4) 386 (P3) 286 (P2) (P1) Year Source: S. Borkar (Intel) EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 20 20

11 #2: Logic Density Shrinks and compactions meet density goals New micro architectures drop density 1000 Log gic Transistors/mm 2 Logic Density i860 Pentium II (R) 486 Pentium Pro (R) Pentium (R) 2x trend Source: Intel 1 1.5µ 1.0µ 0.8µ 0.6µ 0.35µ 0.25µ 0.18µ 0.13µ EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide #3: Die Size Growth Die size grows by 14% to satisfy Moore s law 100 Die size (mm) 10 Pentium Pro 486 Pentium ~7% growth per year ~2X growth in 10 years Year Source: S. Borkar (Intel) EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 22 22

12 #4: Frequency Lead microprocessor frequency doubles every 2 years Frequency (Mhz) Doubles every 2 years Pentium 4 Pentium Pro Pentium Year Source: S. Borkar (Intel) EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide Processor Frequency Trend Frequency doubles each generation Number of gates/clock reduce by 25% 10, Intel Processor freq IBM Power P scales by 2X per DE generation Gate delays/clock Game over! Mhz 1, S 21164A A Pentium(R) II MP Pentium Pro 601, 603 (R) Pentium(R) ate Delays/ lock G Source: V. De, S. Borkar ISLPED 99 EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 24 24

13 Technology Roadmap (2002) International Technology Roadmap for Semiconductors (ITRS) Year DRAM ½ pitch [nm] MPU transistors/chip 97M 153M 243M 386M 773M 1.55G 3.09G Wiring levels High-perf. phys. gate [nm] High-perf. VDD [V] Local clock [GHz] High-perf. power [W] Low-power phys. gate [nm] Low-power VDD [V] Low-power power [W] Node years: 2007/65nm, 2010/45nm, 2013/32nm, 2016/22nm EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide Technology Scaling ISS data 100 x1.4 / 3 years 1000 κ 0.7 Power Dissipation (W) x4 / 3 years 85 (a) Power dissipation vs. year. 90 Year MPU DSP 95 Power Density (mw/mm 2 ) κ Scaling Factor κ (normalized by 4µm design rule) 10 (b) Power density vs. scaling factor. Source: T. Kuroda EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 26 26

14 New Trend: Parallel Hardware Higher logic throughput, yet lower power Vdd Logic Block 0.7 x Vdd Freq = 1 Throughput = 1 Active Power = 1 SD Lkg Power = 1 Source: S. Borkar (Intel) Logic Block Freq = 0.7 Throughput = 1.4 Logic Block Active Power = 0.7 SD Lkg Power = 0.7 EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide Dual ore Rule of thumb Voltage Frequency Power Performance 1% 1% 3% 0.66% In the same process technology ache ache ore ore ore Source: S. Borkar (Intel) Voltage = 1 Voltage = 15% Freq = 1 Freq = 15% Area = 1 Area = 2 Power = 1 Power = 1 Perf = 1 Perf = ~1.8 EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 28 28

15 Future Multi core Platform Heterogeneous Multi ore Platform SO GP GP GP GP General Purpose ores GP SP GP SP SP GP GP SP GP GP GP GP Special Purpose HW Interconnect fabric Source: S. Borkar (Intel) EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide Software hallenge Source: ITRS 2007 EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 30 30

16 Impact of Process Variations 130nm data (getting worse with scaling) 1.4 Source: S. Borkar (Intel) No ormalized Frequency % Frequency ~30% Leakage Power ~5 10X 5X Normalized Leakage EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide Implications Reliability Extreme variations (Static & Dynamic) will result in unreliable components Impossible to design reliable system as we know today Transient errors (Soft Errors) Gradual errors (Variations) Time dependent (Degradation) Source: S. Borkar (Intel) Test One time factory testing will be out Burn in to catch chip infant mortality will not be practical Test HW will be part of the design Dynamically self test, detect errors, reconfigure, & adapt EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 32 32

17 In a Nut shell 100 BT integration capacity 100 Billion Transistors Billions unusable (variations) Some will fail over time Intermittent failures Source: S. Borkar (Intel) Yet, deliver high performance in the power & cost envelope EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide Parallel Data Processing Power limited technology scaling Increased impact of process variations More leakage power, multiple threshold devices Single dimensional Multidimensional data Multi-core Processors MIMO ommunications Neuroscience IBM / Sony / Toshiba Belkin EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 34 34

18 Energy Delay Optimization Same principle, different optimization goals Processors Maximize i performance V DD scaling Highest V DD required Processors ommunications Minimize energy & area Typically, sensitivity ~ 1 Energy ommunications Neural Neuroscience Power density: 0.8mWmm 2 Aggressive V DD scaling 0 Delay EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide ASIs on The Road to Extinction? EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 36 36

19 The Age of oncurrency and Flexibility UB Pleiades ARM Heterogeneous reconfigurable fabric Xilinx Vertex 4 Intel Montecito ourtesy: J. Rabaey (UB) AMD Dualore NTT Video codec (4 Tensilica cores) IBM/Sony ell Processor EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide FPGAs going Multi core BEE2 compute module 14 x17 22 layer PB ourtesy: J. Wawrzynek (UB) EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 38 38

20 Moore s Law and the Long Term What level? EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide Moore s Law and the Long Term What level? Within your working life? ? When? EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 40 40

21 Silicon Technology Reaches Nanoscale Source: Intel EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide Sub wavelength Optical Lithography EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 42 42

22 5 nm Scaling Toward 10 nm Node Bulk/SOI MOS Multi gate MOS Post Silicon 5 nm 65nm 45nm 32nm 22nm 16nm 12nm Technology: scaling, alternative structures and materials, post silicon devices Design: billion transistors, GHz operation Source: K. ao (ASU) EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide Design of Nanoelectronics [TI] [IBM] arbon Nanotube FET ??? [UB] oming soon EEM216A.:. Fall Lecture D. 1: Markovic Introduction / Slide 44 44

23 Moore s Law hallenge Double transistors every two years Stay within the expected power trend Still deliver the expected performance Power limited it scaling regime Two key issues: Design complexity Power efficiency Looking at solutions to these challenges is what this course is all about! EEM216A.:. Fall 2010 Lecture D. 1: Markovic Introduction / Slide 45 45