Optical Interconnection as an IP Macro of COMS LSIs (OIP)

Transcription

1 Optical Interconnection as an IP Macro of COMS LSIs (OIP) Takashi Yoshikawa, Ichiro Hatakeyama, Kazunori Miyoshi, and Kazuhiko Kurata Optical Interconnection NEC Laboratory, RWCP Tomohiro Kudoh, and Hiroaki Nishi Parallel and Distributed Architecture laboratories, RWCP Junichi Sasaki, Nobuharu Kami, and Takara Sugimoto Photonic and Wireless Device Research Laboratories, NEC Kei Tanaka Product Technology Research Laboratories, NEC Muneo Fukaishi, and Kazuyuki Nakamura Silicon System Research Laboratories, NEC 1. Introduction Optical interconnection as an IP* macro of CMOS LSIs (OIP) *IP: Intellectual Property - Background - Objective - What is an OIP? - Who benefits? 1

2 Background system LSI needs 1-10 Gbps high-speed interface. typical high-speed electrical interface CML, LVDS core logic output with pre-emphasis driver fan out buffer current mode big driver x2 delay big ESD diode board: 0.05 MHz.km cable: 50 MHz.km 50 1 Gbps 5 10 Gbps big ESD diode gain input with equalized receiver Frequency equalizer limiter core logic I/Os consume higher power because current mode and high drivable. Pre-emphasis and/or equalizer consume excessive power. Big ESD protection diodes prevent high-speed operation. Designing PWB is difficult, cable length is limited, determined. Objective Tera-bit throughput switch LSI low-power and high-speed interface by in-package optics core logic LSI package small driver LDD small ESD diode LSI package small fiber: ESD low skew 1 ps/m diode VCSEL PD TIA limiter BW 500 MHz.km core logic Gbps 65 10Gbps PWB, cabling become easier because all high-speed signals are optical. Optical interface is included in the conventional design of CMOS-LSI. 2

3 What is an OIP? OIP : Optical interconnection as an IP macro of CMOS LSI IP (Intellectual Property) : reused functional circuit block Concept of the OIP optical interface CMOS chip fiber connector Optical interface as an in-package optics LEF TLF PADLIB UDL Library files Preparing optical interface as an in-package optics. Integrating it in a conventional CMOS design opt-module new inter LSI market Who benefits? system designer use high-speed optics compact system CMOS vender realize higher-speed I/O I/O 64 Gb/s 4 pair of Array TX, RX, (8 x 1 Gbps) + 8 SER/DES T. Yoshikawa et.al. Photon. Tech. Lett. Vol. 9, 1627, x 540 mm 35 x 35 mm I/O 100 Gb/s Gbps 16 x16 SW with optintaerface 3

4 2. Concept Model - MCM package BASE-SX Network Interface Card MCM type OIP Package 40 x 40 x 6 mm (same as 304-pin QFP) 88 electrical pin Optical Connector (12 MT) ceramic package limiter amp MSM-OEIC LDD VCSEL land for PQFP (SER/DES) P-WG MT receptacle 4

5 Implemented 1000BASE-SX graphic card OIP-LSI NIC TX optical Gb/s 64 x 66 PCI mother board MSM-OEIC output (RX) The ceramic package was expensive and assembly yield was low. The optical interface should be assembled on other small substrate. 3. PETIT Photonic and Electronic Tied InTerface - BGA package with PETIT - PETIT configuration - link budget - LDD in CMOS -TIA - Sub assembly, optics - PETIT connector - BGA substrate 5

6 BGA type OIP Package BGA substrate (35 x 35 mm standard 352-pin) PETIT (8 x 8 mm) cross sectional view heat sink CMOS chip PETIT CMOS fiber connector PETIT Fiber-connector BGA substrate mold (if necessary) All optical and analog chips are assembled on the ceramic substrate. In-package optics Mounting PETIT directly on a BGA substrate. PETITI Configuration 12.5 Gbps full-duplex in 8 x 8 mm size AlN substrate ( 8 x 8 mm ) TIA 12.5 Gb/s full duplex 8 x 8 mm ceramic (AlN) P (typ) 1.2 W (Vdd 3.3 V) VCSEL PD TX : 4 x Gbps 850-nm VCSEL no LDD (included in CMOS) RX: 4 x Gbps MSM-PD (GaAs) TIA (GaAs) 6

7 TX (LDD in CMOS and VCSEL) CMOS: NEC s UR2H (0.25 um) +3.3V VCSEL GND 0.25 um CMOS similar circuit with OETC (cf.t. C. Banwell, et. al. J. Quant. Electron. 29., 635, 93) probe card Gbps) CMOS (probe card: noisy, BW ~ 1. 0 GHz) 8b10b-coded and muxed D0.0 RX (TIA (GaAs) and PD) GaAs: NEC s GES01(0.2um) CMOS: UR2H (0.25 um) MSM PD TIA offset cancelor PETIT TIA(GaAs) amp buffer limitter(cmos) offset cancelor level conv. buffer CMOS level light PETIT socket BW of the socket is ~ 1.5 Gbps RX output of PETIT 7

8 VCSEL PML PD guide hole Optics PETIT and PETIT connector 45 degree mirror housing with v groove guide pin 12 core fiber (GI/50) PETIT connector (surface) (backside) Commercial MT connecter can be used. 4. CMOS - Cross-point switch - Multi channel SERDES 8

9 Cross Point Switch Gb/s 16 x 16 NEC UR2H (0.25 um) x 4 LDD x 4 amplifier x 4 amplifier 16 x 16 crossbar x 4 LDD x 4 LDD x 4 amplifier cross point control x 4 amplifier x 4 LDD V CMOS 8.5 mm 250-um pitch solder bump All high-speed signals are optically Input and output via PETIT Gb/s optical PETIT RX TX 4 4 x 4 amplifier x 4 LDD Multi Channel SERDES 4 x Gb/s SERDES clock tolerance 10b8b 8b10b 1:10 CDR 10:1 CMU x4 x4 deframer deskew framer LDD control NEC UR2H (0.25 um) 312 Mb/s SSTL2 SERDES control logic 8.5 mm coded and multiplexed D0.0 (opt) de-multiplexed and decoded 1,1,0,0 9

10 5. Library files conventional cell-based ASIC design flow CMOS chip BGA package Core logic Soft IP (codec) (deskew) Hard IP (SERDES) (LDD,amp) PETIT HDL TLF LEF UDL PADLIB 6. HDTV Switcher - Block diagram - PWB, lack 10

11 Block Diagram Demonstrating 10-Gb/s interconnection and compact implementation. VIDEO DV 4 x ~2.5 Gbps signal Modulate #0 ~2Gbps Modulate #1 Modulate #2 Y, Pb, Pr elemental signals are modulated OPT ADC ADC ADC 16x16 CP- SW 16x16 CP- SW HDTV Modulate #3 DV 4 x ~2.5 Gbps signal Modulate #0 ~2Gbps Modulate #1 Modulate #2 ADC DAC DAC DAC 4-ch SER/ DES 16x16 CP- SW SW x 7 16x16 CP- SW Modulate #3 DAC PWB, Lack 800-Gbps-I/O / board Gbps-I/O OIP SW chips /board 365 x 270 mm 11

12 7. Summary (1)We developed OIP (2)PETIT realized 12.5 Gb/s duplex optical interface in 8 x 8 mm. (3)100 Gb/s optical I/O chip was developed by using OIP. I/O 64 Gb/s fiber connector 430 x 540 mm optical interface Optical interface as an in-package optics CMOS chip I/O 800 Gb/s 365 x 270 mm LEF TLF PADLIB UDL Library files I/O 100 Gb/s 35 x 35 mm Acknowledgements Tetsuya Yamazaki, Osamu Matsuo, Yuji Akimoto, Watanabe, and Shigeo Sato R&D Support Center, NEC Mitsuru Kurihara Product Technology Research Laboratories, NEC Shunji Doi PWB Division, NEC Electron Devices Jun Kato NEC Tohoku Hideki Tanaka, Takumi Dohmae, and Masami Nanba NEC Engineering Tetsuya Enomoto NSW 12