Digitaalsüsteemide disain

Transcription

1 IAY 6 Digitaalsüsteemide disain Register Transfer Level Design. FSM Synthesis. Alexander Sudnitson Tallinn University of Technology

2 Register Transfer Level The Register Transfer Level (RTL) is characterized by A digital system is viewed as divided into a data path (data subsystem) and control path (controller); The state of data path consists of the contents of a set of registers; The function of the system is performed as a sequence of transition transfers (in one or more clock cycles). A register transfer is a transformation ti performed on a datum while the datum is transferred from one register to another. The sequence of register transfers is controlled by the control path (FSM). A sequence of register transfers is representable by an execution graph. 2

3 Basic units of RT-level design Control CONTROL Control Inputs UNIT Outputs Control Inputs Status Signals Data path Inputs DATA PATH UNIT Data path Outputs 3

4 A word description (example) The design ranges over several levels l of representation. We begin the design process with a word description of an example device. Digital unit performs an operation of computing the greatest common divisor (GCD) of two integers corresponding to Euclid algorithm: The gist of this algorithm is computing the remainder from division of the greater number with the less one and further exchanging the greater number with the less one and this less number with the division remainder. This converging g process is looped until the division remainder is equal to zero. That means the termination of the algorithm with the current less number as the result. 4

5 Block diagram (example) Start Ready OP OP2 DISCRETE SYSTEM ANSW The interface description entity EUCLID is port (START: in BIT; --The first and the second operand bus OP, OP2: in INTEGER range to 255; --Answer is ready signal READY: out BIT; --Answer bus ANSW: out INTEGER range to 255); end EUCLID; 5

6 Behavioral Description architecture COMMON of EUCLID is process -- Temporary variables: variable RG, RG2, temp: INTEGER range to 255; begin -- Wii Waiting for the start: wait on START until START event and START = ; RG := OP; RG2 := OP2; if RG /= RG2 then if RG < RG2 then -- Exchange operands: temp:=rg; RG := RG2; RG2:=temp; end if; while RG /= loop -- Calculation of the reminder: RG := RG rem RG2; if RG /= then temp:=rg; RG := RG2; RG2:=temp; end if; end loop; end if; --Answer output: ANSW <= RG2; READY <= ; end process; end COMMON; 6

7 The flowchart (example) BEGIN START RG := OP; RG2 := OP2; RG = RG2 RG < RG2 RG := RG2; RG2 := RG; Remainder Computation Remainder = READY := ; ANSW := RG2; END 7

8 GCD computation of 5 and 24 OP RG RG RG < RG2 RG := RG2; RG2 := RG; 24 5 Remainder = RG /= RG := RG2; RG2 := RG; 5 9 Remainder = RG /= RG := RG2; RG2 := RG; 9 6 Remainder = RG /= RG := RG2; RG2 := RG; 6 3 Remainder = 3 RG = READY := ; ANSW := 3; OP2 8

9 Data path -- The data path is specified by the set of operations presented in the behavioral descriptions and by the set of basic elements which it will be implemented by. tice that remainder computation chip (or macro) doesn t exist. We need to synthesize it on the next design step basing upon its behavioural description and existing (or virtual) elements of the lower level - e.g. adders, shift registers, counters. It would in its turn lead to appearing the control part of the lower level and so on (top-down design methodology). 9

10 Remainder computation Remainder Computation RG2(7) = L(RG2.); C := C+ ; RG := RG - RG2; RG(8) = RG := RG + RG2; C = R(.RG2); C := C - ;

11 The flowchart BEGIN START RG := OP; RG2 := OP2; RG = RG2 RG < RG2 RG := RG2; RG2 := RG; Remainder Computation RG2(7) = L(RG2.); C := C + ; RG := RG - RG2; RG(8) = RG := RG + RG2; C = R(.RG2); C := C - ; Remainder = READY := ; ANSW := RG2; END

12 Data path -2- Consider in our example the data path that is based upon some ALU which completes four arithmetic operations (addition, subtraction, left shift and right shift) with registers RG and RG2 for storing the intermediate results, with up/down counter and with control buses for data transfer. It is considered that RG and RG2 are Master- Slave registers that allows to exchange their contents during one clock cycle. Input operands are 8-bit wide. For this example it is assumed that input operands are positive and none of them is. te, that RG and RG2 have a sign bit, as remainder computation algorithm deals with negative values as well. 2

13 The structure of GCD device START x x CONTROL UNIT y y FSM X5 y READY y5 y4 y x4 x6 y9 y8 OP RG ALU x x2 OP2 RG2 y y7 y6 x3 Counter y3 y2 x5 DATA PATH UNIT y ANSW 3

14 ALU OP >= OP2 OP < OP2 OP /= OP2 OP = OP2 x2 x Result y8 y9 ALU OP OP2 + L R y8 y9 4

15 Registers and Counter x6 NOR x4 x3 RG S ig n RG S ig n enable y enable y C + y3 C Counter NOR x5 enable y2 5

16 Multiplexers y5 y4 OP ALU RG2 RG Input y7 y6 RG2 Input ALU RG OP2 OP2 ALU RG RG2 Input y5 y4 RG Input ALU RG2 OP y7 y6 6

17 Control bus B 8 y A ANSW() ANSW() ANSW(7) & & & y RG() RG() RG(7) 7

18 Control part At every description level after the (regular) structure of data path is defined it is possible to extract the remaining control part from the current level of behavioral description. Naturally this extracted control part description may be at first only behavioral one and the methods of finite automata synthesis are required for control part (controller) implementation. In this stage it is convenient to represent the extracted control behavior by means of graphscheme of algorithm (GSA). The flowchart corresponding to our algorithm was obtained as the first step of GSA synthesis. In this flowchart simultaneously executed statements are grouped into common blocks. The GSA we got from the flowchart by replacing the computational statements (actions of ALU and counter) with the corresponding control signals (y-s) and the conditions - with binary conditions signals (x-s). 8

19 Graph-scheme of algorithm BEGIN x y7 y5 y y x x2 y6 y4 y y x3 y8 y y9 y2 y x4 y x6 x5 y9 y8 y3 y2 y y END 9

20 Moore type FSM synthesis Step. The construction of marked GSA. At this step, the vertices Begin, End and oerator vertices are marked by the symbols s, s2, as follows: vertices Begin, End are marked by the same symbol s; the symbols s2, s3, mark all operator vertices; all operator verteces should be marked; te that while synthesizing a Moore FSM symbols of states t mark not inputs of vertices following the operator ones but operator vertices. Step2. The construction of transition list (state diagram) of a controller. Y(Spres) Spres X(Spres, Snext) Y(Snext) Snext 2

21 Moore type FSM GSA BEGIN S x y7 y5 y y S2 x x2 y6 y4 y y S3 x3 y9 y2 y S4 y8 y S5 x4 y S6 x6 x5 y9 y8 y3 y2 y S7 y S8 END S 2

22 The transition list (Moore FSM) Present State S S2 S3 S4 S5 Next State S2 S S8 S3 S5 S4 S5 S4 S5 S4 S6 S7 S8 S3 x x Input Conditions x x & x2 x & x2 & x3 x & x2 & x3 x3 x3 x3 x3 x4 x4 & x5 x4 & x5 & x6 x4 & x5 & x6 Output Va lue y7 y5 y y y6 y4 y y y9 y2 y y8 y S6 S7 x5 S8 x5 & x6 y S3 x5 & x6 S7 S5 y9 y8 y3 y2 y S8 S y 22

23 Microoperation and microinstruction Let a microoperation be an elementary indivisible step of data processing in the datapath and let Y be a set of microoperations. Microoperations are induced by the binary signals y,,y T from a controller. To perform the microoperation y i (i =,, T) the signal y i = has to appear at the output y i. g y i pp p y i A set of microoperations executed concurrently in the datapath is called a microinstruction. Thus if β h = {y h,, y h t} is microinstruction, then β h is represented as subset of Y and the microoperations y h,, y h t are executed at the same clock period. The Y t could be empty and we denote such an empty microinstruction Y ( - ). 23