Architecture Synthesis Part 3

Transcription

1 Architecture Synthesis Part 3 SS 211 Christian Plessl Paderborn Center for Parallel Computing University of Paderborn Version

2 Overview high-level hardware synthesis micro-programmed architectures 2

3 translate program/algorithm into dedicated hardware units of translation single basic block (combinational) discussed in chapter Architecture synthesis (Part 1) complete program (sequential) this lecture finite state machine Motivation registers 1: int gcd(int a, int b) {! 2: while(a!= b) {! 3: if(a > b) {! 4: a = a - b;! 5: } else {! 6: b = b - a;! 7: }! 8: }! 9: return a;! 1:}! controller FU FU datapath FSM controls of datapath (FSM actions) datapath sends feedback to FSM (FSM conditions) 3

4 Translating SW to HW High-level Synthesis basic idea: execute control data flow graph control flow graph describes possible execution sequences of basic blocks implement CFG as finite state machine (FSM) data flow graph describes arithmetic operations on basic block level implement data flow graphs as data paths use registers for storing and transferring data between basic blocks finite state machine controller registers FU FU data path 4

5 Example Program: Greatest Common Divider (GCD) 1: int gcd(int a, int b) {! 2: while(a!= b) {! 3: if(a > b) {! 4: a = a - b;! 5: } else {! 6: b = b - a;! 7: }! 8: }! 9: return a;! 1:}! 5

6 Control Data Flow Graph for GCD BB br label %BB1 BB1 %b1 = phi i32 [ %b2, %BB5 ], [ %b, %BB ] %a1 = phi i32 [ %a2, %BB5 ], [ %a, %BB ] br label %BB2 BB4 %b2 = sub i32 %b1, %a2 br label %BB1 BB2 %a2 = phi i32 [ %a1, %BB1 ], [ %a3, %BB4 ] %whilecond = icmp eq i32 %b1, %a2 br i1 %whilecond, label %BB6, label %BB3 BB6 ret i32 %a2 true false false BB3 false %ifcond = icmp sgt i32 %a2, %b1 br i1 %ifcond, label %BB4, label %BB5 true BB5 %a3 = sub i32 %a2, %b1 br label %BB2 generated with Clang/LLVM 6

7 Control Data Flow Graph for GCD BB br label %BB1 BB1 %b1 = phi i32 [ %b2, %BB5 ], [ %b, %BB ] %a1 = phi i32 [ %a2, %BB5 ], [ %a, %BB ] br label %BB2 BB4 %b2 = sub i32 %b1, %a2 br label %BB1 BB2 %a2 = phi i32 [ %a1, %BB1 ], [ %a3, %BB4 ] %whilecond = icmp eq i32 %b1, %a2 br i1 %whilecond, label %BB6, label %BB3 BB6 ret i32 %a2 true false false BB3 false %ifcond = icmp sgt i32 %a2, %b1 br i1 %ifcond, label %BB4, label %BB5 true BB5 %a3 = sub i32 %a2, %b1 br label %BB2 data path predicates (flags) for conditional jumps (input to controller FSM) conditional state transitions (evaluated by controller FSM) phi nodes define registers + input multiplexers (other values are temporary) 7

8 Data Path for GCD ena2 sela2 ena1 sela1 a enb1 selb1 b a2 a1 b1 a2 a1 b1 > == ifcond whilecond input signals from controller output signals to controller data path predicates (flags) phi nodes (registers + input multiplexer) 8

9 Control FSM for GCD / a1 1 whilecond / a26 6 / a12 / a51 5 2!ifcond / a35 / a42!whilecond / a23 4 ifcond / a34 3 edge labels: c / a c = condition for transition, a = action executed during transition 9

10 Transition Table and Actions current state condition next state action - 1 a1 a 1 - b a12 - a1 1-2 whilecond 6 a !whilecond 3 a ifcond 4 a a42 - a3 1-3!ifcond 5 a a51 a2 1 - b2 1 sel a1 en a1 sel a2 en a2 sel b1 en b1 input signals to data path 1

11 Limitations and Potential Improvements limitations of this basic high-level synthesis approach restricted subset of C only (no function calls, memory access, ) limited amount of parallelism (CDFG is executed sequentially) no sharing of operators in data path single cycle execution model (each basic block is executed in exactly one cycle) FSMs can become very complex features of more advanced high-level synthesis methods sharing of operators in data path program transformations to increase parallelism loop pipelining and retiming many tools available commercial: e.g. Impulse C, Mentor Catapult C, AutoESL free/open source: e.g. ROCCC, SPARK, LegUp, C-to-Verilog 11

12 Microprogrammed Architectures two sides of the spectrum for implementing applications CPU: generic fully programmable architecture, application can be easily varied after fabrication ASIC: highly specialized, application is fixed at design time middle ground: Microprogrammed Architectures also tailored to particular application or class of applications but the controller is programmable (instead of a fixed FSM) 12

13 FSMD vs. Microprogrammed Architecture state reg Jump field status Next- State Logic Datapath status Next- Address Logic CSAR Datapath Control Store Microinstruction Command field finite state machine with datapath (FSMD) fixed microprogrammed architecture programmable CSAR (control store address register) corresponds to instruction counter in CPU Schaumont 21 13

14 Microinstruction Encoding microinstruction specifies commands for datapath jump field jump field how to compute address of next microinstruction based on feedback from data path optional address constant address absolute address of microinstruction here: address field width is 12 bits, hence 496 microinstructions can be addressed CSAR bits datapath command next address Command field next Default Jump Jump if carry Jump if no carry Jump if zero CSAR = CSAR + 1 CSAR = address CSAR = cf? address : CSAR + 1 CSAR = cf? CSAR + 1 : address CSAR = zf? address : CSAR Jump if not zero CSAR = zf? CSAR + 1 : address Control Store microinstruction microinstruction datapath command next + address Datapath cf + zf Jump field flags Next Address Logic Next CSAR Schaumont 21 14

15 Command Field Horizontal vs. Vertical Microcode tradeoff between code density and decoding effort horizontal microcode microinstruction directly contains bits to control datapath no decoding required low code density vertical microcode microinstructions contain encoded form of datapath control signals decoding required higher code density Micro-Programmed Controller Datapath Micro-instruction a = 2 * a a = a 1 a = IN IN Vertical Microcode 1 1 Decoder sel1 sel2 alu a Horizontal Microcode / Schaumont 21 15

16 Example: A Microcoded Datapath unused SBUS ALU Shifter Dest Nxt Address Dest SBUS ALU Shifter Address Nxt Register File Input Shift flags Next- Address Logic CSAR Control Store ACC same microinstruction format as in previous example 4 datapath units to be controlled SBUS: select operand ALU: choose ALU operation Shifter: optional bit shift of ALU result Dest: select location for storing the result Schaumont 21 16

17 Example: Microinstruction Encoding Table 5.1 Microinstruction encoding of the example machine Field Width Encoding SBUS 4 Selectsthe operand that willdrive the S-Bus R 11 R5 1 R1 11 R6 1 R2 111 R7 11 R3 1 Input 1 R4 11 Address/Constant ALU 4 Selectsthe operation performed by the ALU ACC 11 ACC S-Bus 1 S-Bus 111 not S-Bus 1 ACC C SBus 1 ACC C 1 11 ACC SBus 11 SBus 1 1 SBus ACC ACC & S-Bus Shifter 3 Selectsthe function ofthe programmable shifter logical SHL(ALU) 1 arith SHL(ALU) 1 logical SHR(ALU) 11 arith SHR(ALU) 1 rotate left ALU 111 ALU 11 rotate right ALU Dest 4 Selectsthe target that willstore S-Bus R 11 R5 1 R1 11 R6 1 R2 111 R7 11 R3 1 ACC 1 R unconnected Nxt 4 Selectsnext-value for CSAR CSAR C 1 11 cf? CSARC 1:Address 1 Address 1 zf? Address : CSAR C 1 1 cf? Address : CSAR C 1 11 zf? CSAR C 1:Address available microinstructions and their encoding Schaumont 21 17

18 Example: How to Encode a Microinstruction how to encode ACC R2? RT-level Instruction ACC < R2 Micro-Instruction Field Encoding SBUS 1 ALU 1 Shifter 111 Dest 1 Nxt Address Micro-Instruction Formation {,1,1,111,1,,} {1,,1111,1,,,,} Micro-Instruction Encoding 1F8 Schaumont 21 18

19 Example: Implementing GCD on this Architecture 1: int gcd(int a, int b) {! 2: while(a!= b) {! 3: if(a > b) {! 4: a = a - b;! 5: } else {! 6: b = b - a;! 7: }! 8: }! 9: return a;! 1:}! ; Command Field Jump Field! ; ! 1: IN -> R ; read a, store in R! 2: IN -> ACC ; read b, store in ACC! 3: Lcheck: R - ACC JUMP_IF_Z Ldone ; check while condition! 4: (R ACC) << 1 JUMP_IF_C Lsmall ; check whether R<ACC,..! 5: R - ACC -> R JUMP Lcheck ; if so, ACC RO -> ACC! 6: Lsmall: ACC - R -> ACC JUMP Lcheck ; else R - ACC -> R! 7: Ldone: JUMP Ldone ; infinite loop, end of prog! Schaumont 21 19

20 Changes (v1..) initial version 2