The RISC-V Base ISA and Standard Extensions

Transcription

1 The RISC-V Base ISA and Standard Extensions 8 th RISC-V Workshop, Barcelona May 7, 2018 Andrew Waterman, SiFive

2 Why Instruction Set Architecture matters Why can t Intel sell mobile chips? 99%+ of mobile phones/tablets are based on ARM s v7/v8 ISA Why can t ARM partners sell servers? 99%+ of laptops/desktops/servers are based on the AMD64 ISA (over 95%+ built by Intel) How can IBM still sell mainframes? IBM 360 is the oldest surviving ISA (50+ years) ISA is the most important interface in a computer system ISA is where software meets hardware 2

3 Open Software/Standards Work! Field Standard Free, Open Impl. Proprietary Impl. Networking Ethernet, TCP/IP Many Many OS Posix Linux, FreeBSD M/S Windows Compilers C gcc, LLVM Intel icc, ARMcc Databases SQL MySQL, PostgresSQL Oracle 12C, M/S DB2 Graphics OpenGL Mesa3D M/S DirectX ISA?????? x86, ARM, IBM360 Why not have successful free & open standards and free & open implementations, like other fields? Dominant proprietary ISAs are not great designs 3

4 What is RISC-V? A high-quality, license-free, royalty-free RISC ISA specification originally designed at UC Berkeley Standard maintained by the non-profit RISC-V Foundation Suitable for all types of computing system, from microcontrollers to supercomputers Numerous proprietary and open-source cores Experiencing rapid uptake in industry and academia Supported by a growing shared software ecosystem A work in progress 4

5 RISC-V Origins In 2010, after many years and many projects using MIPS, SPARC, and x86 as the bases of research at Berkeley, it was time to choose an ISA for next set of projects Obvious choices: x86 and ARM 5

6 Intel x86 AAA Instruction ASCII Adjust After Addition AL register is default source and destination If the low nibble is > 9 decimal, or the auxiliary carry flag AF = 1, then Add 6 to low nibble of AL and discard overflow Increment high byte of AL Set CF and AF Else CF = AF = 0 Single byte instruction 6

7 ARM v7 LDMIAEQ Instruction LDMIAEQ SP!, {R4-R7, PC} LoaD Multiple, Increment-Address Writes to 7 registers from 6 loads Only executes if EQ condition code is set Writes to the PC (a conditional branch) Can change instruction sets Idiom for "stack pop and return from a function call" 7

8 RISC-V Origin Story x86 impossible IP issues, too complex ARM mostly impossible no 64-bit, IP issues, complex So we started 3-month project in summer 2010 to develop our own clean-slate ISA Principal designers: Andrew Waterman, Yunsup Lee, Dave Patterson, Krste Asanovic Four years later, we released the frozen base user spec First public specification released in May 2011 Several publications, many tapeouts, lots of software along the way 8

9 Our Goals for a Universal ISA Works well with existing software stacks, languages Is native hardware ISA, not virtual machine/andf Suits all sizes of processor, from smallest microcontroller to largest supercomputer Suits all implementation technologies: FPGA, ASIC, full-custom,?? Suits all microarchitectural styles: microcoded, in-order, decoupled, out-of-order, single-issue, superscalar, Supports extensive customization to act as base for customized accelerators Stable: not changing, not disappearing 9

10 The RV32I Base Instruction Set Architecture 8 th RISC-V Workshop, Barcelona, Catalonia May 7, 2018

11 RV32I Architectural State general-purpose registers, x1-x31 (x0 is hardwired to 0), plus pc Registers are 32 bits wide => 1024 bits of architectural state

12 RV32I Instruction Formats Instructions all 32-bits wide; must be 32-bit aligned in memory 4 base formats (R/I/S/U) + 2 immediate-encoding variants (B/J) Register specifiers (rs2/rs1/rd) always in same place R I S B U J 12

13 RV32I Arithmetic and Logical Operations Most arithmetic instructions use R-type format Perform the computation rs1 OP rs2 and write result to rd There are 10 of them: Arithmetic: ADD, SUB Bitwise: AND, OR, XOR Shifts: SLL, SRL, SRA Comparisons: SLT (rd = rs1 < rs2? 1 : 0), SLTU (same, but unsigned) 13

14 RV32I Arithmetic and Logical Operations Also have register-immediate forms using I-type format Perform the computation rs1 OP imm and write result to rd Same ones as R-type, but no need for SUB Arithmetic: ADDI Bitwise: ANDI, ORI, XORI Shifts: SLLI, SRLI, SRAI Comparisons: SLTI, SLTIU Immediate is always sign-extended (even when it represents an unsigned quantity) 14

15 RV32I Arithmetic and Logical Operations 15

16 RV32I Memory Access Instructions Loads also use I-type format Compute address rs1 + imm, read from memory, write result to rd LB, LH, LW: load byte (8b), load halfword (16b), load word (32b) LB and LH sign-extend the quantity before writing rd LBU, LHU (load byte unsigned, load halfword unsigned) zero-extend 16

17 RV32I Memory Access Instructions Stores use S-type format Compute address rs1 + imm; write contents of rs2 to memory SW stores all 32 bits of rs2; SB and SH store lower 8b/16b Note, imm[4:0] moves to bits 11:7 to accommodate rs2 17

18 RV32I Addressing Two U-type instructions: LUI (Load Upper Immediate) supports global addressing lui t0, 0x12345 # t0 = 0x lw t0, 0x678(t0) # t0 = Mem[0x ] Also use LUI + ADDI to generate any 32-bit constant AUIPC (Add Upper Immediate to PC) supports PC-relative addressing auipc t0, 0x12345 # t0 = pc + 0x lw t0, 0x678(t0) # t0 = Mem[pc + 0x ] 18

19 RV32I Conditional Branches Branches use B-type format Same as S-type format, except immediate scaled by 2 (can only branch to even-numbered addresses) Supports ISA extensions with instruction lengths in multiples of 2 bytes Compare rs1 and rs2; if true, set pc := pc + imm; else fall through Equality (BEQ/BNE), magnitude (BLT/BGE/BLTU/BGEU) 19

20 RV32I Unconditional Jumps JAL (Jump and Link) is the only J-type instruction Sets rd := pc + 4; sets pc := pc + imm (±1 MiB range) When rd=x0, it s just a jump; when rd=x1, it s a function call Then sets pc := pc + imm JALR (Jump and Link Register) uses I-type format Sets rd := pc + 4; sets pc := rs1 + imm Use for returns (rd=x0, rs1=x1), indirect calls (rd=x1), table jumps Use with LUI/AUIPC to call any 32-bit address 20

21 The Rest of RV32I FENCE for memory ordering (see Memory Model talk later today) FENCE.I for self-modifying code ECALL for system calls EBREAK for breakpoints CSRRx to access control and status registers (see Priv Arch talk) 21

22 RISC-V Specifies Three Base ISAs Besides RV32I RV32E (E=Embedded): Same as RV32I, but only registers x0-x15 are present. Accessing x16-x31 causes an illegal-instruction trap. Removes 512 bits of state; helps implementations sensitive to regfile cost RV64I: 64-bit address variant Expands the x-registers and the pc to 64 bits Adds new load and store instructions: LWU, LD, SD Existing arithmetic instructions now operate on full 64-bit registers New arithmetic instructions that operate on lower 32 bits of registers and produce a 32-bit result sign-extended to 64 bits: ADDW, SUBW, SLLW, SRLW, SRAW, ADDIW, SLLIW, SRLIW, SRAIW RV128I: 128-bit address variant; follows same pattern as RV64I 22

23 The M Standard Extension for Integer Multiplication and Division 8 th RISC-V Workshop, Barcelona, Catalonia May 7, 2018

24 The M Extension for Integer Multiply/Divide Multiply/divide not part of base ISA Not always needed; sometimes too costly M extension adds these features with 8 R-type instructions Instruction Meaning. mul rd, rs1, rs2 rd = rs1 rs2 mulh rd, rs1, rs2 rd = (sext(rs1) sext(rs2)) >> XLEN mulhu rd, rs1, rs2 rd = (zext(rs1) zext(rs2)) >> XLEN mulhsu rd, rs1, rs2 rd = (sext(rs1) zext(rs2)) >> XLEN div rd, rs1, rs2 rd = rs1 rs2 rem rd, rs1, rs2 rd = rs1 % rs2 divu rd, rs1, rs2 rd = rs1 uns rs2 remu rd, rs1, rs2 rd = rs1 % uns rs2 24

25 The A Standard Extension for Atomic Memory Operations 8 th RISC-V Workshop, Barcelona, Catalonia May 7, 2018

26 The A Extension for Atomic Memory Operations Loads/stores can t scalably support multiprocessor synchronization A extension provides synchronization primitives in two forms: Load-reserved/Store-conditional Atomic fetch-and-ϕ 26

27 Load-reserved, Store-conditional Splits an atomic read-modify-write operation into three phases: Load data, and acquire reservation on the address Compute new value Store new value, only if reservation still held Store may fail, so sequence needs to be retried Writes rd with zero on success or nonzero on failure Forward progress guaranteed for certain restricted sequences Instruction Meaning. lr.w rd, (rs1) rd = M[rs1]; reserve M[rs1] 27 sc.w rd, rs2, (rs1) if still reserved: M[rs1] = rs2; rd = 0 otherwise: rd = nonzero

28 Load-reserved, Store-conditional Example: atomically decrement a variable if it s not zero retry: lr.w t0, (a0) beqz t0, done addi t0, t0, -1 sc.w t1, t0, (a0) bnez t1, retry done: 28

29 Atomic Memory Operations LR/SC can implement any single-word atomic primitive But doesn t scale well to highly parallel systems AMOs can be implemented more scalably: send operation to the data, rather than moving the data around Instruction Meaning. amoswap.w rd, rs2, (rs1) t = M[rs1]; M[rs1] = rs2; rd = t amoadd.w rd, rs2, (rs1) t = M[rs1]; M[rs1] = t + rs2; rd = t amoand.w rd, rs2, (rs1) t = M[rs1]; M[rs1] = t & rs2; rd = t amoor.w rd, rs2, (rs1) t = M[rs1]; M[rs1] = t rs2; rd = t amoxor.w rd, rs2, (rs1) t = M[rs1]; M[rs1] = t ^ rs2; rd = t amomin.w rd, rs2, (rs1) t = M[rs1]; M[rs1] = min(t, rs2); rd = t amomax.w rd, rs2, (rs1) t = M[rs1]; M[rs1] = max(t, rs2); rd = t amominu.w rd, rs2, (rs1) t = M[rs1]; M[rs1] = min u (t, rs2); rd = t amomaxu.w rd, rs2, (rs1) t = M[rs1]; M[rs1] = max u (t, rs2); rd = t 29

30 Memory Ordering AMOs and LR/SC can be marked acquire, release, both, or neither Informally: Acquire: the AMO is ordered before later memory accesses Release: the AMO is ordered after preceding memory accesses Both: the AMO is sequentially consistent Neither option useful for associative reductions See Memory Model talk later today 30

31 The F and D Standard Extensions for Single- and Double-Precision Floating-Point 8 th RISC-V Workshop, Barcelona, Catalonia May 7, 2018

32 F/D extensions add new architectural state 32 FLEN=32 for F FLEN=64 for D

33 Floating-point Loads/Stores Need new loads & stores to transfer data to/from F-registers Same instruction formats as integer loads (I-type), stores (S-type) Instruction Meaning. flw rd, imm(rs1) Load single-precision float into f[rd] fsw rs2, imm(rs1) Store single-precision float from f[rs2] fld rd, imm(rs1) fsd rd, imm(rs1) Load double-precision float into f[rd] Store double-precision float from f[rs2] Also have instructions to move between f and x registers 33

34 Floating-point Arithmetic Most FP arithmetic operations use R-type format Instruction Meaning. fadd.s rd, rs1, rs2 rd = rs1 + rs2, single-precision fsub.s rd, rs1, rs2 rd = rs1 - rs2, single-precision fmul.s rd, rs1, rs2 rd = rs1 rs2, single-precision fdiv.s rd, rs1, rs2 rd = rs1 rs2, single-precision fsqrt.s rd, rs1 rd = sqrt(rs1), single-precision fmin.s rd, rs1, rs2 rd = min(rs1, rs2), single-precision fmax.s rd, rs1, rs2 rd = max(rs1, rs2), single-precision Rounding mode can be specified statically on each instruction or taken from dynamic rounding mode register in fcsr D extension adds double-precision versions of all of these 34

35 Floating-point Arithmetic: Fused Mul/Add Fused multiply-add instructions need new R4 instruction format Instruction Meaning. fmadd.s rd, rs1, rs2, rs3 rd = rs1 rs2 + rs3 fmsub.s rd, rs1, rs2, rs3 rd = rs1 rs2 - rs3 fnmadd.s rd, rs1, rs2, rs3 rd = -rs1 rs2 - rs3 fnmsub.s rd, rs1, rs2, rs3 rd = -rs1 rs2 + rs3 D extension adds double-precision versions of all of these 35

36 Floating-point Sign Injection Unusual feature of RISC-V ISA Forms new FP number by taking exponent/mantissa from rs1 but with new sign bit Instruction Meaning. fsgnj.s rd, rs1, rs2 rd = rs1, but with sign of rs2 fsgnjn.s rd, rs1, rs2 rd = rs1, but with sign of (-rs2) fsgnjx.s rd, rs1, rs2 rd = rs1, but with sign of (rs1 rs2) fsgnj implements move when rs1=rs2 fsgnjn implements negate when rs1=rs2 fsgnjx implements absolute value when rs1=rs2 36

37 Other Floating-Point Instructions Conversions between single and double Conversions to and from integer Integer operands use x-registers Comparisons (=, <, ) write Boolean result to x-register Use in conjunction with integer BEQ/BNE to branch on FP comparison Classify Is a number NaN, Inf, normal, subnormal, etc. 37

38 What s not in the F/D Extensions No traps on IEEE 754 exceptions Simplifies precise exceptions for in-order pipelines: allows FP operations to commit before they complete To act on IEEE 754 exceptions, read FCSR and branch No NaN-payload propagation (not required by IEEE 754; saves HW) 38

39 The C Standard Extension for Compressed Instructions 8 th RISC-V Workshop, Barcelona, Catalonia May 7, 2018

40 The C Extension for Compressed Instructions Problem: 32-bit instruction encoding is not very dense Three most popular instructions in GNU C Library (2.5% of total) jalr x0, 0(ra) addi a0, s0, 0 addi a0, x0, Return from subroutine Move s0 to a0 Move zero to a0 14 of 24 nibbles are zero! 40

41 The C Extension for Compressed Instructions Problem: 32-bit instruction encoding is not very dense Solution: 16-bit representation of most popular instructions Key observations: Locality: ⅔ of references are to ¼ of the registers Few unique operands: half of all instructions are destructive Small immediate operands: half need only 5 bits A few opcodes dominate (addi + lw + sw = 50%) 41

42 What s in the C Extension: Arithmetic RVC Instruction Expands to Notes. c.addi rd, imm addi rd, rd, imm Add immediate c.li rd, imm addi rd, x0, imm Load immediate c.addi4spn rd, imm addi rd, sp, imm Address the stack c.addi16sp imm addi sp, sp, imm [De]allocate stack c.add rd, rs add rd, rd, rs Add registers c.mv rd, rs add rd, x0, rs Move register c.slli rd, imm slli rd, rd, imm Shift left Also several instructions constrained to registers x8-x15: c.srli, c.srai, c.andi, c.sub, c.xor, c.or, c.and 42

43 What s in the C Extension: Loads/Stores RVC Instruction Expands to Notes. c.lw rd, imm(rs) lw rd, imm(rs) Regs x8-x15 only c.sw rs2, imm(rs1) sw rs2, imm(rs1) Regs x8-x15 only c.lwsp rd, imm lw rd, imm(sp) Load from stack c.swsp rs, imm sw rs, imm(sp) Store to stack Also instructions for floating-point loads and stores: c.flw, c.fsw, c.flwsp, c.fswsp, c.fld, c.fsd, c.fldsp, c.fsdsp 43

44 What s in the C Extension: Control Flow RVC Instruction Expands to Notes. c.j offset jal x0, offset Unconditional jump c.jal offset jal ra, offset Call function c.jr rs jalr x0, 0(rs) Return; table jump c.jalr rs jalr ra, 0(rs) Indirect call c.beqz rs, imm beq rs, x0, imm Regs x8-x15 only c.bnez rs, imm bne rs, x0, imm Regs x8-x15 only 44

45 What s not in the C extension No Load-Multiple/Store-Multiple instructions 45 int foo(int x) { return bar() + x; } With LdM/StM swm mv jal add lwm ret {s0, ra},-16(++sp) s0,a0 ra,bar a0,a0,s0 {s0, ra},(sp++)16 Without LdM/StM addi sp,sp,-16 sw s0,8(sp) sw ra,12(sp) mv s0,a0 jal ra,bar add a0,a0,s0 lw ra,12(sp) lw s0,8(sp) addi sp,sp,16 ret

46 What s not in the C extension Use shared prologue/epilogue routines instead of LdM/StM Same code-size savings (slight increase in dyn. instr. count) riscv_save_1: int foo(int x) { return bar() + x; } With shared prologue/epilogue jal mv jal add jal t0, riscv_save_1 s0,a0 ra,bar a0,a0,s0 x0, riscv_restore_1 addi sp,sp,-16 sw s0,8(sp) sw ra,12(sp) jr t0 riscv_restore_1: lw s0,8(sp) lw ra,12(sp) addi sp,sp,16 ret 46

47 C Extension: Static Code Size C extension makes RISC-V code very compact 180% 160% 140% 120% 100% 80% 60% 40% 20% 0% 100% 32-bit ISAs 140% 126% 136% 101% 173% 126% 180% 160% 140% 120% 100% 80% 60% 40% 20% 0% 64-bit ISAs 169% 141% 131% 129% 100% RV64C RV64 X86-64 ARMv8 MIPS64 Corpus: SPEC CPU2006 (n.b. these results use shared prologue/epilogue routines, saving 4%) 47

48 Questions? 8 th RISC-V Workshop, Barcelona, Catalonia May 7, 2018